Lines Matching refs:L
411 #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
419 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
431 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
437 #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
482 #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
491 #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
503 #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
524 #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
542 #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
587 #define BNX2_PCI_VPD_ADDR_FLAG_SL 0L
606 #define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
624 #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
779 #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
789 #define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8)
800 #define BNX2_MISC_CFG_LEDMODE_MAC_XI (0L<<8)
821 #define BNX2_MISC_ID_BOND_ID_X (0L<<0)
926 #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
938 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
945 #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1118 #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
1306 #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0)
1323 #define BNX2_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4)
1340 #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8)
1380 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16)
1389 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22)
1394 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24)
1399 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26)
1404 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28)
1409 #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30)
1493 #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0)
1518 #define BNX2_MISC_OTP_CMD1_FMODE_IDLE (0L<<0)
1539 #define BNX2_MISC_OTP_CMD2_DOSEL_0 (0L<<16)
1715 #define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0)
1720 #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3)
1727 #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11)
1761 #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15)
1766 #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5)
1769 #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6)
1774 #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8)
1779 #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10)
1810 #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI (0L<<0)
1833 #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
1847 #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
1861 #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
1879 #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
1934 #define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT (0L<<0)
1943 #define BNX2_NVM_CFG4_FLASH_VENDOR_ST (0L<<3)
1946 #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0L<<4)
1955 #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0L<<0)
2008 #define BNX2_DMA_CONFIG_MAX_PL_128B_XI (0L<<12)
2013 #define BNX2_DMA_CONFIG_MAX_RRS_128B_XI (0L<<16)
2098 #define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT (0L<<4)
2101 #define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT (0L<<5)
2125 #define BNX2_DMA_TAG_RAM_00_MASTER_CTX (0L<<4)
2132 #define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG (0L<<7)
2141 #define BNX2_DMA_TAG_RAM_01_MASTER_CTX (0L<<4)
2148 #define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG (0L<<7)
2157 #define BNX2_DMA_TAG_RAM_02_MASTER_CTX (0L<<4)
2164 #define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG (0L<<7)
2173 #define BNX2_DMA_TAG_RAM_03_MASTER_CTX (0L<<4)
2180 #define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG (0L<<7)
2189 #define BNX2_DMA_TAG_RAM_04_MASTER_CTX (0L<<4)
2196 #define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG (0L<<7)
2205 #define BNX2_DMA_TAG_RAM_05_MASTER_CTX (0L<<4)
2212 #define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG (0L<<7)
2221 #define BNX2_DMA_TAG_RAM_06_MASTER_CTX (0L<<4)
2228 #define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG (0L<<7)
2237 #define BNX2_DMA_TAG_RAM_07_MASTER_CTX (0L<<4)
2244 #define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG (0L<<7)
2253 #define BNX2_DMA_TAG_RAM_08_MASTER_CTX (0L<<4)
2260 #define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG (0L<<7)
2269 #define BNX2_DMA_TAG_RAM_09_MASTER_CTX (0L<<4)
2276 #define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG (0L<<7)
2285 #define BNX2_DMA_TAG_RAM_10_MASTER_CTX (0L<<4)
2292 #define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG (0L<<7)
2301 #define BNX2_DMA_TAG_RAM_11_MASTER_CTX (0L<<4)
2308 #define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG (0L<<7)
2416 #define BNX2_CTX_COMMAND_PAGE_SIZE_256 (0L<<16)
2461 #define BNX2_CTX_LOCK_TYPE_VOID_XI (0L<<0)
2597 #define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
2651 #define BNX2_EMAC_LED_ACTIVITY_SEL_0 (0L<<17)
2724 #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
2725 #define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
2870 #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
2932 #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
3265 #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START (0L<<13)
3273 #define BNX2_RPM_RC_CNTL_16_COMP_EQUAL (0L<<16)
3297 #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START (0L<<13)
3305 #define BNX2_RPM_RC_CNTL_17_COMP_EQUAL (0L<<16)
3329 #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START (0L<<13)
3337 #define BNX2_RPM_RC_CNTL_18_COMP_EQUAL (0L<<16)
3361 #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START (0L<<13)
3369 #define BNX2_RPM_RC_CNTL_19_COMP_EQUAL (0L<<16)
3393 #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
3401 #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
3429 #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI (0L<<13)
3437 #define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI (0L<<16)
3463 #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI (0L<<13)
3471 #define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI (0L<<16)
3497 #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI (0L<<13)
3505 #define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI (0L<<16)
3531 #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI (0L<<13)
3539 #define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI (0L<<16)
3565 #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI (0L<<13)
3573 #define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI (0L<<16)
3599 #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI (0L<<13)
3607 #define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI (0L<<16)
3633 #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI (0L<<13)
3641 #define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI (0L<<16)
3667 #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI (0L<<13)
3675 #define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI (0L<<16)
3701 #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI (0L<<13)
3709 #define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI (0L<<16)
3735 #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI (0L<<13)
3743 #define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI (0L<<16)
3769 #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI (0L<<13)
3777 #define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI (0L<<16)
3803 #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI (0L<<13)
3811 #define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI (0L<<16)
3837 #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI (0L<<13)
3845 #define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI (0L<<16)
3871 #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI (0L<<13)
3879 #define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI (0L<<16)
3905 #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI (0L<<13)
3913 #define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI (0L<<16)
3956 #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
4017 #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
4057 #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
4176 #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI (0L<<0)
4181 #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI (0L<<2)
4318 #define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
4372 #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
4395 #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
4416 #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
4437 #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
4483 #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
4598 #define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
4628 #define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
4720 #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0 (0L<<2)
4725 #define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
4730 #define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
4738 #define BNX2_TDMA_CONFIG_OFIFO_CMP_3 (0L<<19)
4742 #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI (0L<<20)
4750 #define BNX2_TDMA_CONFIG_BYTES_OST_512_XI (0L<<24)
4758 #define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI (0L<<28)
4819 #define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
4849 #define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19)
4884 #define BNX2_HC_CONFIG_SB_ADDR_INC_64B (0L<<24)
4946 #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
5209 #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
5221 #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
5234 #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
5240 #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
5243 #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
5246 #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
5249 #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
5252 #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
5261 #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
5264 #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
5700 #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
5709 #define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
5795 #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
5804 #define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
5890 #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
5898 #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
5921 #define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
5942 #define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
6036 #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
6044 #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
6067 #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6088 #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6109 #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6202 #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
6210 #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
6233 #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
6374 #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
6383 #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)