Lines Matching refs:tp
91 #define tg3_flag(tp, flag) \ argument
92 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
93 #define tg3_flag_set(tp, flag) \ argument
94 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define tg3_flag_clear(tp, flag) \ argument
96 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
129 #define TG3_MAX_MTU(tp) \ argument
130 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
136 #define TG3_RX_STD_RING_SIZE(tp) \ argument
137 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
140 #define TG3_RX_JMB_RING_SIZE(tp) \ argument
141 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
155 #define TG3_RX_STD_RING_BYTES(tp) \ argument
156 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
157 #define TG3_RX_JMB_RING_BYTES(tp) \ argument
158 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
159 #define TG3_RX_RCB_RING_BYTES(tp) \ argument
160 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
175 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ argument
176 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
178 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ argument
179 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
194 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD argument
196 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) argument
200 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset) argument
202 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD) argument
212 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3) argument
213 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1) argument
468 static void tg3_write32(struct tg3 *tp, u32 off, u32 val) in tg3_write32() argument
470 writel(val, tp->regs + off); in tg3_write32()
473 static u32 tg3_read32(struct tg3 *tp, u32 off) in tg3_read32() argument
475 return readl(tp->regs + off); in tg3_read32()
478 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) in tg3_ape_write32() argument
480 writel(val, tp->aperegs + off); in tg3_ape_write32()
483 static u32 tg3_ape_read32(struct tg3 *tp, u32 off) in tg3_ape_read32() argument
485 return readl(tp->aperegs + off); in tg3_ape_read32()
488 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) in tg3_write_indirect_reg32() argument
492 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
493 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
494 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
495 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
498 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) in tg3_write_flush_reg32() argument
500 writel(val, tp->regs + off); in tg3_write_flush_reg32()
501 readl(tp->regs + off); in tg3_write_flush_reg32()
504 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) in tg3_read_indirect_reg32() argument
509 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
510 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
511 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
512 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
516 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) in tg3_write_indirect_mbox() argument
521 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
526 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
531 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
532 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
533 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
534 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
541 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
542 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
546 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) in tg3_read_indirect_mbox() argument
551 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
552 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
553 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
554 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
563 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) in _tw32_flush() argument
565 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) in _tw32_flush()
567 tp->write32(tp, off, val); in _tw32_flush()
570 tg3_write32(tp, off, val); in _tw32_flush()
573 tp->read32(tp, off); in _tw32_flush()
582 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) in tw32_mailbox_flush() argument
584 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
585 if (tg3_flag(tp, FLUSH_POSTED_WRITES) || in tw32_mailbox_flush()
586 (!tg3_flag(tp, MBOX_WRITE_REORDER) && in tw32_mailbox_flush()
587 !tg3_flag(tp, ICH_WORKAROUND))) in tw32_mailbox_flush()
588 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
591 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) in tg3_write32_tx_mbox() argument
593 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
595 if (tg3_flag(tp, TXD_MBOX_HWBUG)) in tg3_write32_tx_mbox()
597 if (tg3_flag(tp, MBOX_WRITE_REORDER) || in tg3_write32_tx_mbox()
598 tg3_flag(tp, FLUSH_POSTED_WRITES)) in tg3_write32_tx_mbox()
602 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) in tg3_read32_mbox_5906() argument
604 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
607 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) in tg3_write32_mbox_5906() argument
609 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
612 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
613 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
614 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
615 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
616 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
618 #define tw32(reg, val) tp->write32(tp, reg, val)
619 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
620 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
621 #define tr32(reg) tp->read32(tp, reg)
623 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) in tg3_write_mem() argument
627 if (tg3_asic_rev(tp) == ASIC_REV_5906 && in tg3_write_mem()
631 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
632 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_write_mem()
633 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
634 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
645 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
648 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) in tg3_read_mem() argument
652 if (tg3_asic_rev(tp) == ASIC_REV_5906 && in tg3_read_mem()
658 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
659 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_read_mem()
660 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
661 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
664 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
672 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
675 static void tg3_ape_lock_init(struct tg3 *tp) in tg3_ape_lock_init() argument
680 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_lock_init()
695 if (!tp->pci_fn) in tg3_ape_lock_init()
698 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
700 tg3_ape_write32(tp, regbase + 4 * i, bit); in tg3_ape_lock_init()
705 static int tg3_ape_lock(struct tg3 *tp, int locknum) in tg3_ape_lock() argument
711 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_lock()
716 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_lock()
721 if (!tp->pci_fn) in tg3_ape_lock()
724 bit = 1 << tp->pci_fn; in tg3_ape_lock()
736 if (tg3_asic_rev(tp) == ASIC_REV_5761) { in tg3_ape_lock()
746 tg3_ape_write32(tp, req + off, bit); in tg3_ape_lock()
750 status = tg3_ape_read32(tp, gnt + off); in tg3_ape_lock()
753 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
761 tg3_ape_write32(tp, gnt + off, bit); in tg3_ape_lock()
768 static void tg3_ape_unlock(struct tg3 *tp, int locknum) in tg3_ape_unlock() argument
772 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_unlock()
777 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_unlock()
782 if (!tp->pci_fn) in tg3_ape_unlock()
785 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
797 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_unlock()
802 tg3_ape_write32(tp, gnt + 4 * locknum, bit); in tg3_ape_unlock()
805 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us) in tg3_ape_event_lock() argument
810 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) in tg3_ape_event_lock()
813 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); in tg3_ape_event_lock()
817 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_event_lock()
827 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us) in tg3_ape_wait_for_event() argument
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); in tg3_ape_wait_for_event()
843 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, in tg3_ape_scratchpad_read() argument
849 if (!tg3_flag(tp, APE_HAS_NCSI)) in tg3_ape_scratchpad_read()
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_ape_scratchpad_read()
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_scratchpad_read()
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) + in tg3_ape_scratchpad_read()
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN); in tg3_ape_scratchpad_read()
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_scratchpad_read()
877 err = tg3_ape_event_lock(tp, 1000); in tg3_ape_scratchpad_read()
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata); in tg3_ape_scratchpad_read()
886 tg3_ape_write32(tp, bufoff, base_off); in tg3_ape_scratchpad_read()
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length); in tg3_ape_scratchpad_read()
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_scratchpad_read()
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); in tg3_ape_scratchpad_read()
894 if (tg3_ape_wait_for_event(tp, 30000)) in tg3_ape_scratchpad_read()
898 u32 val = tg3_ape_read32(tp, msgoff + i); in tg3_ape_scratchpad_read()
908 static int tg3_ape_send_event(struct tg3 *tp, u32 event) in tg3_ape_send_event() argument
913 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_ape_send_event()
917 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_send_event()
922 err = tg3_ape_event_lock(tp, 20000); in tg3_ape_send_event()
926 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, in tg3_ape_send_event()
929 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_send_event()
930 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); in tg3_ape_send_event()
935 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) in tg3_ape_driver_state_change() argument
940 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_driver_state_change()
945 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_ape_driver_state_change()
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, in tg3_ape_driver_state_change()
948 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, in tg3_ape_driver_state_change()
950 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); in tg3_ape_driver_state_change()
951 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); in tg3_ape_driver_state_change()
952 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, in tg3_ape_driver_state_change()
954 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, in tg3_ape_driver_state_change()
956 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, in tg3_ape_driver_state_change()
962 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
963 tg3_flag(tp, WOL_ENABLE)) { in tg3_ape_driver_state_change()
964 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, in tg3_ape_driver_state_change()
970 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); in tg3_ape_driver_state_change()
980 tg3_ape_send_event(tp, event); in tg3_ape_driver_state_change()
983 static void tg3_send_ape_heartbeat(struct tg3 *tp, in tg3_send_ape_heartbeat() argument
987 if (!tg3_flag(tp, ENABLE_APE) || in tg3_send_ape_heartbeat()
988 time_before(jiffies, tp->ape_hb_jiffies + interval)) in tg3_send_ape_heartbeat()
991 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_send_ape_heartbeat()
992 tp->ape_hb_jiffies = jiffies; in tg3_send_ape_heartbeat()
995 static void tg3_disable_ints(struct tg3 *tp) in tg3_disable_ints() argument
1000 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
1001 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1002 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1005 static void tg3_enable_ints(struct tg3 *tp) in tg3_enable_ints() argument
1009 tp->irq_sync = 0; in tg3_enable_ints()
1013 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1015 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1016 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1017 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1020 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_enable_ints()
1023 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1027 if (!tg3_flag(tp, TAGGED_STATUS) && in tg3_enable_ints()
1028 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1029 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1031 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1033 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1038 struct tg3 *tp = tnapi->tp; in tg3_has_work() local
1043 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_has_work()
1067 struct tg3 *tp = tnapi->tp; in tg3_int_reenable() local
1075 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) in tg3_int_reenable()
1076 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1080 static void tg3_switch_clocks(struct tg3 *tp) in tg3_switch_clocks() argument
1085 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) in tg3_switch_clocks()
1094 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1096 if (tg3_flag(tp, 5705_PLUS)) { in tg3_switch_clocks()
1115 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, in __tg3_readphy() argument
1122 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1124 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1128 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1159 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1160 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1164 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1169 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) in tg3_readphy() argument
1171 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1174 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, in __tg3_writephy() argument
1181 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1185 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1187 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1191 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1218 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1219 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1223 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1228 static int tg3_writephy(struct tg3 *tp, int reg, u32 val) in tg3_writephy() argument
1230 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1233 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) in tg3_phy_cl45_write() argument
1237 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_write()
1241 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_write()
1245 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_write()
1250 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_write()
1256 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) in tg3_phy_cl45_read() argument
1260 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_read()
1264 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_read()
1268 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_read()
1273 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_read()
1279 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) in tg3_phydsp_read() argument
1283 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_read()
1285 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_read()
1290 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) in tg3_phydsp_write() argument
1294 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_write()
1296 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write()
1301 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) in tg3_phy_auxctl_read() argument
1305 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, in tg3_phy_auxctl_read()
1309 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); in tg3_phy_auxctl_read()
1314 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) in tg3_phy_auxctl_write() argument
1319 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); in tg3_phy_auxctl_write()
1322 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable) in tg3_phy_toggle_auxctl_smdsp() argument
1327 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); in tg3_phy_toggle_auxctl_smdsp()
1337 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_toggle_auxctl_smdsp()
1343 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val) in tg3_phy_shdw_write() argument
1345 return tg3_writephy(tp, MII_TG3_MISC_SHDW, in tg3_phy_shdw_write()
1349 static int tg3_bmcr_reset(struct tg3 *tp) in tg3_bmcr_reset() argument
1358 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
1364 err = tg3_readphy(tp, MII_BMCR, &phy_control); in tg3_bmcr_reset()
1382 struct tg3 *tp = bp->priv; in tg3_mdio_read() local
1385 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1387 if (__tg3_readphy(tp, mii_id, reg, &val)) in tg3_mdio_read()
1390 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1397 struct tg3 *tp = bp->priv; in tg3_mdio_write() local
1400 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1402 if (__tg3_writephy(tp, mii_id, reg, val)) in tg3_mdio_write()
1405 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1410 static void tg3_mdio_config_5785(struct tg3 *tp) in tg3_mdio_config_5785() argument
1415 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_config_5785()
1446 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) in tg3_mdio_config_5785()
1459 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1460 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1462 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1477 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1478 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1483 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1491 static void tg3_mdio_start(struct tg3 *tp) in tg3_mdio_start() argument
1493 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1494 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1497 if (tg3_flag(tp, MDIOBUS_INITED) && in tg3_mdio_start()
1498 tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_mdio_start()
1499 tg3_mdio_config_5785(tp); in tg3_mdio_start()
1502 static int tg3_mdio_init(struct tg3 *tp) in tg3_mdio_init() argument
1508 if (tg3_flag(tp, 5717_PLUS)) { in tg3_mdio_init()
1511 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1513 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) in tg3_mdio_init()
1519 tp->phy_addr += 7; in tg3_mdio_init()
1520 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) { in tg3_mdio_init()
1523 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1526 tp->phy_addr = addr; in tg3_mdio_init()
1528 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1530 tg3_mdio_start(tp); in tg3_mdio_init()
1532 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) in tg3_mdio_init()
1535 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1536 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1539 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1540 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", in tg3_mdio_init()
1541 (tp->pdev->bus->number << 8) | tp->pdev->devfn); in tg3_mdio_init()
1542 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1543 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1544 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1545 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1546 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1553 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) in tg3_mdio_init()
1554 tg3_bmcr_reset(tp); in tg3_mdio_init()
1556 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1558 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1559 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1563 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_init()
1566 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1567 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1568 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1583 if (tg3_flag(tp, RGMII_INBAND_DISABLE)) in tg3_mdio_init()
1585 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_init()
1587 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_init()
1597 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1601 tg3_flag_set(tp, MDIOBUS_INITED); in tg3_mdio_init()
1603 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_mdio_init()
1604 tg3_mdio_config_5785(tp); in tg3_mdio_init()
1609 static void tg3_mdio_fini(struct tg3 *tp) in tg3_mdio_fini() argument
1611 if (tg3_flag(tp, MDIOBUS_INITED)) { in tg3_mdio_fini()
1612 tg3_flag_clear(tp, MDIOBUS_INITED); in tg3_mdio_fini()
1613 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1614 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1619 static inline void tg3_generate_fw_event(struct tg3 *tp) in tg3_generate_fw_event() argument
1627 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1633 static void tg3_wait_for_event_ack(struct tg3 *tp) in tg3_wait_for_event_ack() argument
1640 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1655 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1663 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data) in tg3_phy_gather_ump_data() argument
1668 if (!tg3_readphy(tp, MII_BMCR, ®)) in tg3_phy_gather_ump_data()
1670 if (!tg3_readphy(tp, MII_BMSR, ®)) in tg3_phy_gather_ump_data()
1675 if (!tg3_readphy(tp, MII_ADVERTISE, ®)) in tg3_phy_gather_ump_data()
1677 if (!tg3_readphy(tp, MII_LPA, ®)) in tg3_phy_gather_ump_data()
1682 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1683 if (!tg3_readphy(tp, MII_CTRL1000, ®)) in tg3_phy_gather_ump_data()
1685 if (!tg3_readphy(tp, MII_STAT1000, ®)) in tg3_phy_gather_ump_data()
1690 if (!tg3_readphy(tp, MII_PHYADDR, ®)) in tg3_phy_gather_ump_data()
1698 static void tg3_ump_link_report(struct tg3 *tp) in tg3_ump_link_report() argument
1702 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) in tg3_ump_link_report()
1705 tg3_phy_gather_ump_data(tp, data); in tg3_ump_link_report()
1707 tg3_wait_for_event_ack(tp); in tg3_ump_link_report()
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); in tg3_ump_link_report()
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); in tg3_ump_link_report()
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]); in tg3_ump_link_report()
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]); in tg3_ump_link_report()
1713 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]); in tg3_ump_link_report()
1714 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]); in tg3_ump_link_report()
1716 tg3_generate_fw_event(tp); in tg3_ump_link_report()
1720 static void tg3_stop_fw(struct tg3 *tp) in tg3_stop_fw() argument
1722 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_stop_fw()
1724 tg3_wait_for_event_ack(tp); in tg3_stop_fw()
1726 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); in tg3_stop_fw()
1728 tg3_generate_fw_event(tp); in tg3_stop_fw()
1731 tg3_wait_for_event_ack(tp); in tg3_stop_fw()
1736 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) in tg3_write_sig_pre_reset() argument
1738 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, in tg3_write_sig_pre_reset()
1741 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_pre_reset()
1744 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1749 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1754 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1765 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) in tg3_write_sig_post_reset() argument
1767 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_post_reset()
1770 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_post_reset()
1775 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_post_reset()
1786 static void tg3_write_sig_legacy(struct tg3 *tp, int kind) in tg3_write_sig_legacy() argument
1788 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_write_sig_legacy()
1791 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1796 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1801 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1811 static int tg3_poll_fw(struct tg3 *tp) in tg3_poll_fw() argument
1816 if (tg3_flag(tp, NO_FWARE_REPORTED)) in tg3_poll_fw()
1819 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_poll_fw()
1824 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_poll_fw()
1829 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1839 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); in tg3_poll_fw()
1842 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1843 if (!tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1844 tg3_flag_set(tp, NO_FWARE_REPORTED); in tg3_poll_fw()
1845 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1859 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1860 tg3_flag_set(tp, NO_FWARE_REPORTED); in tg3_poll_fw()
1862 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1865 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { in tg3_poll_fw()
1875 static void tg3_link_report(struct tg3 *tp) in tg3_link_report() argument
1877 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1878 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1879 tg3_ump_link_report(tp); in tg3_link_report()
1880 } else if (netif_msg_link(tp)) { in tg3_link_report()
1881 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1882 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1884 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1886 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1889 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1892 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1895 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1896 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1897 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1899 tg3_ump_link_report(tp); in tg3_link_report()
1902 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1965 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) in tg3_setup_flow_control() argument
1969 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1970 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1972 if (tg3_flag(tp, USE_PHYLIB)) in tg3_setup_flow_control()
1973 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; in tg3_setup_flow_control()
1975 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1977 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_setup_flow_control()
1978 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1983 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1985 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
1988 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1990 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1992 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1993 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
1996 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1998 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
2000 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
2001 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2008 struct tg3 *tp = netdev_priv(dev); in tg3_adjust_link() local
2009 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_adjust_link()
2011 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2013 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2016 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2025 tg3_asic_rev(tp) != ASIC_REV_5785) in tg3_adjust_link()
2034 tp->link_config.flowctrl); in tg3_adjust_link()
2042 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); in tg3_adjust_link()
2046 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2047 tp->mac_mode = mac_mode; in tg3_adjust_link()
2048 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2052 if (tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_adjust_link()
2072 if (phydev->link != tp->old_link || in tg3_adjust_link()
2073 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2074 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2075 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2078 tp->old_link = phydev->link; in tg3_adjust_link()
2079 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2080 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2082 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2085 tg3_link_report(tp); in tg3_adjust_link()
2088 static int tg3_phy_init(struct tg3 *tp) in tg3_phy_init() argument
2092 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2096 tg3_bmcr_reset(tp); in tg3_phy_init()
2098 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_init()
2101 phydev = phy_connect(tp->dev, phydev_name(phydev), in tg3_phy_init()
2104 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2112 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2123 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_init()
2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2134 static void tg3_phy_start(struct tg3 *tp) in tg3_phy_start() argument
2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2141 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_start()
2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2145 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2146 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2147 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2149 phydev->advertising, tp->link_config.advertising); in tg3_phy_start()
2157 static void tg3_phy_stop(struct tg3 *tp) in tg3_phy_stop() argument
2159 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2162 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_stop()
2165 static void tg3_phy_fini(struct tg3 *tp) in tg3_phy_fini() argument
2167 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2168 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_fini()
2169 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2173 static int tg3_phy_set_extloopbk(struct tg3 *tp) in tg3_phy_set_extloopbk() argument
2178 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2181 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2183 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2190 err = tg3_phy_auxctl_read(tp, in tg3_phy_set_extloopbk()
2196 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2203 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) in tg3_phy_fet_toggle_apd() argument
2207 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_phy_fet_toggle_apd()
2210 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_fet_toggle_apd()
2212 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { in tg3_phy_fet_toggle_apd()
2217 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); in tg3_phy_fet_toggle_apd()
2219 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_phy_fet_toggle_apd()
2223 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) in tg3_phy_toggle_apd() argument
2227 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_apd()
2228 (tg3_flag(tp, 5717_PLUS) && in tg3_phy_toggle_apd()
2229 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2232 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2233 tg3_phy_fet_toggle_apd(tp, enable); in tg3_phy_toggle_apd()
2241 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable) in tg3_phy_toggle_apd()
2244 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg); in tg3_phy_toggle_apd()
2251 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg); in tg3_phy_toggle_apd()
2254 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable) in tg3_phy_toggle_automdix() argument
2258 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_automdix()
2259 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2262 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2265 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { in tg3_phy_toggle_automdix()
2268 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_toggle_automdix()
2270 if (!tg3_readphy(tp, reg, &phy)) { in tg3_phy_toggle_automdix()
2275 tg3_writephy(tp, reg, phy); in tg3_phy_toggle_automdix()
2277 tg3_writephy(tp, MII_TG3_FET_TEST, ephy); in tg3_phy_toggle_automdix()
2282 ret = tg3_phy_auxctl_read(tp, in tg3_phy_toggle_automdix()
2289 tg3_phy_auxctl_write(tp, in tg3_phy_toggle_automdix()
2295 static void tg3_phy_set_wirespeed(struct tg3 *tp) in tg3_phy_set_wirespeed() argument
2300 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2303 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
2305 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
2309 static void tg3_phy_apply_otp(struct tg3 *tp) in tg3_phy_apply_otp() argument
2313 if (!tp->phy_otp) in tg3_phy_apply_otp()
2316 otp = tp->phy_otp; in tg3_phy_apply_otp()
2318 if (tg3_phy_toggle_auxctl_smdsp(tp, true)) in tg3_phy_apply_otp()
2323 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); in tg3_phy_apply_otp()
2327 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); in tg3_phy_apply_otp()
2331 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); in tg3_phy_apply_otp()
2334 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); in tg3_phy_apply_otp()
2337 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); in tg3_phy_apply_otp()
2341 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); in tg3_phy_apply_otp()
2343 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_apply_otp()
2346 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee) in tg3_eee_pull_config() argument
2349 struct ethtool_eee *dest = &tp->eee; in tg3_eee_pull_config()
2351 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2357 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val)) in tg3_eee_pull_config()
2368 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val)) in tg3_eee_pull_config()
2373 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val)) in tg3_eee_pull_config()
2386 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up) in tg3_phy_eee_adjust() argument
2390 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2393 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2395 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2397 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2398 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2399 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2402 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2409 tg3_eee_pull_config(tp, NULL); in tg3_phy_eee_adjust()
2410 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2411 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2414 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2416 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_eee_adjust()
2417 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); in tg3_phy_eee_adjust()
2418 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_eee_adjust()
2426 static void tg3_phy_eee_enable(struct tg3 *tp) in tg3_phy_eee_enable() argument
2430 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2431 (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_phy_eee_enable()
2432 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_phy_eee_enable()
2433 tg3_flag(tp, 57765_CLASS)) && in tg3_phy_eee_enable()
2434 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_eee_enable()
2437 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); in tg3_phy_eee_enable()
2438 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_eee_enable()
2445 static int tg3_wait_macro_done(struct tg3 *tp) in tg3_wait_macro_done() argument
2452 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { in tg3_wait_macro_done()
2463 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) in tg3_phy_write_and_check_testpat() argument
2476 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2478 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2481 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
2484 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2485 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2490 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2492 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2493 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2498 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2499 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2507 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || in tg3_phy_write_and_check_testpat()
2508 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || in tg3_phy_write_and_check_testpat()
2509 tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2517 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); in tg3_phy_write_and_check_testpat()
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
2519 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
2529 static int tg3_phy_reset_chanpat(struct tg3 *tp) in tg3_phy_reset_chanpat() argument
2536 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_reset_chanpat()
2538 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2540 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
2541 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2542 if (tg3_wait_macro_done(tp)) in tg3_phy_reset_chanpat()
2549 static int tg3_phy_reset_5703_4_5(struct tg3 *tp) in tg3_phy_reset_5703_4_5() argument
2558 err = tg3_bmcr_reset(tp); in tg3_phy_reset_5703_4_5()
2565 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) in tg3_phy_reset_5703_4_5()
2569 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2572 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
2576 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) in tg3_phy_reset_5703_4_5()
2579 tg3_writephy(tp, MII_CTRL1000, in tg3_phy_reset_5703_4_5()
2582 err = tg3_phy_toggle_auxctl_smdsp(tp, true); in tg3_phy_reset_5703_4_5()
2587 tg3_phydsp_write(tp, 0x8005, 0x0800); in tg3_phy_reset_5703_4_5()
2589 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); in tg3_phy_reset_5703_4_5()
2594 err = tg3_phy_reset_chanpat(tp); in tg3_phy_reset_5703_4_5()
2598 tg3_phydsp_write(tp, 0x8005, 0x0000); in tg3_phy_reset_5703_4_5()
2600 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); in tg3_phy_reset_5703_4_5()
2601 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
2603 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset_5703_4_5()
2605 tg3_writephy(tp, MII_CTRL1000, phy9_orig); in tg3_phy_reset_5703_4_5()
2607 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32); in tg3_phy_reset_5703_4_5()
2612 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2617 static void tg3_carrier_off(struct tg3 *tp) in tg3_carrier_off() argument
2619 netif_carrier_off(tp->dev); in tg3_carrier_off()
2620 tp->link_up = false; in tg3_carrier_off()
2623 static void tg3_warn_mgmt_link_flap(struct tg3 *tp) in tg3_warn_mgmt_link_flap() argument
2625 if (tg3_flag(tp, ENABLE_ASF)) in tg3_warn_mgmt_link_flap()
2626 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2633 static int tg3_phy_reset(struct tg3 *tp) in tg3_phy_reset() argument
2638 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_phy_reset()
2643 err = tg3_readphy(tp, MII_BMSR, &val); in tg3_phy_reset()
2644 err |= tg3_readphy(tp, MII_BMSR, &val); in tg3_phy_reset()
2648 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2649 netif_carrier_off(tp->dev); in tg3_phy_reset()
2650 tg3_link_report(tp); in tg3_phy_reset()
2653 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_phy_reset()
2654 tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_phy_reset()
2655 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_phy_reset()
2656 err = tg3_phy_reset_5703_4_5(tp); in tg3_phy_reset()
2663 if (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_phy_reset()
2664 tg3_chip_rev(tp) != CHIPREV_5784_AX) { in tg3_phy_reset()
2671 err = tg3_bmcr_reset(tp); in tg3_phy_reset()
2677 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); in tg3_phy_reset()
2682 if (tg3_chip_rev(tp) == CHIPREV_5784_AX || in tg3_phy_reset()
2683 tg3_chip_rev(tp) == CHIPREV_5761_AX) { in tg3_phy_reset()
2693 if (tg3_flag(tp, 5717_PLUS) && in tg3_phy_reset()
2694 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2697 tg3_phy_apply_otp(tp); in tg3_phy_reset()
2699 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2700 tg3_phy_toggle_apd(tp, true); in tg3_phy_reset()
2702 tg3_phy_toggle_apd(tp, false); in tg3_phy_reset()
2705 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2706 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2707 tg3_phydsp_write(tp, 0x201f, 0x2aaa); in tg3_phy_reset()
2708 tg3_phydsp_write(tp, 0x000a, 0x0323); in tg3_phy_reset()
2709 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2712 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2714 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2717 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2718 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2719 tg3_phydsp_write(tp, 0x000a, 0x310b); in tg3_phy_reset()
2720 tg3_phydsp_write(tp, 0x201f, 0x9506); in tg3_phy_reset()
2721 tg3_phydsp_write(tp, 0x401f, 0x14e2); in tg3_phy_reset()
2722 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2724 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2725 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2726 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); in tg3_phy_reset()
2727 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2728 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset()
2729 tg3_writephy(tp, MII_TG3_TEST1, in tg3_phy_reset()
2732 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); in tg3_phy_reset()
2734 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2740 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2742 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_phy_reset()
2743 } else if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2745 err = tg3_phy_auxctl_read(tp, in tg3_phy_reset()
2748 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_reset()
2755 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2756 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) in tg3_phy_reset()
2757 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_reset()
2761 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_phy_reset()
2763 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); in tg3_phy_reset()
2766 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0) in tg3_phy_reset()
2767 tg3_phydsp_write(tp, 0xffb, 0x4000); in tg3_phy_reset()
2769 tg3_phy_toggle_automdix(tp, true); in tg3_phy_reset()
2770 tg3_phy_set_wirespeed(tp); in tg3_phy_reset()
2790 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) in tg3_set_function_status() argument
2794 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_function_status()
2795 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_set_function_status()
2796 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); in tg3_set_function_status()
2800 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2804 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_function_status()
2805 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_set_function_status()
2806 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); in tg3_set_function_status()
2813 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) in tg3_pwrsrc_switch_to_vmain() argument
2815 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vmain()
2818 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_pwrsrc_switch_to_vmain()
2819 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_pwrsrc_switch_to_vmain()
2820 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_pwrsrc_switch_to_vmain()
2821 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_pwrsrc_switch_to_vmain()
2824 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); in tg3_pwrsrc_switch_to_vmain()
2826 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2829 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); in tg3_pwrsrc_switch_to_vmain()
2831 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2838 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) in tg3_pwrsrc_die_with_vmain() argument
2842 if (!tg3_flag(tp, IS_NIC) || in tg3_pwrsrc_die_with_vmain()
2843 tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_pwrsrc_die_with_vmain()
2844 tg3_asic_rev(tp) == ASIC_REV_5701) in tg3_pwrsrc_die_with_vmain()
2847 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2862 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) in tg3_pwrsrc_switch_to_vaux() argument
2864 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vaux()
2867 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_pwrsrc_switch_to_vaux()
2868 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_pwrsrc_switch_to_vaux()
2869 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2876 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2877 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2884 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2900 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_pwrsrc_switch_to_vaux()
2902 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2908 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2921 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2927 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2933 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2939 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) in tg3_frob_aux_power_5717() argument
2944 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_frob_aux_power_5717()
2947 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) in tg3_frob_aux_power_5717()
2950 msg = tg3_set_function_status(tp, msg); in tg3_frob_aux_power_5717()
2956 tg3_pwrsrc_switch_to_vaux(tp); in tg3_frob_aux_power_5717()
2958 tg3_pwrsrc_die_with_vmain(tp); in tg3_frob_aux_power_5717()
2961 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); in tg3_frob_aux_power_5717()
2964 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) in tg3_frob_aux_power() argument
2969 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) in tg3_frob_aux_power()
2972 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_frob_aux_power()
2973 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_frob_aux_power()
2974 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_frob_aux_power()
2975 tg3_frob_aux_power_5717(tp, include_wol ? in tg3_frob_aux_power()
2976 tg3_flag(tp, WOL_ENABLE) != 0 : 0); in tg3_frob_aux_power()
2980 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2983 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
2998 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || in tg3_frob_aux_power()
2999 tg3_flag(tp, ENABLE_ASF)) in tg3_frob_aux_power()
3003 tg3_pwrsrc_switch_to_vaux(tp); in tg3_frob_aux_power()
3005 tg3_pwrsrc_die_with_vmain(tp); in tg3_frob_aux_power()
3008 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) in tg3_5700_link_polarity() argument
3010 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3012 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3021 static bool tg3_phy_power_bug(struct tg3 *tp) in tg3_phy_power_bug() argument
3023 switch (tg3_asic_rev(tp)) { in tg3_phy_power_bug()
3028 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3032 if (!tp->pci_fn) in tg3_phy_power_bug()
3037 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3038 !tp->pci_fn) in tg3_phy_power_bug()
3046 static bool tg3_phy_led_bug(struct tg3 *tp) in tg3_phy_led_bug() argument
3048 switch (tg3_asic_rev(tp)) { in tg3_phy_led_bug()
3051 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3052 !tp->pci_fn) in tg3_phy_led_bug()
3060 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) in tg3_power_down_phy() argument
3064 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3067 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3068 if (tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_power_down_phy()
3080 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_phy()
3081 tg3_bmcr_reset(tp); in tg3_power_down_phy()
3086 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3088 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_power_down_phy()
3091 tg3_writephy(tp, MII_ADVERTISE, 0); in tg3_power_down_phy()
3092 tg3_writephy(tp, MII_BMCR, in tg3_power_down_phy()
3095 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_power_down_phy()
3097 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { in tg3_power_down_phy()
3099 tg3_writephy(tp, in tg3_power_down_phy()
3103 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_power_down_phy()
3107 if (!tg3_phy_led_bug(tp)) in tg3_power_down_phy()
3108 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_power_down_phy()
3114 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); in tg3_power_down_phy()
3120 if (tg3_phy_power_bug(tp)) in tg3_power_down_phy()
3123 if (tg3_chip_rev(tp) == CHIPREV_5784_AX || in tg3_power_down_phy()
3124 tg3_chip_rev(tp) == CHIPREV_5761_AX) { in tg3_power_down_phy()
3131 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); in tg3_power_down_phy()
3135 static int tg3_nvram_lock(struct tg3 *tp) in tg3_nvram_lock() argument
3137 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_lock()
3140 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3152 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3158 static void tg3_nvram_unlock(struct tg3 *tp) in tg3_nvram_unlock() argument
3160 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_unlock()
3161 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3162 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3163 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3169 static void tg3_enable_nvram_access(struct tg3 *tp) in tg3_enable_nvram_access() argument
3171 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_enable_nvram_access()
3179 static void tg3_disable_nvram_access(struct tg3 *tp) in tg3_disable_nvram_access() argument
3181 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_disable_nvram_access()
3188 static int tg3_nvram_read_using_eeprom(struct tg3 *tp, in tg3_nvram_read_using_eeprom() argument
3230 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) in tg3_nvram_exec_cmd() argument
3249 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) in tg3_nvram_phys_addr() argument
3251 if (tg3_flag(tp, NVRAM) && in tg3_nvram_phys_addr()
3252 tg3_flag(tp, NVRAM_BUFFERED) && in tg3_nvram_phys_addr()
3253 tg3_flag(tp, FLASH) && in tg3_nvram_phys_addr()
3254 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && in tg3_nvram_phys_addr()
3255 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3257 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3259 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3264 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) in tg3_nvram_logical_addr() argument
3266 if (tg3_flag(tp, NVRAM) && in tg3_nvram_logical_addr()
3267 tg3_flag(tp, NVRAM_BUFFERED) && in tg3_nvram_logical_addr()
3268 tg3_flag(tp, FLASH) && in tg3_nvram_logical_addr()
3269 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && in tg3_nvram_logical_addr()
3270 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3273 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3285 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) in tg3_nvram_read() argument
3289 if (!tg3_flag(tp, NVRAM)) in tg3_nvram_read()
3290 return tg3_nvram_read_using_eeprom(tp, offset, val); in tg3_nvram_read()
3292 offset = tg3_nvram_phys_addr(tp, offset); in tg3_nvram_read()
3297 ret = tg3_nvram_lock(tp); in tg3_nvram_read()
3301 tg3_enable_nvram_access(tp); in tg3_nvram_read()
3304 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | in tg3_nvram_read()
3310 tg3_disable_nvram_access(tp); in tg3_nvram_read()
3312 tg3_nvram_unlock(tp); in tg3_nvram_read()
3318 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) in tg3_nvram_read_be32() argument
3321 int res = tg3_nvram_read(tp, offset, &v); in tg3_nvram_read_be32()
3327 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, in tg3_nvram_write_block_using_eeprom() argument
3377 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, in tg3_nvram_write_block_unbuffered() argument
3381 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3397 ret = tg3_nvram_read_be32(tp, phy_addr + j, in tg3_nvram_write_block_unbuffered()
3416 tg3_enable_nvram_access(tp); in tg3_nvram_write_block_unbuffered()
3424 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3433 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3439 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3459 ret = tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_unbuffered()
3468 tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_unbuffered()
3476 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, in tg3_nvram_write_block_buffered() argument
3488 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3490 phy_addr = tg3_nvram_phys_addr(tp, offset); in tg3_nvram_write_block_buffered()
3496 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3503 !tg3_flag(tp, FLASH) || in tg3_nvram_write_block_buffered()
3504 !tg3_flag(tp, 57765_PLUS)) in tg3_nvram_write_block_buffered()
3507 if (tg3_asic_rev(tp) != ASIC_REV_5752 && in tg3_nvram_write_block_buffered()
3508 !tg3_flag(tp, 5755_PLUS) && in tg3_nvram_write_block_buffered()
3509 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3514 ret = tg3_nvram_exec_cmd(tp, cmd); in tg3_nvram_write_block_buffered()
3518 if (!tg3_flag(tp, FLASH)) { in tg3_nvram_write_block_buffered()
3523 ret = tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_buffered()
3531 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) in tg3_nvram_write_block() argument
3535 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
3536 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3541 if (!tg3_flag(tp, NVRAM)) { in tg3_nvram_write_block()
3542 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); in tg3_nvram_write_block()
3546 ret = tg3_nvram_lock(tp); in tg3_nvram_write_block()
3550 tg3_enable_nvram_access(tp); in tg3_nvram_write_block()
3551 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) in tg3_nvram_write_block()
3557 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { in tg3_nvram_write_block()
3558 ret = tg3_nvram_write_block_buffered(tp, offset, len, in tg3_nvram_write_block()
3561 ret = tg3_nvram_write_block_unbuffered(tp, offset, len, in tg3_nvram_write_block()
3568 tg3_disable_nvram_access(tp); in tg3_nvram_write_block()
3569 tg3_nvram_unlock(tp); in tg3_nvram_write_block()
3572 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
3573 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3586 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base) in tg3_pause_cpu() argument
3596 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3604 static int tg3_rxcpu_pause(struct tg3 *tp) in tg3_rxcpu_pause() argument
3606 int rc = tg3_pause_cpu(tp, RX_CPU_BASE); in tg3_rxcpu_pause()
3616 static int tg3_txcpu_pause(struct tg3 *tp) in tg3_txcpu_pause() argument
3618 return tg3_pause_cpu(tp, TX_CPU_BASE); in tg3_txcpu_pause()
3622 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base) in tg3_resume_cpu() argument
3629 static void tg3_rxcpu_resume(struct tg3 *tp) in tg3_rxcpu_resume() argument
3631 tg3_resume_cpu(tp, RX_CPU_BASE); in tg3_rxcpu_resume()
3635 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base) in tg3_halt_cpu() argument
3639 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); in tg3_halt_cpu()
3641 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_halt_cpu()
3648 rc = tg3_rxcpu_pause(tp); in tg3_halt_cpu()
3654 if (tg3_flag(tp, IS_SSB_CORE)) in tg3_halt_cpu()
3657 rc = tg3_txcpu_pause(tp); in tg3_halt_cpu()
3661 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3667 if (tg3_flag(tp, NVRAM)) in tg3_halt_cpu()
3672 static int tg3_fw_data_len(struct tg3 *tp, in tg3_fw_data_len() argument
3691 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3694 fw_len = tp->fw->size; in tg3_fw_data_len()
3700 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, in tg3_load_firmware_cpu() argument
3706 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3708 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { in tg3_load_firmware_cpu()
3709 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3715 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766) in tg3_load_firmware_cpu()
3720 if (tg3_asic_rev(tp) != ASIC_REV_57766) { in tg3_load_firmware_cpu()
3724 int lock_err = tg3_nvram_lock(tp); in tg3_load_firmware_cpu()
3725 err = tg3_halt_cpu(tp, cpu_base); in tg3_load_firmware_cpu()
3727 tg3_nvram_unlock(tp); in tg3_load_firmware_cpu()
3732 write_op(tp, cpu_scratch_base + i, 0); in tg3_load_firmware_cpu()
3746 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++) in tg3_load_firmware_cpu()
3747 write_op(tp, cpu_scratch_base + in tg3_load_firmware_cpu()
3766 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc) in tg3_pause_cpu_and_set_pc() argument
3787 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) in tg3_load_5701_a0_firmware_fix() argument
3792 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3800 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3806 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3813 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3816 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3823 tg3_rxcpu_resume(tp); in tg3_load_5701_a0_firmware_fix()
3828 static int tg3_validate_rxcpu_state(struct tg3 *tp) in tg3_validate_rxcpu_state() argument
3845 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3849 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE); in tg3_validate_rxcpu_state()
3851 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3860 static void tg3_load_57766_firmware(struct tg3 *tp) in tg3_load_57766_firmware() argument
3864 if (!tg3_flag(tp, NO_NVRAM)) in tg3_load_57766_firmware()
3867 if (tg3_validate_rxcpu_state(tp)) in tg3_load_57766_firmware()
3870 if (!tp->fw) in tg3_load_57766_firmware()
3887 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3891 if (tg3_rxcpu_pause(tp)) in tg3_load_57766_firmware()
3895 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr); in tg3_load_57766_firmware()
3897 tg3_rxcpu_resume(tp); in tg3_load_57766_firmware()
3901 static int tg3_load_tso_firmware(struct tg3 *tp) in tg3_load_tso_firmware() argument
3907 if (!tg3_flag(tp, FW_TSO)) in tg3_load_tso_firmware()
3910 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3918 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3920 if (tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_load_tso_firmware()
3929 err = tg3_load_firmware_cpu(tp, cpu_base, in tg3_load_tso_firmware()
3936 err = tg3_pause_cpu_and_set_pc(tp, cpu_base, in tg3_load_tso_firmware()
3939 netdev_err(tp->dev, in tg3_load_tso_firmware()
3946 tg3_resume_cpu(tp, cpu_base); in tg3_load_tso_firmware()
3951 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index) in __tg3_set_one_mac_addr() argument
3970 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1) in __tg3_set_mac_addr() argument
3978 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3981 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in __tg3_set_mac_addr()
3982 tg3_asic_rev(tp) == ASIC_REV_5704) { in __tg3_set_mac_addr()
3984 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3987 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
3988 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
3989 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
3990 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
3991 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
3992 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
3997 static void tg3_enable_register_access(struct tg3 *tp) in tg3_enable_register_access() argument
4003 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
4004 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4007 static int tg3_power_up(struct tg3 *tp) in tg3_power_up() argument
4011 tg3_enable_register_access(tp); in tg3_power_up()
4013 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4016 tg3_pwrsrc_switch_to_vmain(tp); in tg3_power_up()
4018 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4026 static int tg3_power_down_prepare(struct tg3 *tp) in tg3_power_down_prepare() argument
4031 tg3_enable_register_access(tp); in tg3_power_down_prepare()
4034 if (tg3_flag(tp, CLKREQ_BUG)) in tg3_power_down_prepare()
4035 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4042 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4043 tg3_flag(tp, WOL_ENABLE); in tg3_power_down_prepare()
4045 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_power_down_prepare()
4047 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4048 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4053 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_power_down_prepare()
4055 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4057 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4058 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4059 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4061 &tp->link_config.advertising, in tg3_power_down_prepare()
4072 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { in tg3_power_down_prepare()
4073 if (tg3_flag(tp, WOL_SPEED_100MB)) { in tg3_power_down_prepare()
4101 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4102 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4104 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4105 tg3_setup_phy(tp, false); in tg3_power_down_prepare()
4108 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_prepare()
4113 } else if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
4118 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); in tg3_power_down_prepare()
4124 if (tg3_flag(tp, WOL_CAP)) in tg3_power_down_prepare()
4125 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | in tg3_power_down_prepare()
4133 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4135 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4136 tg3_phy_auxctl_write(tp, in tg3_power_down_prepare()
4144 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4146 else if (tp->phy_flags & in tg3_power_down_prepare()
4148 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4155 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4156 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_power_down_prepare()
4157 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? in tg3_power_down_prepare()
4159 if (tg3_5700_link_polarity(tp, speed)) in tg3_power_down_prepare()
4168 if (!tg3_flag(tp, 5750_PLUS)) in tg3_power_down_prepare()
4169 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4172 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && in tg3_power_down_prepare()
4173 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) in tg3_power_down_prepare()
4176 if (tg3_flag(tp, ENABLE_APE)) in tg3_power_down_prepare()
4188 if (!tg3_flag(tp, WOL_SPEED_100MB) && in tg3_power_down_prepare()
4189 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4190 tg3_asic_rev(tp) == ASIC_REV_5701)) { in tg3_power_down_prepare()
4193 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4199 } else if (tg3_flag(tp, 5780_CLASS) || in tg3_power_down_prepare()
4200 tg3_flag(tp, CPMU_PRESENT) || in tg3_power_down_prepare()
4201 tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_prepare()
4203 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { in tg3_power_down_prepare()
4206 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4207 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_power_down_prepare()
4212 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
4220 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4223 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4226 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
4229 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4230 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_power_down_prepare()
4239 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4243 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) in tg3_power_down_prepare()
4244 tg3_power_down_phy(tp, do_low_power); in tg3_power_down_prepare()
4246 tg3_frob_aux_power(tp, true); in tg3_power_down_prepare()
4249 if ((!tg3_flag(tp, IS_SSB_CORE)) && in tg3_power_down_prepare()
4250 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) || in tg3_power_down_prepare()
4251 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) { in tg3_power_down_prepare()
4256 if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
4259 err = tg3_nvram_lock(tp); in tg3_power_down_prepare()
4260 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_power_down_prepare()
4262 tg3_nvram_unlock(tp); in tg3_power_down_prepare()
4266 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); in tg3_power_down_prepare()
4268 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN); in tg3_power_down_prepare()
4273 static void tg3_power_down(struct tg3 *tp) in tg3_power_down() argument
4275 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4276 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4279 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex) in tg3_aux_stat_to_speed_duplex() argument
4313 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4326 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) in tg3_phy_autoneg_cfg() argument
4335 err = tg3_writephy(tp, MII_ADVERTISE, new_adv); in tg3_phy_autoneg_cfg()
4339 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4342 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_phy_autoneg_cfg()
4343 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) in tg3_phy_autoneg_cfg()
4346 err = tg3_writephy(tp, MII_CTRL1000, new_adv); in tg3_phy_autoneg_cfg()
4351 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4357 err = tg3_phy_toggle_auxctl_smdsp(tp, true); in tg3_phy_autoneg_cfg()
4369 if (!tp->eee.eee_enabled) { in tg3_phy_autoneg_cfg()
4371 tp->eee.advertised = 0; in tg3_phy_autoneg_cfg()
4373 tp->eee.advertised = advertise & in tg3_phy_autoneg_cfg()
4378 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); in tg3_phy_autoneg_cfg()
4382 switch (tg3_asic_rev(tp)) { in tg3_phy_autoneg_cfg()
4392 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); in tg3_phy_autoneg_cfg()
4396 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) in tg3_phy_autoneg_cfg()
4397 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | in tg3_phy_autoneg_cfg()
4401 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_autoneg_cfg()
4410 static void tg3_phy_copper_begin(struct tg3 *tp) in tg3_phy_copper_begin() argument
4412 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4413 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4416 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4417 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4420 if (tg3_flag(tp, WOL_SPEED_100MB)) in tg3_phy_copper_begin()
4423 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4424 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4432 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4433 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4437 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4440 tg3_phy_autoneg_cfg(tp, adv, fc); in tg3_phy_copper_begin()
4442 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4443 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4451 tg3_writephy(tp, MII_BMCR, in tg3_phy_copper_begin()
4457 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4458 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4460 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_phy_copper_begin()
4465 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL); in tg3_phy_copper_begin()
4469 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4483 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4486 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && in tg3_phy_copper_begin()
4488 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); in tg3_phy_copper_begin()
4493 if (tg3_readphy(tp, MII_BMSR, &tmp) || in tg3_phy_copper_begin()
4494 tg3_readphy(tp, MII_BMSR, &tmp)) in tg3_phy_copper_begin()
4501 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_copper_begin()
4507 static int tg3_phy_pull_config(struct tg3 *tp) in tg3_phy_pull_config() argument
4512 err = tg3_readphy(tp, MII_BMCR, &val); in tg3_phy_pull_config()
4517 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4518 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4519 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_phy_pull_config()
4525 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4528 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4531 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4534 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4537 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4538 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4547 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4549 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4551 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4557 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4558 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4559 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_phy_pull_config()
4561 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4564 err = tg3_readphy(tp, MII_ADVERTISE, &val); in tg3_phy_pull_config()
4569 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4571 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4573 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4576 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4579 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4580 err = tg3_readphy(tp, MII_CTRL1000, &val); in tg3_phy_pull_config()
4586 err = tg3_readphy(tp, MII_ADVERTISE, &val); in tg3_phy_pull_config()
4591 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4597 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4604 static int tg3_init_5401phy_dsp(struct tg3 *tp) in tg3_init_5401phy_dsp() argument
4610 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_init_5401phy_dsp()
4612 err |= tg3_phydsp_write(tp, 0x0012, 0x1804); in tg3_init_5401phy_dsp()
4613 err |= tg3_phydsp_write(tp, 0x0013, 0x1204); in tg3_init_5401phy_dsp()
4614 err |= tg3_phydsp_write(tp, 0x8006, 0x0132); in tg3_init_5401phy_dsp()
4615 err |= tg3_phydsp_write(tp, 0x8006, 0x0232); in tg3_init_5401phy_dsp()
4616 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); in tg3_init_5401phy_dsp()
4623 static bool tg3_phy_eee_config_ok(struct tg3 *tp) in tg3_phy_eee_config_ok() argument
4627 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4630 tg3_eee_pull_config(tp, &eee); in tg3_phy_eee_config_ok()
4632 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4633 if (tp->eee.advertised != eee.advertised || in tg3_phy_eee_config_ok()
4634 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4635 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4646 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) in tg3_phy_copper_an_config_ok() argument
4650 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4654 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4655 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4659 if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) in tg3_phy_copper_an_config_ok()
4665 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4670 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) in tg3_phy_copper_an_config_ok()
4674 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_phy_copper_an_config_ok()
4675 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) { in tg3_phy_copper_an_config_ok()
4690 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) in tg3_phy_copper_fetch_rmtadv() argument
4694 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4697 if (tg3_readphy(tp, MII_STAT1000, &val)) in tg3_phy_copper_fetch_rmtadv()
4703 if (tg3_readphy(tp, MII_LPA, rmtadv)) in tg3_phy_copper_fetch_rmtadv()
4707 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4712 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up) in tg3_test_and_report_link_chg() argument
4714 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4716 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4718 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4719 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4720 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4723 tg3_link_report(tp); in tg3_test_and_report_link_chg()
4730 static void tg3_clear_mac_status(struct tg3 *tp) in tg3_clear_mac_status() argument
4742 static void tg3_setup_eee(struct tg3 *tp) in tg3_setup_eee() argument
4748 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) in tg3_setup_eee()
4757 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4761 if (tg3_asic_rev(tp) != ASIC_REV_5717) in tg3_setup_eee()
4764 if (tg3_flag(tp, ENABLE_APE)) in tg3_setup_eee()
4767 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4771 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4778 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset) in tg3_setup_copper_phy() argument
4787 tg3_clear_mac_status(tp); in tg3_setup_copper_phy()
4789 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4791 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4795 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); in tg3_setup_copper_phy()
4800 if ((tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_setup_copper_phy()
4801 tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_setup_copper_phy()
4802 tg3_asic_rev(tp) == ASIC_REV_5705) && in tg3_setup_copper_phy()
4803 tp->link_up) { in tg3_setup_copper_phy()
4804 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4805 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4810 tg3_phy_reset(tp); in tg3_setup_copper_phy()
4812 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4813 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4814 if (tg3_readphy(tp, MII_BMSR, &bmsr) || in tg3_setup_copper_phy()
4815 !tg3_flag(tp, INIT_COMPLETE)) in tg3_setup_copper_phy()
4819 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
4823 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4826 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4833 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4836 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4837 err = tg3_phy_reset(tp); in tg3_setup_copper_phy()
4839 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
4844 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_setup_copper_phy()
4845 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) { in tg3_setup_copper_phy()
4847 tg3_writephy(tp, 0x15, 0x0a75); in tg3_setup_copper_phy()
4848 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4849 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_setup_copper_phy()
4850 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4854 tg3_readphy(tp, MII_TG3_ISTAT, &val); in tg3_setup_copper_phy()
4855 tg3_readphy(tp, MII_TG3_ISTAT, &val); in tg3_setup_copper_phy()
4857 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4858 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); in tg3_setup_copper_phy()
4859 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4860 tg3_writephy(tp, MII_TG3_IMASK, ~0); in tg3_setup_copper_phy()
4862 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_setup_copper_phy()
4863 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_setup_copper_phy()
4864 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4865 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_setup_copper_phy()
4868 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); in tg3_setup_copper_phy()
4874 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4875 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4877 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4878 err = tg3_phy_auxctl_read(tp, in tg3_setup_copper_phy()
4882 tg3_phy_auxctl_write(tp, in tg3_setup_copper_phy()
4891 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4892 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4901 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); in tg3_setup_copper_phy()
4904 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && in tg3_setup_copper_phy()
4909 tg3_aux_stat_to_speed_duplex(tp, aux_stat, in tg3_setup_copper_phy()
4915 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
4916 if (tg3_readphy(tp, MII_BMCR, &bmcr)) in tg3_setup_copper_phy()
4926 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4927 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4929 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4930 bool eee_config_ok = tg3_phy_eee_config_ok(tp); in tg3_setup_copper_phy()
4934 tg3_phy_copper_an_config_ok(tp, &lcl_adv) && in tg3_setup_copper_phy()
4935 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) in tg3_setup_copper_phy()
4943 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4945 tg3_setup_eee(tp); in tg3_setup_copper_phy()
4946 tg3_phy_reset(tp); in tg3_setup_copper_phy()
4950 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4951 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4957 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4960 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4968 if (!tg3_readphy(tp, reg, &val) && (val & bit)) in tg3_setup_copper_phy()
4969 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4971 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); in tg3_setup_copper_phy()
4976 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4977 tg3_phy_copper_begin(tp); in tg3_setup_copper_phy()
4979 if (tg3_flag(tp, ROBOSWITCH)) { in tg3_setup_copper_phy()
4984 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4985 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4988 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4989 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || in tg3_setup_copper_phy()
4990 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
4994 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
4996 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4997 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
4998 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
5000 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5001 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
5002 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
5004 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5009 if (tg3_flag(tp, RGMII_MODE)) { in tg3_setup_copper_phy()
5013 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5015 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5018 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5026 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5027 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5028 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5030 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_setup_copper_phy()
5032 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5033 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5035 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5041 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5042 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) { in tg3_setup_copper_phy()
5043 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5044 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5048 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5051 tg3_phy_eee_adjust(tp, current_link_up); in tg3_setup_copper_phy()
5053 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_setup_copper_phy()
5061 if (tg3_asic_rev(tp) == ASIC_REV_5700 && in tg3_setup_copper_phy()
5063 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5064 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { in tg3_setup_copper_phy()
5070 tg3_write_mem(tp, in tg3_setup_copper_phy()
5076 if (tg3_flag(tp, CLKREQ_BUG)) { in tg3_setup_copper_phy()
5077 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5078 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5079 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5082 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5086 tg3_test_and_report_link_chg(tp, current_link_up); in tg3_setup_copper_phy()
5155 static int tg3_fiber_aneg_smachine(struct tg3 *tp, in tg3_fiber_aneg_smachine() argument
5235 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5236 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5258 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5264 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5265 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5279 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5280 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5365 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5366 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5407 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) in fiber_autoneg() argument
5417 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5421 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5430 status = tg3_fiber_aneg_smachine(tp, &aninfo); in fiber_autoneg()
5437 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5438 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5452 static void tg3_init_bcm8002(struct tg3 *tp) in tg3_init_bcm8002() argument
5458 if (tg3_flag(tp, INIT_COMPLETE) && in tg3_init_bcm8002()
5463 tg3_writephy(tp, 0x16, 0x8007); in tg3_init_bcm8002()
5466 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_init_bcm8002()
5474 tg3_writephy(tp, 0x10, 0x8411); in tg3_init_bcm8002()
5477 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5479 tg3_writephy(tp, 0x18, 0x00a0); in tg3_init_bcm8002()
5480 tg3_writephy(tp, 0x16, 0x41ff); in tg3_init_bcm8002()
5483 tg3_writephy(tp, 0x13, 0x0400); in tg3_init_bcm8002()
5485 tg3_writephy(tp, 0x13, 0x0000); in tg3_init_bcm8002()
5487 tg3_writephy(tp, 0x11, 0x0a50); in tg3_init_bcm8002()
5489 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5499 tg3_writephy(tp, 0x10, 0x8011); in tg3_init_bcm8002()
5502 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) in tg3_setup_fiber_hw_autoneg() argument
5516 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 && in tg3_setup_fiber_hw_autoneg()
5517 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) { in tg3_setup_fiber_hw_autoneg()
5529 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5544 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5553 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5560 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5561 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5565 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5576 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5577 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5597 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5600 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_hw_autoneg()
5602 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5603 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5605 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5606 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5628 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5630 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5632 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5639 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5640 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5647 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) in tg3_setup_fiber_by_hand() argument
5654 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5658 if (fiber_autoneg(tp, &txflags, &rxflags)) { in tg3_setup_fiber_by_hand()
5671 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5674 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_by_hand()
5696 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_by_hand()
5701 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5704 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5712 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset) in tg3_setup_fiber_phy() argument
5721 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5722 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5723 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5725 if (!tg3_flag(tp, HW_AUTONEG) && in tg3_setup_fiber_phy()
5726 tp->link_up && in tg3_setup_fiber_phy()
5727 tg3_flag(tp, INIT_COMPLETE)) { in tg3_setup_fiber_phy()
5743 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5744 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5745 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5748 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5749 tg3_init_bcm8002(tp); in tg3_setup_fiber_phy()
5756 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5759 if (tg3_flag(tp, HW_AUTONEG)) in tg3_setup_fiber_phy()
5760 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); in tg3_setup_fiber_phy()
5762 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); in tg3_setup_fiber_phy()
5764 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5766 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5781 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5782 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5783 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5786 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5791 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5792 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5793 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5797 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5798 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5799 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5804 if (!tg3_test_and_report_link_chg(tp, current_link_up)) { in tg3_setup_fiber_phy()
5805 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5807 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5808 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5809 tg3_link_report(tp); in tg3_setup_fiber_phy()
5815 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset) in tg3_setup_fiber_mii_phy() argument
5824 if ((tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_setup_fiber_mii_phy()
5825 tg3_asic_rev(tp) == ASIC_REV_5720) && in tg3_setup_fiber_mii_phy()
5826 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) && in tg3_setup_fiber_mii_phy()
5830 tg3_phy_reset(tp); in tg3_setup_fiber_mii_phy()
5832 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5835 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5840 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5843 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5846 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5855 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5858 tg3_clear_mac_status(tp); in tg3_setup_fiber_mii_phy()
5863 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5864 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5867 tg3_clear_mac_status(tp); in tg3_setup_fiber_mii_phy()
5870 tg3_phy_reset(tp); in tg3_setup_fiber_mii_phy()
5872 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5874 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5875 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5876 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
5883 err |= tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_fiber_mii_phy()
5885 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5886 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5888 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5891 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5897 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5898 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5901 tg3_writephy(tp, MII_ADVERTISE, newadv); in tg3_setup_fiber_mii_phy()
5903 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_setup_fiber_mii_phy()
5906 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5907 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5917 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5927 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5930 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5934 tg3_writephy(tp, MII_ADVERTISE, adv); in tg3_setup_fiber_mii_phy()
5935 tg3_writephy(tp, MII_BMCR, bmcr | in tg3_setup_fiber_mii_phy()
5939 tg3_carrier_off(tp); in tg3_setup_fiber_mii_phy()
5941 tg3_writephy(tp, MII_BMCR, new_bmcr); in tg3_setup_fiber_mii_phy()
5943 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5944 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5945 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
5951 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5969 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); in tg3_setup_fiber_mii_phy()
5970 err |= tg3_readphy(tp, MII_LPA, &remote_adv); in tg3_setup_fiber_mii_phy()
5979 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5981 } else if (!tg3_flag(tp, 5780_CLASS)) { in tg3_setup_fiber_mii_phy()
5991 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_mii_phy()
5993 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5994 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
5995 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5997 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
6002 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
6003 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
6005 tg3_test_and_report_link_chg(tp, current_link_up); in tg3_setup_fiber_mii_phy()
6009 static void tg3_serdes_parallel_detect(struct tg3 *tp) in tg3_serdes_parallel_detect() argument
6011 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
6013 tp->serdes_counter--; in tg3_serdes_parallel_detect()
6017 if (!tp->link_up && in tg3_serdes_parallel_detect()
6018 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6021 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_serdes_parallel_detect()
6026 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); in tg3_serdes_parallel_detect()
6027 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); in tg3_serdes_parallel_detect()
6030 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6032 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6033 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6043 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_serdes_parallel_detect()
6044 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6047 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6048 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6049 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6053 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6055 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6060 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_serdes_parallel_detect()
6061 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); in tg3_serdes_parallel_detect()
6063 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6069 static int tg3_setup_phy(struct tg3 *tp, bool force_reset) in tg3_setup_phy() argument
6074 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6075 err = tg3_setup_fiber_phy(tp, force_reset); in tg3_setup_phy()
6076 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6077 err = tg3_setup_fiber_mii_phy(tp, force_reset); in tg3_setup_phy()
6079 err = tg3_setup_copper_phy(tp, force_reset); in tg3_setup_phy()
6081 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { in tg3_setup_phy()
6099 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_setup_phy()
6100 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_setup_phy()
6105 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6106 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6113 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_setup_phy()
6114 if (tp->link_up) { in tg3_setup_phy()
6116 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6122 if (tg3_flag(tp, ASPM_WORKAROUND)) { in tg3_setup_phy()
6124 if (!tp->link_up) in tg3_setup_phy()
6126 tp->pwrmgmt_thresh; in tg3_setup_phy()
6136 static u64 tg3_refclk_read(struct tg3 *tp, struct ptp_system_timestamp *sts) in tg3_refclk_read() argument
6149 static void tg3_refclk_write(struct tg3 *tp, u64 newval) in tg3_refclk_write() argument
6159 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6160 static inline void tg3_full_unlock(struct tg3 *tp);
6163 struct tg3 *tp = netdev_priv(dev); in tg3_get_ts_info() local
6169 if (tg3_flag(tp, PTP_CAPABLE)) { in tg3_get_ts_info()
6175 if (tp->ptp_clock) in tg3_get_ts_info()
6176 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6191 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_adjfreq() local
6211 tg3_full_lock(tp, 0); in tg3_ptp_adjfreq()
6220 tg3_full_unlock(tp); in tg3_ptp_adjfreq()
6227 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_adjtime() local
6229 tg3_full_lock(tp, 0); in tg3_ptp_adjtime()
6230 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6231 tg3_full_unlock(tp); in tg3_ptp_adjtime()
6240 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_gettimex() local
6242 tg3_full_lock(tp, 0); in tg3_ptp_gettimex()
6243 ns = tg3_refclk_read(tp, sts); in tg3_ptp_gettimex()
6244 ns += tp->ptp_adjust; in tg3_ptp_gettimex()
6245 tg3_full_unlock(tp); in tg3_ptp_gettimex()
6256 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_settime() local
6260 tg3_full_lock(tp, 0); in tg3_ptp_settime()
6261 tg3_refclk_write(tp, ns); in tg3_ptp_settime()
6262 tp->ptp_adjust = 0; in tg3_ptp_settime()
6263 tg3_full_unlock(tp); in tg3_ptp_settime()
6271 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_enable() local
6284 tg3_full_lock(tp, 0); in tg3_ptp_enable()
6295 netdev_warn(tp->dev, in tg3_ptp_enable()
6302 netdev_warn(tp->dev, in tg3_ptp_enable()
6321 tg3_full_unlock(tp); in tg3_ptp_enable()
6347 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock, in tg3_hwclock_to_timestamp() argument
6352 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6356 static void tg3_ptp_init(struct tg3 *tp) in tg3_ptp_init() argument
6358 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_ptp_init()
6362 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real())); in tg3_ptp_init()
6363 tp->ptp_adjust = 0; in tg3_ptp_init()
6364 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6368 static void tg3_ptp_resume(struct tg3 *tp) in tg3_ptp_resume() argument
6370 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_ptp_resume()
6373 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6374 tp->ptp_adjust = 0; in tg3_ptp_resume()
6377 static void tg3_ptp_fini(struct tg3 *tp) in tg3_ptp_fini() argument
6379 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6382 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6383 tp->ptp_clock = NULL; in tg3_ptp_fini()
6384 tp->ptp_adjust = 0; in tg3_ptp_fini()
6387 static inline int tg3_irq_sync(struct tg3 *tp) in tg3_irq_sync() argument
6389 return tp->irq_sync; in tg3_irq_sync()
6392 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) in tg3_rd32_loop() argument
6401 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) in tg3_dump_legacy_regs() argument
6403 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); in tg3_dump_legacy_regs()
6404 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); in tg3_dump_legacy_regs()
6405 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); in tg3_dump_legacy_regs()
6406 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); in tg3_dump_legacy_regs()
6407 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); in tg3_dump_legacy_regs()
6408 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); in tg3_dump_legacy_regs()
6409 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); in tg3_dump_legacy_regs()
6410 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); in tg3_dump_legacy_regs()
6411 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); in tg3_dump_legacy_regs()
6412 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); in tg3_dump_legacy_regs()
6413 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); in tg3_dump_legacy_regs()
6414 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); in tg3_dump_legacy_regs()
6415 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); in tg3_dump_legacy_regs()
6416 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); in tg3_dump_legacy_regs()
6417 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); in tg3_dump_legacy_regs()
6418 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); in tg3_dump_legacy_regs()
6419 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); in tg3_dump_legacy_regs()
6420 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); in tg3_dump_legacy_regs()
6421 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); in tg3_dump_legacy_regs()
6423 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_dump_legacy_regs()
6424 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); in tg3_dump_legacy_regs()
6426 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); in tg3_dump_legacy_regs()
6427 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); in tg3_dump_legacy_regs()
6428 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6429 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6430 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6431 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6432 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6433 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); in tg3_dump_legacy_regs()
6435 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_dump_legacy_regs()
6436 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6437 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6438 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6441 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); in tg3_dump_legacy_regs()
6442 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); in tg3_dump_legacy_regs()
6443 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); in tg3_dump_legacy_regs()
6444 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); in tg3_dump_legacy_regs()
6445 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); in tg3_dump_legacy_regs()
6447 if (tg3_flag(tp, NVRAM)) in tg3_dump_legacy_regs()
6448 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); in tg3_dump_legacy_regs()
6451 static void tg3_dump_state(struct tg3 *tp) in tg3_dump_state() argument
6460 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_dump_state()
6465 tg3_dump_legacy_regs(tp, regs); in tg3_dump_state()
6472 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6479 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6480 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6483 netdev_err(tp->dev, in tg3_dump_state()
6494 netdev_err(tp->dev, in tg3_dump_state()
6513 static void tg3_tx_recover(struct tg3 *tp) in tg3_tx_recover() argument
6515 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || in tg3_tx_recover()
6516 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6518 netdev_warn(tp->dev, in tg3_tx_recover()
6524 tg3_flag_set(tp, TX_RECOVERY_PENDING); in tg3_tx_recover()
6541 struct tg3 *tp = tnapi->tp; in tg3_tx() local
6545 int index = tnapi - tp->napi; in tg3_tx()
6548 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx()
6551 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6559 tg3_tx_recover(tp); in tg3_tx()
6568 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp); in tg3_tx()
6573 pci_unmap_single(tp->pdev, in tg3_tx()
6593 pci_unmap_page(tp->pdev, in tg3_tx()
6613 tg3_tx_recover(tp); in tg3_tx()
6647 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) in tg3_rx_data_free() argument
6649 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) + in tg3_rx_data_free()
6655 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping), in tg3_rx_data_free()
6673 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, in tg3_alloc_rx_data() argument
6685 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6688 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6692 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6708 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) + in tg3_alloc_rx_data()
6720 mapping = pci_map_single(tp->pdev, in tg3_alloc_rx_data()
6721 data + TG3_RX_OFFSET(tp), in tg3_alloc_rx_data()
6724 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) { in tg3_alloc_rx_data()
6747 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx() local
6750 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6755 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6763 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6814 struct tg3 *tp = tnapi->tp; in tg3_rx() local
6845 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6851 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6866 tp->rx_dropped++; in tg3_rx()
6870 prefetch(data + TG3_RX_OFFSET(tp)); in tg3_rx()
6882 if (len > TG3_RX_COPY_THRESH(tp)) { in tg3_rx()
6886 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key, in tg3_rx()
6891 pci_unmap_single(tp->pdev, dma_addr, skb_size, in tg3_rx()
6906 skb_reserve(skb, TG3_RX_OFFSET(tp)); in tg3_rx()
6911 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6917 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in tg3_rx()
6919 data + TG3_RX_OFFSET(tp), in tg3_rx()
6921 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE); in tg3_rx()
6926 tg3_hwclock_to_timestamp(tp, tstamp, in tg3_rx()
6929 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6937 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6939 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6947 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6959 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6961 tp->rx_std_ring_mask; in tg3_rx()
6969 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
6983 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_rx()
6989 tp->rx_std_ring_mask; in tg3_rx()
6995 tp->rx_jmb_ring_mask; in tg3_rx()
7005 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
7006 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
7008 if (tnapi != &tp->napi[1]) { in tg3_rx()
7009 tp->rx_refill = true; in tg3_rx()
7010 napi_schedule(&tp->napi[1].napi); in tg3_rx()
7017 static void tg3_poll_link(struct tg3 *tp) in tg3_poll_link() argument
7020 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_poll_link()
7021 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7026 spin_lock(&tp->lock); in tg3_poll_link()
7027 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_poll_link()
7035 tg3_setup_phy(tp, false); in tg3_poll_link()
7036 spin_unlock(&tp->lock); in tg3_poll_link()
7041 static int tg3_rx_prodring_xfer(struct tg3 *tp, in tg3_rx_prodring_xfer() argument
7062 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7066 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7101 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7103 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7120 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7124 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7159 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7161 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7169 struct tg3 *tp = tnapi->tp; in tg3_poll_work() local
7174 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_work()
7188 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7189 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7194 tp->rx_refill = false; in tg3_poll_work()
7195 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7196 err |= tg3_rx_prodring_xfer(tp, dpr, in tg3_poll_work()
7197 &tp->napi[i].prodring); in tg3_poll_work()
7210 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7216 static inline void tg3_reset_task_schedule(struct tg3 *tp) in tg3_reset_task_schedule() argument
7218 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7219 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7222 static inline void tg3_reset_task_cancel(struct tg3 *tp) in tg3_reset_task_cancel() argument
7224 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_cancel()
7225 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7226 tg3_flag_clear(tp, TX_RECOVERY_PENDING); in tg3_reset_task_cancel()
7232 struct tg3 *tp = tnapi->tp; in tg3_poll_msix() local
7239 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_msix()
7260 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7270 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7271 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7279 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1); in tg3_poll_msix()
7285 tg3_reset_task_schedule(tp); in tg3_poll_msix()
7289 static void tg3_process_error(struct tg3 *tp) in tg3_process_error() argument
7294 if (tg3_flag(tp, ERROR_PROCESSED)) in tg3_process_error()
7300 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7305 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7310 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7317 tg3_dump_state(tp); in tg3_process_error()
7319 tg3_flag_set(tp, ERROR_PROCESSED); in tg3_process_error()
7320 tg3_reset_task_schedule(tp); in tg3_process_error()
7326 struct tg3 *tp = tnapi->tp; in tg3_poll() local
7332 tg3_process_error(tp); in tg3_poll()
7334 tg3_poll_link(tp); in tg3_poll()
7338 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll()
7344 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_poll()
7362 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1); in tg3_poll()
7368 tg3_reset_task_schedule(tp); in tg3_poll()
7372 static void tg3_napi_disable(struct tg3 *tp) in tg3_napi_disable() argument
7376 for (i = tp->irq_cnt - 1; i >= 0; i--) in tg3_napi_disable()
7377 napi_disable(&tp->napi[i].napi); in tg3_napi_disable()
7380 static void tg3_napi_enable(struct tg3 *tp) in tg3_napi_enable() argument
7384 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_enable()
7385 napi_enable(&tp->napi[i].napi); in tg3_napi_enable()
7388 static void tg3_napi_init(struct tg3 *tp) in tg3_napi_init() argument
7392 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64); in tg3_napi_init()
7393 for (i = 1; i < tp->irq_cnt; i++) in tg3_napi_init()
7394 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64); in tg3_napi_init()
7397 static void tg3_napi_fini(struct tg3 *tp) in tg3_napi_fini() argument
7401 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7402 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7405 static inline void tg3_netif_stop(struct tg3 *tp) in tg3_netif_stop() argument
7407 netif_trans_update(tp->dev); /* prevent tx timeout */ in tg3_netif_stop()
7408 tg3_napi_disable(tp); in tg3_netif_stop()
7409 netif_carrier_off(tp->dev); in tg3_netif_stop()
7410 netif_tx_disable(tp->dev); in tg3_netif_stop()
7414 static inline void tg3_netif_start(struct tg3 *tp) in tg3_netif_start() argument
7416 tg3_ptp_resume(tp); in tg3_netif_start()
7422 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7424 if (tp->link_up) in tg3_netif_start()
7425 netif_carrier_on(tp->dev); in tg3_netif_start()
7427 tg3_napi_enable(tp); in tg3_netif_start()
7428 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7429 tg3_enable_ints(tp); in tg3_netif_start()
7432 static void tg3_irq_quiesce(struct tg3 *tp) in tg3_irq_quiesce() argument
7433 __releases(tp->lock) in tg3_irq_quiesce()
7434 __acquires(tp->lock) in tg3_irq_quiesce()
7438 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7440 tp->irq_sync = 1; in tg3_irq_quiesce()
7443 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7445 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7446 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7448 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7456 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) in tg3_full_lock() argument
7458 spin_lock_bh(&tp->lock); in tg3_full_lock()
7460 tg3_irq_quiesce(tp); in tg3_full_lock()
7463 static inline void tg3_full_unlock(struct tg3 *tp) in tg3_full_unlock() argument
7465 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7474 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot() local
7480 if (likely(!tg3_irq_sync(tp))) in tg3_msi_1shot()
7493 struct tg3 *tp = tnapi->tp; in tg3_msi() local
7506 if (likely(!tg3_irq_sync(tp))) in tg3_msi()
7515 struct tg3 *tp = tnapi->tp; in tg3_interrupt() local
7525 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt()
7544 if (tg3_irq_sync(tp)) in tg3_interrupt()
7564 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged() local
7574 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt_tagged()
7602 if (tg3_irq_sync(tp)) in tg3_interrupt_tagged()
7617 struct tg3 *tp = tnapi->tp; in tg3_test_isr() local
7622 tg3_disable_ints(tp); in tg3_test_isr()
7632 struct tg3 *tp = netdev_priv(dev); in tg3_poll_controller() local
7634 if (tg3_irq_sync(tp)) in tg3_poll_controller()
7637 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7638 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7644 struct tg3 *tp = netdev_priv(dev); in tg3_tx_timeout() local
7646 if (netif_msg_tx_err(tp)) { in tg3_tx_timeout()
7648 tg3_dump_state(tp); in tg3_tx_timeout()
7651 tg3_reset_task_schedule(tp); in tg3_tx_timeout()
7665 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping, in tg3_4g_tso_overflow_test() argument
7668 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) { in tg3_4g_tso_overflow_test()
7677 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, in tg3_40bit_overflow_test() argument
7681 if (tg3_flag(tp, 40BIT_DMA_BUG)) in tg3_40bit_overflow_test()
7703 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set() local
7706 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) in tg3_tx_frag_set()
7712 if (tg3_4g_tso_overflow_test(tp, map, len, mss)) in tg3_tx_frag_set()
7715 if (tg3_40bit_overflow_test(tp, map, len)) in tg3_tx_frag_set()
7718 if (tp->dma_limit) { in tg3_tx_frag_set()
7721 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7722 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7723 len -= tp->dma_limit; in tg3_tx_frag_set()
7727 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7728 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7771 pci_unmap_single(tnapi->tp->pdev, in tg3_tx_skb_unmap()
7788 pci_unmap_page(tnapi->tp->pdev, in tg3_tx_skb_unmap()
7806 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround() local
7811 if (tg3_asic_rev(tp) != ASIC_REV_5701) in tigon3_dma_hwbug_workaround()
7825 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len, in tigon3_dma_hwbug_workaround()
7828 if (pci_dma_mapping_error(tp->pdev, new_addr)) { in tigon3_dma_hwbug_workaround()
7868 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi, in tg3_tso_bug() argument
7890 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7897 tg3_start_xmit(seg, tp->dev); in tg3_tso_bug()
7909 struct tg3 *tp = netdev_priv(dev); in tg3_start_xmit() local
7923 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in tg3_start_xmit()
7924 if (tg3_flag(tp, ENABLE_TSS)) in tg3_start_xmit()
7966 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
7972 tg3_flag(tp, TSO_BUG)) { in tg3_start_xmit()
7974 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
7989 if (tg3_flag(tp, HW_TSO_1) || in tg3_start_xmit()
7990 tg3_flag(tp, HW_TSO_2) || in tg3_start_xmit()
7991 tg3_flag(tp, HW_TSO_3)) { in tg3_start_xmit()
7999 if (tg3_flag(tp, HW_TSO_3)) { in tg3_start_xmit()
8004 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_start_xmit()
8006 else if (tg3_flag(tp, HW_TSO_1) || in tg3_start_xmit()
8007 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_start_xmit()
8035 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in tg3_start_xmit()
8045 tg3_flag(tp, TX_TSTAMP_EN)) { in tg3_start_xmit()
8052 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE); in tg3_start_xmit()
8053 if (pci_dma_mapping_error(tp->pdev, mapping)) in tg3_start_xmit()
8062 if (tg3_flag(tp, 5701_DMA_BUG)) in tg3_start_xmit()
8072 if (!tg3_flag(tp, HW_TSO_1) && in tg3_start_xmit()
8073 !tg3_flag(tp, HW_TSO_2) && in tg3_start_xmit()
8074 !tg3_flag(tp, HW_TSO_3)) in tg3_start_xmit()
8085 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in tg3_start_xmit()
8091 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8117 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
8163 tp->tx_dropped++; in tg3_start_xmit()
8167 static void tg3_mac_loopback(struct tg3 *tp, bool enable) in tg3_mac_loopback() argument
8170 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8173 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8175 if (!tg3_flag(tp, 5705_PLUS)) in tg3_mac_loopback()
8176 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8178 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8179 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8181 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8183 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8185 if (tg3_flag(tp, 5705_PLUS) || in tg3_mac_loopback()
8186 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8187 tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_mac_loopback()
8188 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8191 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8195 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) in tg3_phy_lpbk_set() argument
8199 tg3_phy_toggle_apd(tp, false); in tg3_phy_lpbk_set()
8200 tg3_phy_toggle_automdix(tp, false); in tg3_phy_lpbk_set()
8202 if (extlpbk && tg3_phy_set_extloopbk(tp)) in tg3_phy_lpbk_set()
8214 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8224 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8225 tg3_readphy(tp, MII_CTRL1000, &val); in tg3_phy_lpbk_set()
8228 tg3_writephy(tp, MII_CTRL1000, val); in tg3_phy_lpbk_set()
8232 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); in tg3_phy_lpbk_set()
8237 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_lpbk_set()
8240 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8241 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_phy_lpbk_set()
8245 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8246 tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_phy_lpbk_set()
8247 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | in tg3_phy_lpbk_set()
8252 tg3_readphy(tp, MII_TG3_FET_PTEST, &val); in tg3_phy_lpbk_set()
8256 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8257 tg3_flag(tp, 5780_CLASS)) { in tg3_phy_lpbk_set()
8260 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8263 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8270 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_phy_lpbk_set()
8271 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8278 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_lpbk_set()
8290 struct tg3 *tp = netdev_priv(dev); in tg3_set_loopback() local
8293 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8296 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8297 tg3_mac_loopback(tp, true); in tg3_set_loopback()
8298 netif_carrier_on(tp->dev); in tg3_set_loopback()
8299 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8302 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8305 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8306 tg3_mac_loopback(tp, false); in tg3_set_loopback()
8308 tg3_setup_phy(tp, true); in tg3_set_loopback()
8309 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8317 struct tg3 *tp = netdev_priv(dev); in tg3_fix_features() local
8319 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8335 static void tg3_rx_prodring_free(struct tg3 *tp, in tg3_rx_prodring_free() argument
8340 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8342 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8343 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8344 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8346 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_rx_prodring_free()
8349 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8350 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8358 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8359 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8360 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8362 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_free()
8363 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8364 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8376 static int tg3_rx_prodring_alloc(struct tg3 *tp, in tg3_rx_prodring_alloc() argument
8386 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8388 TG3_RX_STD_BUFF_RING_SIZE(tp)); in tg3_rx_prodring_alloc()
8391 TG3_RX_JMB_BUFF_RING_SIZE(tp)); in tg3_rx_prodring_alloc()
8396 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8399 if (tg3_flag(tp, 5780_CLASS) && in tg3_rx_prodring_alloc()
8400 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8402 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8408 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8419 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8422 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i, in tg3_rx_prodring_alloc()
8424 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8427 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8430 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8435 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_rx_prodring_alloc()
8438 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8440 if (!tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_rx_prodring_alloc()
8443 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8454 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8457 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i, in tg3_rx_prodring_alloc()
8459 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8462 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8465 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8474 tg3_rx_prodring_free(tp, tpr); in tg3_rx_prodring_alloc()
8478 static void tg3_rx_prodring_fini(struct tg3 *tp, in tg3_rx_prodring_fini() argument
8486 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8491 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8497 static int tg3_rx_prodring_init(struct tg3 *tp, in tg3_rx_prodring_init() argument
8500 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8505 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8506 TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_init()
8512 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_init()
8513 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8518 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8519 TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_init()
8529 tg3_rx_prodring_fini(tp, tpr); in tg3_rx_prodring_init()
8540 static void tg3_free_rings(struct tg3 *tp) in tg3_free_rings() argument
8544 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8545 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8547 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8563 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8574 static int tg3_init_rings(struct tg3 *tp) in tg3_init_rings() argument
8579 tg3_free_rings(tp); in tg3_init_rings()
8581 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8582 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8597 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8600 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8601 tg3_free_rings(tp); in tg3_init_rings()
8609 static void tg3_mem_tx_release(struct tg3 *tp) in tg3_mem_tx_release() argument
8613 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8614 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8617 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8627 static int tg3_mem_tx_acquire(struct tg3 *tp) in tg3_mem_tx_acquire() argument
8630 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8635 if (tg3_flag(tp, ENABLE_TSS)) in tg3_mem_tx_acquire()
8638 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8645 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8656 tg3_mem_tx_release(tp); in tg3_mem_tx_acquire()
8660 static void tg3_mem_rx_release(struct tg3 *tp) in tg3_mem_rx_release() argument
8664 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8665 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8667 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8672 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8673 TG3_RX_RCB_RING_BYTES(tp), in tg3_mem_rx_release()
8680 static int tg3_mem_rx_acquire(struct tg3 *tp) in tg3_mem_rx_acquire() argument
8684 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8689 if (tg3_flag(tp, ENABLE_RSS)) in tg3_mem_rx_acquire()
8693 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8695 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8702 if (!i && tg3_flag(tp, ENABLE_RSS)) in tg3_mem_rx_acquire()
8705 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8706 TG3_RX_RCB_RING_BYTES(tp), in tg3_mem_rx_acquire()
8716 tg3_mem_rx_release(tp); in tg3_mem_rx_acquire()
8724 static void tg3_free_consistent(struct tg3 *tp) in tg3_free_consistent() argument
8728 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8729 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8732 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8739 tg3_mem_rx_release(tp); in tg3_free_consistent()
8740 tg3_mem_tx_release(tp); in tg3_free_consistent()
8746 if (tp->hw_stats) { in tg3_free_consistent()
8747 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8748 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8749 tp->hw_stats = NULL; in tg3_free_consistent()
8757 static int tg3_alloc_consistent(struct tg3 *tp) in tg3_alloc_consistent() argument
8761 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8763 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8764 if (!tp->hw_stats) in tg3_alloc_consistent()
8767 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8768 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8771 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8780 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_alloc_consistent()
8809 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp)) in tg3_alloc_consistent()
8815 tg3_free_consistent(tp); in tg3_alloc_consistent()
8824 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent) in tg3_stop_block() argument
8829 if (tg3_flag(tp, 5705_PLUS)) { in tg3_stop_block()
8851 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8852 dev_err(&tp->pdev->dev, in tg3_stop_block()
8866 dev_err(&tp->pdev->dev, in tg3_stop_block()
8876 static int tg3_abort_hw(struct tg3 *tp, bool silent) in tg3_abort_hw() argument
8880 tg3_disable_ints(tp); in tg3_abort_hw()
8882 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8883 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8884 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8889 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8890 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
8893 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8894 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); in tg3_abort_hw()
8895 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); in tg3_abort_hw()
8896 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8897 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); in tg3_abort_hw()
8898 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); in tg3_abort_hw()
8900 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); in tg3_abort_hw()
8901 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8902 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); in tg3_abort_hw()
8903 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8904 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); in tg3_abort_hw()
8905 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8906 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); in tg3_abort_hw()
8908 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8909 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
8912 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
8913 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
8921 dev_err(&tp->pdev->dev, in tg3_abort_hw()
8927 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); in tg3_abort_hw()
8928 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8929 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); in tg3_abort_hw()
8934 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); in tg3_abort_hw()
8935 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); in tg3_abort_hw()
8938 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
8939 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
8948 static void tg3_save_pci_state(struct tg3 *tp) in tg3_save_pci_state() argument
8950 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
8954 static void tg3_restore_pci_state(struct tg3 *tp) in tg3_restore_pci_state() argument
8959 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
8960 tp->misc_host_ctrl); in tg3_restore_pci_state()
8964 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && in tg3_restore_pci_state()
8965 tg3_flag(tp, PCIX_MODE)) in tg3_restore_pci_state()
8968 if (tg3_flag(tp, ENABLE_APE)) in tg3_restore_pci_state()
8972 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
8974 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
8976 if (!tg3_flag(tp, PCI_EXPRESS)) { in tg3_restore_pci_state()
8977 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
8978 tp->pci_cacheline_sz); in tg3_restore_pci_state()
8979 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
8980 tp->pci_lat_timer); in tg3_restore_pci_state()
8984 if (tg3_flag(tp, PCIX_MODE)) { in tg3_restore_pci_state()
8987 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8990 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8994 if (tg3_flag(tp, 5780_CLASS)) { in tg3_restore_pci_state()
8999 if (tg3_flag(tp, USING_MSI)) { in tg3_restore_pci_state()
9002 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
9003 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9005 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
9006 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9014 static void tg3_override_clk(struct tg3 *tp) in tg3_override_clk() argument
9018 switch (tg3_asic_rev(tp)) { in tg3_override_clk()
9035 static void tg3_restore_clk(struct tg3 *tp) in tg3_restore_clk() argument
9039 switch (tg3_asic_rev(tp)) { in tg3_restore_clk()
9058 static int tg3_chip_reset(struct tg3 *tp) in tg3_chip_reset() argument
9059 __releases(tp->lock) in tg3_chip_reset()
9060 __acquires(tp->lock) in tg3_chip_reset()
9066 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9069 tg3_nvram_lock(tp); in tg3_chip_reset()
9071 tg3_ape_lock(tp, TG3_APE_LOCK_GRC); in tg3_chip_reset()
9076 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9082 tg3_save_pci_state(tp); in tg3_chip_reset()
9084 if (tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_chip_reset()
9085 tg3_flag(tp, 5755_PLUS)) in tg3_chip_reset()
9094 write_op = tp->write32; in tg3_chip_reset()
9096 tp->write32 = tg3_write32; in tg3_chip_reset()
9104 tg3_flag_set(tp, CHIP_RESETTING); in tg3_chip_reset()
9105 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9106 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9116 tg3_full_unlock(tp); in tg3_chip_reset()
9118 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9119 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9121 tg3_full_lock(tp, 0); in tg3_chip_reset()
9123 if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_chip_reset()
9131 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_chip_reset()
9133 if (tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_chip_reset()
9134 !tg3_flag(tp, 57765_PLUS) && in tg3_chip_reset()
9139 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) { in tg3_chip_reset()
9145 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_chip_reset()
9156 tg3_override_clk(tp); in tg3_chip_reset()
9159 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
9165 tp->write32 = write_op; in tg3_chip_reset()
9188 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9192 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9195 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) { in tg3_chip_reset()
9203 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9204 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9214 if (!tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
9216 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9219 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9226 tg3_restore_pci_state(tp); in tg3_chip_reset()
9228 tg3_flag_clear(tp, CHIP_RESETTING); in tg3_chip_reset()
9229 tg3_flag_clear(tp, ERROR_PROCESSED); in tg3_chip_reset()
9232 if (tg3_flag(tp, 5780_CLASS)) in tg3_chip_reset()
9236 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) { in tg3_chip_reset()
9237 tg3_stop_fw(tp); in tg3_chip_reset()
9241 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_chip_reset()
9247 tg3_stop_fw(tp); in tg3_chip_reset()
9248 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_chip_reset()
9251 err = tg3_poll_fw(tp); in tg3_chip_reset()
9255 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9257 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) { in tg3_chip_reset()
9263 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9264 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_chip_reset()
9265 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9266 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) in tg3_chip_reset()
9267 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9268 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9271 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9272 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9273 val = tp->mac_mode; in tg3_chip_reset()
9274 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9275 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9276 val = tp->mac_mode; in tg3_chip_reset()
9283 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); in tg3_chip_reset()
9285 tg3_mdio_start(tp); in tg3_chip_reset()
9287 if (tg3_flag(tp, PCI_EXPRESS) && in tg3_chip_reset()
9288 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && in tg3_chip_reset()
9289 tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_chip_reset()
9290 !tg3_flag(tp, 57765_PLUS)) { in tg3_chip_reset()
9296 tg3_restore_clk(tp); in tg3_chip_reset()
9301 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_chip_reset()
9308 tg3_flag_clear(tp, ENABLE_ASF); in tg3_chip_reset()
9309 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9312 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); in tg3_chip_reset()
9313 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); in tg3_chip_reset()
9317 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); in tg3_chip_reset()
9319 tg3_flag_set(tp, ENABLE_ASF); in tg3_chip_reset()
9320 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9321 if (tg3_flag(tp, 5750_PLUS)) in tg3_chip_reset()
9322 tg3_flag_set(tp, ASF_NEW_HANDSHAKE); in tg3_chip_reset()
9324 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg); in tg3_chip_reset()
9326 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9328 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9340 static int tg3_halt(struct tg3 *tp, int kind, bool silent) in tg3_halt() argument
9344 tg3_stop_fw(tp); in tg3_halt()
9346 tg3_write_sig_pre_reset(tp, kind); in tg3_halt()
9348 tg3_abort_hw(tp, silent); in tg3_halt()
9349 err = tg3_chip_reset(tp); in tg3_halt()
9351 __tg3_set_mac_addr(tp, false); in tg3_halt()
9353 tg3_write_sig_legacy(tp, kind); in tg3_halt()
9354 tg3_write_sig_post_reset(tp, kind); in tg3_halt()
9356 if (tp->hw_stats) { in tg3_halt()
9358 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9359 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9362 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9370 struct tg3 *tp = netdev_priv(dev); in tg3_set_mac_addr() local
9383 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_set_mac_addr()
9396 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9397 __tg3_set_mac_addr(tp, skip_mac_1); in tg3_set_mac_addr()
9399 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9405 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, in tg3_set_bdinfo() argument
9409 tg3_write_mem(tp, in tg3_set_bdinfo()
9412 tg3_write_mem(tp, in tg3_set_bdinfo()
9415 tg3_write_mem(tp, in tg3_set_bdinfo()
9419 if (!tg3_flag(tp, 5705_PLUS)) in tg3_set_bdinfo()
9420 tg3_write_mem(tp, in tg3_set_bdinfo()
9426 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec) in tg3_coal_tx_init() argument
9430 if (!tg3_flag(tp, ENABLE_TSS)) { in tg3_coal_tx_init()
9439 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9451 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9458 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec) in tg3_coal_rx_init() argument
9461 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9463 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_coal_rx_init()
9485 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9492 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) in __tg3_set_coalesce() argument
9494 tg3_coal_tx_init(tp, ec); in __tg3_set_coalesce()
9495 tg3_coal_rx_init(tp, ec); in __tg3_set_coalesce()
9497 if (!tg3_flag(tp, 5705_PLUS)) { in __tg3_set_coalesce()
9503 if (!tp->link_up) in __tg3_set_coalesce()
9511 static void tg3_tx_rcbs_disable(struct tg3 *tp) in tg3_tx_rcbs_disable() argument
9516 if (!tg3_flag(tp, 5705_PLUS)) in tg3_tx_rcbs_disable()
9518 else if (tg3_flag(tp, 5717_PLUS)) in tg3_tx_rcbs_disable()
9520 else if (tg3_flag(tp, 57765_CLASS) || in tg3_tx_rcbs_disable()
9521 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_tx_rcbs_disable()
9528 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, in tg3_tx_rcbs_disable()
9533 static void tg3_tx_rcbs_init(struct tg3 *tp) in tg3_tx_rcbs_init() argument
9538 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx_rcbs_init()
9541 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9542 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9547 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9554 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp) in tg3_rx_ret_rcbs_disable() argument
9559 if (tg3_flag(tp, 5717_PLUS)) in tg3_rx_ret_rcbs_disable()
9561 else if (!tg3_flag(tp, 5705_PLUS)) in tg3_rx_ret_rcbs_disable()
9563 else if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_rx_ret_rcbs_disable()
9564 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_rx_ret_rcbs_disable()
9565 tg3_flag(tp, 57765_CLASS)) in tg3_rx_ret_rcbs_disable()
9572 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, in tg3_rx_ret_rcbs_disable()
9577 static void tg3_rx_ret_rcbs_init(struct tg3 *tp) in tg3_rx_ret_rcbs_init() argument
9582 if (tg3_flag(tp, ENABLE_RSS)) in tg3_rx_ret_rcbs_init()
9585 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9586 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9591 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9592 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9598 static void tg3_rings_reset(struct tg3 *tp) in tg3_rings_reset() argument
9602 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9604 tg3_tx_rcbs_disable(tp); in tg3_rings_reset()
9606 tg3_rx_ret_rcbs_disable(tp); in tg3_rings_reset()
9609 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9610 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9611 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9612 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9615 if (tg3_flag(tp, SUPPORT_MSIX)) { in tg3_rings_reset()
9616 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9617 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9618 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9619 if (tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
9620 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9621 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9622 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9623 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9624 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9625 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9627 if (!tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
9628 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9630 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9631 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9632 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9633 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9637 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_rings_reset()
9654 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9664 tg3_tx_rcbs_init(tp); in tg3_rings_reset()
9665 tg3_rx_ret_rcbs_init(tp); in tg3_rings_reset()
9668 static void tg3_setup_rxbd_thresholds(struct tg3 *tp) in tg3_setup_rxbd_thresholds() argument
9672 if (!tg3_flag(tp, 5750_PLUS) || in tg3_setup_rxbd_thresholds()
9673 tg3_flag(tp, 5780_CLASS) || in tg3_setup_rxbd_thresholds()
9674 tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_setup_rxbd_thresholds()
9675 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_setup_rxbd_thresholds()
9676 tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9678 else if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_setup_rxbd_thresholds()
9679 tg3_asic_rev(tp) == ASIC_REV_5787) in tg3_setup_rxbd_thresholds()
9684 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9685 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9690 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9693 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_setup_rxbd_thresholds()
9698 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9703 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9731 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) in tg3_set_multi() argument
9742 struct tg3 *tp = netdev_priv(dev); in __tg3_set_rx_mode() local
9745 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9752 if (!tg3_flag(tp, ENABLE_ASF)) in __tg3_set_rx_mode()
9761 tg3_set_multi(tp, 1); in __tg3_set_rx_mode()
9764 tg3_set_multi(tp, 0); in __tg3_set_rx_mode()
9787 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) { in __tg3_set_rx_mode()
9795 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9796 i + TG3_UCAST_ADDR_IDX(tp)); in __tg3_set_rx_mode()
9801 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9802 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9808 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt) in tg3_rss_init_dflt_indir_tbl() argument
9813 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9816 static void tg3_rss_check_indir_tbl(struct tg3 *tp) in tg3_rss_check_indir_tbl() argument
9820 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_rss_check_indir_tbl()
9823 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9824 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9830 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9835 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9838 static void tg3_rss_write_indir_tbl(struct tg3 *tp) in tg3_rss_write_indir_tbl() argument
9844 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9848 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9855 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp) in tg3_lso_rd_dma_workaround_bit() argument
9857 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_lso_rd_dma_workaround_bit()
9864 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) in tg3_reset_hw() argument
9868 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9870 tg3_disable_ints(tp); in tg3_reset_hw()
9872 tg3_stop_fw(tp); in tg3_reset_hw()
9874 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); in tg3_reset_hw()
9876 if (tg3_flag(tp, INIT_COMPLETE)) in tg3_reset_hw()
9877 tg3_abort_hw(tp, 1); in tg3_reset_hw()
9879 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9880 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9881 tg3_phy_pull_config(tp); in tg3_reset_hw()
9882 tg3_eee_pull_config(tp, NULL); in tg3_reset_hw()
9883 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9887 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
9888 tg3_setup_eee(tp); in tg3_reset_hw()
9891 tg3_phy_reset(tp); in tg3_reset_hw()
9893 err = tg3_chip_reset(tp); in tg3_reset_hw()
9897 tg3_write_sig_legacy(tp, RESET_KIND_INIT); in tg3_reset_hw()
9899 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { in tg3_reset_hw()
9920 if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_reset_hw()
9935 if (tg3_flag(tp, L1PLLPD_EN)) { in tg3_reset_hw()
9949 if (tg3_flag(tp, 57765_CLASS)) { in tg3_reset_hw()
9950 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { in tg3_reset_hw()
9965 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) { in tg3_reset_hw()
9999 if (!tg3_flag(tp, CPMU_PRESENT)) { in tg3_reset_hw()
10000 if (!tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
10001 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
10002 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
10005 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && in tg3_reset_hw()
10006 tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
10012 if (tg3_flag(tp, ENABLE_APE)) { in tg3_reset_hw()
10023 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) { in tg3_reset_hw()
10035 err = tg3_init_rings(tp); in tg3_reset_hw()
10039 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10042 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) in tg3_reset_hw()
10044 if (!tg3_flag(tp, 57765_CLASS) && in tg3_reset_hw()
10045 tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_reset_hw()
10046 tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_reset_hw()
10048 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10049 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 && in tg3_reset_hw()
10050 tg3_asic_rev(tp) != ASIC_REV_5761) { in tg3_reset_hw()
10054 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10057 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10061 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10069 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10072 if (tp->rxptpctl) in tg3_reset_hw()
10074 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10076 if (tg3_flag(tp, PTP_CAPABLE)) in tg3_reset_hw()
10079 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10085 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_reset_hw()
10086 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) { in tg3_reset_hw()
10098 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
10100 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) { in tg3_reset_hw()
10102 if (tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_reset_hw()
10108 } else if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10111 fw_len = tp->fw_len; in tg3_reset_hw()
10119 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10121 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10123 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10125 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10128 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10130 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10132 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10135 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10137 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10140 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_reset_hw()
10142 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_reset_hw()
10143 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_reset_hw()
10144 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10145 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) in tg3_reset_hw()
10154 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10158 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1) in tg3_reset_hw()
10161 tg3_setup_rxbd_thresholds(tp); in tg3_reset_hw()
10184 if (!tg3_flag(tp, 5717_PLUS)) in tg3_reset_hw()
10189 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10196 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10197 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { in tg3_reset_hw()
10199 if (tg3_flag(tp, JUMBO_RING_ENABLE)) { in tg3_reset_hw()
10204 val = TG3_RX_JMB_RING_SIZE(tp) << in tg3_reset_hw()
10208 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || in tg3_reset_hw()
10209 tg3_flag(tp, 57765_CLASS) || in tg3_reset_hw()
10210 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10218 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10219 val = TG3_RX_STD_RING_SIZE(tp); in tg3_reset_hw()
10229 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10233 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10236 tg3_rings_reset(tp); in tg3_reset_hw()
10239 __tg3_set_mac_addr(tp, false); in tg3_reset_hw()
10243 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10252 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10253 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10273 if (tg3_asic_rev(tp) == ASIC_REV_5717) in tg3_reset_hw()
10276 if (tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_reset_hw()
10277 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10278 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_reset_hw()
10283 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_reset_hw()
10284 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_reset_hw()
10285 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_reset_hw()
10286 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_reset_hw()
10289 !tg3_flag(tp, IS_5788)) { in tg3_reset_hw()
10294 if (tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
10297 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_reset_hw()
10298 tp->dma_limit = 0; in tg3_reset_hw()
10299 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10301 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10305 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
10306 tg3_flag(tp, HW_TSO_2) || in tg3_reset_hw()
10307 tg3_flag(tp, HW_TSO_3)) in tg3_reset_hw()
10310 if (tg3_flag(tp, 57765_PLUS) || in tg3_reset_hw()
10311 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10312 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_reset_hw()
10315 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10316 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10319 if (tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_reset_hw()
10320 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_reset_hw()
10321 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10322 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_reset_hw()
10323 tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10326 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10332 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10333 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10344 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_reset_hw()
10345 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10346 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10349 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10361 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
10366 tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10387 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10389 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
10395 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10397 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10406 tg3_write_mem(tp, i, 0); in tg3_reset_hw()
10411 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10415 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10418 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10419 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10425 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10428 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
10429 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10430 if (!tg3_flag(tp, 5705_PLUS) && in tg3_reset_hw()
10431 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10432 tg3_asic_rev(tp) != ASIC_REV_5700) in tg3_reset_hw()
10433 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10434 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10443 if (!tg3_flag(tp, IS_NIC)) { in tg3_reset_hw()
10450 if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_reset_hw()
10454 if (tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_reset_hw()
10457 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10458 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10461 if (tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_reset_hw()
10462 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10465 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10468 if (tg3_flag(tp, USING_MSIX)) { in tg3_reset_hw()
10471 if (tp->irq_cnt > 1) in tg3_reset_hw()
10473 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_reset_hw()
10478 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
10489 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_reset_hw()
10490 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_reset_hw()
10491 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_reset_hw()
10492 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 || in tg3_reset_hw()
10493 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) { in tg3_reset_hw()
10496 !tg3_flag(tp, IS_5788)) { in tg3_reset_hw()
10502 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
10505 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_reset_hw()
10511 if (tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
10514 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10516 if (tg3_asic_rev(tp) == ASIC_REV_5703) { in tg3_reset_hw()
10519 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_reset_hw()
10523 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10530 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_reset_hw()
10531 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_reset_hw()
10533 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) in tg3_reset_hw()
10538 val |= tg3_lso_rd_dma_workaround_bit(tp); in tg3_reset_hw()
10540 tg3_flag_set(tp, 5719_5720_RDMA_BUG); in tg3_reset_hw()
10545 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10548 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_reset_hw()
10557 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_reset_hw()
10561 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
10562 tg3_flag(tp, HW_TSO_2) || in tg3_reset_hw()
10563 tg3_flag(tp, HW_TSO_3)) in tg3_reset_hw()
10566 if (tg3_flag(tp, ENABLE_TSS)) in tg3_reset_hw()
10571 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { in tg3_reset_hw()
10572 err = tg3_load_5701_a0_firmware_fix(tp); in tg3_reset_hw()
10577 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_reset_hw()
10581 tg3_load_57766_firmware(tp); in tg3_reset_hw()
10584 if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10585 err = tg3_load_tso_firmware(tp); in tg3_reset_hw()
10590 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10592 if (tg3_flag(tp, 5755_PLUS) || in tg3_reset_hw()
10593 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_reset_hw()
10594 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10596 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10597 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10599 tp->tx_mode &= ~val; in tg3_reset_hw()
10600 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10603 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10606 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_reset_hw()
10609 tg3_rss_write_indir_tbl(tp); in tg3_reset_hw()
10617 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10618 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
10619 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10621 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10622 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10624 if (tg3_flag(tp, ENABLE_RSS)) in tg3_reset_hw()
10625 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10632 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10635 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10638 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10642 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10645 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10646 if ((tg3_asic_rev(tp) == ASIC_REV_5704) && in tg3_reset_hw()
10647 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10655 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) in tg3_reset_hw()
10662 if (tg3_flag(tp, 57765_CLASS)) in tg3_reset_hw()
10668 if (tg3_asic_rev(tp) == ASIC_REV_5704 && in tg3_reset_hw()
10669 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10671 tg3_flag_set(tp, HW_AUTONEG); in tg3_reset_hw()
10674 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10675 tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_reset_hw()
10680 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10681 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10682 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10685 if (!tg3_flag(tp, USE_PHYLIB)) { in tg3_reset_hw()
10686 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10687 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10689 err = tg3_setup_phy(tp, false); in tg3_reset_hw()
10693 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10694 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10698 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { in tg3_reset_hw()
10699 tg3_writephy(tp, MII_TG3_TEST1, in tg3_reset_hw()
10701 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); in tg3_reset_hw()
10706 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10714 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) in tg3_reset_hw()
10718 if (tg3_flag(tp, ENABLE_ASF)) in tg3_reset_hw()
10768 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
10770 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, in tg3_reset_hw()
10773 tg3_write_sig_post_reset(tp, RESET_KIND_INIT); in tg3_reset_hw()
10781 static int tg3_init_hw(struct tg3 *tp, bool reset_phy) in tg3_init_hw() argument
10787 tg3_enable_register_access(tp); in tg3_init_hw()
10788 tg3_poll_fw(tp); in tg3_init_hw()
10790 tg3_switch_clocks(tp); in tg3_init_hw()
10794 return tg3_reset_hw(tp, reset_phy); in tg3_init_hw()
10798 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir) in tg3_sd_scan_scratchpad() argument
10804 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len); in tg3_sd_scan_scratchpad()
10817 struct tg3 *tp = dev_get_drvdata(dev); in tg3_show_temp() local
10820 spin_lock_bh(&tp->lock); in tg3_show_temp()
10821 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10823 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10843 static void tg3_hwmon_close(struct tg3 *tp) in tg3_hwmon_close() argument
10845 if (tp->hwmon_dev) { in tg3_hwmon_close()
10846 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10847 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10851 static void tg3_hwmon_open(struct tg3 *tp) in tg3_hwmon_open() argument
10855 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10858 tg3_sd_scan_scratchpad(tp, ocirs); in tg3_hwmon_open()
10871 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10872 tp, tg3_groups); in tg3_hwmon_open()
10873 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10874 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10879 static inline void tg3_hwmon_close(struct tg3 *tp) { } in tg3_hwmon_close() argument
10880 static inline void tg3_hwmon_open(struct tg3 *tp) { } in tg3_hwmon_open() argument
10891 static void tg3_periodic_fetch_stats(struct tg3 *tp) in tg3_periodic_fetch_stats() argument
10893 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10895 if (!tp->link_up) in tg3_periodic_fetch_stats()
10911 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) && in tg3_periodic_fetch_stats()
10917 val &= ~tg3_lso_rd_dma_workaround_bit(tp); in tg3_periodic_fetch_stats()
10919 tg3_flag_clear(tp, 5719_5720_RDMA_BUG); in tg3_periodic_fetch_stats()
10938 if (tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_periodic_fetch_stats()
10939 tg3_asic_rev(tp) != ASIC_REV_5762 && in tg3_periodic_fetch_stats()
10940 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 && in tg3_periodic_fetch_stats()
10941 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) { in tg3_periodic_fetch_stats()
10957 static void tg3_chk_missed_msi(struct tg3 *tp) in tg3_chk_missed_msi() argument
10961 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
10962 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
10982 struct tg3 *tp = from_timer(tp, t, timer); in tg3_timer() local
10984 spin_lock(&tp->lock); in tg3_timer()
10986 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
10987 spin_unlock(&tp->lock); in tg3_timer()
10991 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_timer()
10992 tg3_flag(tp, 57765_CLASS)) in tg3_timer()
10993 tg3_chk_missed_msi(tp); in tg3_timer()
10995 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { in tg3_timer()
11000 if (!tg3_flag(tp, TAGGED_STATUS)) { in tg3_timer()
11005 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
11007 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
11009 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11014 spin_unlock(&tp->lock); in tg3_timer()
11015 tg3_reset_task_schedule(tp); in tg3_timer()
11021 if (!--tp->timer_counter) { in tg3_timer()
11022 if (tg3_flag(tp, 5705_PLUS)) in tg3_timer()
11023 tg3_periodic_fetch_stats(tp); in tg3_timer()
11025 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
11026 tg3_phy_eee_enable(tp); in tg3_timer()
11028 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_timer()
11035 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
11042 tg3_setup_phy(tp, false); in tg3_timer()
11043 } else if (tg3_flag(tp, POLL_SERDES)) { in tg3_timer()
11047 if (tp->link_up && in tg3_timer()
11051 if (!tp->link_up && in tg3_timer()
11057 if (!tp->serdes_counter) { in tg3_timer()
11059 (tp->mac_mode & in tg3_timer()
11062 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11065 tg3_setup_phy(tp, false); in tg3_timer()
11067 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11068 tg3_flag(tp, 5780_CLASS)) { in tg3_timer()
11069 tg3_serdes_parallel_detect(tp); in tg3_timer()
11070 } else if (tg3_flag(tp, POLL_CPMU_LINK)) { in tg3_timer()
11075 if (link_up != tp->link_up) in tg3_timer()
11076 tg3_setup_phy(tp, false); in tg3_timer()
11079 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11099 if (!--tp->asf_counter) { in tg3_timer()
11100 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_timer()
11101 tg3_wait_for_event_ack(tp); in tg3_timer()
11103 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, in tg3_timer()
11105 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); in tg3_timer()
11106 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, in tg3_timer()
11109 tg3_generate_fw_event(tp); in tg3_timer()
11111 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11115 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL); in tg3_timer()
11117 spin_unlock(&tp->lock); in tg3_timer()
11120 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11121 add_timer(&tp->timer); in tg3_timer()
11124 static void tg3_timer_init(struct tg3 *tp) in tg3_timer_init() argument
11126 if (tg3_flag(tp, TAGGED_STATUS) && in tg3_timer_init()
11127 tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_timer_init()
11128 !tg3_flag(tp, 57765_CLASS)) in tg3_timer_init()
11129 tp->timer_offset = HZ; in tg3_timer_init()
11131 tp->timer_offset = HZ / 10; in tg3_timer_init()
11133 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11135 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11136 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11139 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11142 static void tg3_timer_start(struct tg3 *tp) in tg3_timer_start() argument
11144 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11145 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11147 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11148 add_timer(&tp->timer); in tg3_timer_start()
11151 static void tg3_timer_stop(struct tg3 *tp) in tg3_timer_stop() argument
11153 del_timer_sync(&tp->timer); in tg3_timer_stop()
11159 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy) in tg3_restart_hw() argument
11160 __releases(tp->lock) in tg3_restart_hw()
11161 __acquires(tp->lock) in tg3_restart_hw()
11165 err = tg3_init_hw(tp, reset_phy); in tg3_restart_hw()
11167 netdev_err(tp->dev, in tg3_restart_hw()
11169 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_restart_hw()
11170 tg3_full_unlock(tp); in tg3_restart_hw()
11171 tg3_timer_stop(tp); in tg3_restart_hw()
11172 tp->irq_sync = 0; in tg3_restart_hw()
11173 tg3_napi_enable(tp); in tg3_restart_hw()
11174 dev_close(tp->dev); in tg3_restart_hw()
11175 tg3_full_lock(tp, 0); in tg3_restart_hw()
11182 struct tg3 *tp = container_of(work, struct tg3, reset_task); in tg3_reset_task() local
11186 tg3_full_lock(tp, 0); in tg3_reset_task()
11188 if (!netif_running(tp->dev)) { in tg3_reset_task()
11189 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11190 tg3_full_unlock(tp); in tg3_reset_task()
11195 tg3_full_unlock(tp); in tg3_reset_task()
11197 tg3_phy_stop(tp); in tg3_reset_task()
11199 tg3_netif_stop(tp); in tg3_reset_task()
11201 tg3_full_lock(tp, 1); in tg3_reset_task()
11203 if (tg3_flag(tp, TX_RECOVERY_PENDING)) { in tg3_reset_task()
11204 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11205 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11206 tg3_flag_set(tp, MBOX_WRITE_REORDER); in tg3_reset_task()
11207 tg3_flag_clear(tp, TX_RECOVERY_PENDING); in tg3_reset_task()
11210 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_reset_task()
11211 err = tg3_init_hw(tp, true); in tg3_reset_task()
11213 tg3_full_unlock(tp); in tg3_reset_task()
11214 tp->irq_sync = 0; in tg3_reset_task()
11215 tg3_napi_enable(tp); in tg3_reset_task()
11219 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11220 dev_close(tp->dev); in tg3_reset_task()
11224 tg3_netif_start(tp); in tg3_reset_task()
11226 tg3_full_unlock(tp); in tg3_reset_task()
11229 tg3_phy_start(tp); in tg3_reset_task()
11231 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11236 static int tg3_request_irq(struct tg3 *tp, int irq_num) in tg3_request_irq() argument
11241 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11243 if (tp->irq_cnt == 1) in tg3_request_irq()
11244 name = tp->dev->name; in tg3_request_irq()
11249 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11252 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11255 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11258 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11262 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_request_irq()
11264 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_request_irq()
11269 if (tg3_flag(tp, TAGGED_STATUS)) in tg3_request_irq()
11277 static int tg3_test_interrupt(struct tg3 *tp) in tg3_test_interrupt() argument
11279 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11280 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11287 tg3_disable_ints(tp); in tg3_test_interrupt()
11295 if (tg3_flag(tp, 57765_PLUS)) { in tg3_test_interrupt()
11306 tg3_enable_ints(tp); in tg3_test_interrupt()
11308 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11323 if (tg3_flag(tp, 57765_PLUS) && in tg3_test_interrupt()
11330 tg3_disable_ints(tp); in tg3_test_interrupt()
11334 err = tg3_request_irq(tp, 0); in tg3_test_interrupt()
11341 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { in tg3_test_interrupt()
11354 static int tg3_test_msi(struct tg3 *tp) in tg3_test_msi() argument
11359 if (!tg3_flag(tp, USING_MSI)) in tg3_test_msi()
11365 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11366 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11369 err = tg3_test_interrupt(tp); in tg3_test_msi()
11371 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11381 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11385 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11387 pci_disable_msi(tp->pdev); in tg3_test_msi()
11389 tg3_flag_clear(tp, USING_MSI); in tg3_test_msi()
11390 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11392 err = tg3_request_irq(tp, 0); in tg3_test_msi()
11399 tg3_full_lock(tp, 1); in tg3_test_msi()
11401 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_test_msi()
11402 err = tg3_init_hw(tp, true); in tg3_test_msi()
11404 tg3_full_unlock(tp); in tg3_test_msi()
11407 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11412 static int tg3_request_firmware(struct tg3 *tp) in tg3_request_firmware() argument
11416 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11417 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11418 tp->fw_needed); in tg3_request_firmware()
11422 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11429 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11430 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11431 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11432 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11433 release_firmware(tp->fw); in tg3_request_firmware()
11434 tp->fw = NULL; in tg3_request_firmware()
11439 tp->fw_needed = NULL; in tg3_request_firmware()
11443 static u32 tg3_irq_count(struct tg3 *tp) in tg3_irq_count() argument
11445 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11453 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11459 static bool tg3_enable_msix(struct tg3 *tp) in tg3_enable_msix() argument
11464 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11465 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11466 if (!tp->rxq_cnt) in tg3_enable_msix()
11467 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11468 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11469 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11475 if (!tp->txq_req) in tg3_enable_msix()
11476 tp->txq_cnt = 1; in tg3_enable_msix()
11478 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11480 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11485 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11488 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11489 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11490 tp->irq_cnt, rc); in tg3_enable_msix()
11491 tp->irq_cnt = rc; in tg3_enable_msix()
11492 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11493 if (tp->txq_cnt) in tg3_enable_msix()
11494 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11497 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11498 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11500 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11501 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11505 if (tp->irq_cnt == 1) in tg3_enable_msix()
11508 tg3_flag_set(tp, ENABLE_RSS); in tg3_enable_msix()
11510 if (tp->txq_cnt > 1) in tg3_enable_msix()
11511 tg3_flag_set(tp, ENABLE_TSS); in tg3_enable_msix()
11513 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11518 static void tg3_ints_init(struct tg3 *tp) in tg3_ints_init() argument
11520 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && in tg3_ints_init()
11521 !tg3_flag(tp, TAGGED_STATUS)) { in tg3_ints_init()
11525 netdev_warn(tp->dev, in tg3_ints_init()
11530 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) in tg3_ints_init()
11531 tg3_flag_set(tp, USING_MSIX); in tg3_ints_init()
11532 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11533 tg3_flag_set(tp, USING_MSI); in tg3_ints_init()
11535 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
11537 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11539 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_ints_init()
11544 if (!tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
11545 tp->irq_cnt = 1; in tg3_ints_init()
11546 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11549 if (tp->irq_cnt == 1) { in tg3_ints_init()
11550 tp->txq_cnt = 1; in tg3_ints_init()
11551 tp->rxq_cnt = 1; in tg3_ints_init()
11552 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11553 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11557 static void tg3_ints_fini(struct tg3 *tp) in tg3_ints_fini() argument
11559 if (tg3_flag(tp, USING_MSIX)) in tg3_ints_fini()
11560 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11561 else if (tg3_flag(tp, USING_MSI)) in tg3_ints_fini()
11562 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11563 tg3_flag_clear(tp, USING_MSI); in tg3_ints_fini()
11564 tg3_flag_clear(tp, USING_MSIX); in tg3_ints_fini()
11565 tg3_flag_clear(tp, ENABLE_RSS); in tg3_ints_fini()
11566 tg3_flag_clear(tp, ENABLE_TSS); in tg3_ints_fini()
11569 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq, in tg3_start() argument
11572 struct net_device *dev = tp->dev; in tg3_start()
11579 tg3_ints_init(tp); in tg3_start()
11581 tg3_rss_check_indir_tbl(tp); in tg3_start()
11586 err = tg3_alloc_consistent(tp); in tg3_start()
11590 tg3_napi_init(tp); in tg3_start()
11592 tg3_napi_enable(tp); in tg3_start()
11594 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11595 err = tg3_request_irq(tp, i); in tg3_start()
11598 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11606 tg3_full_lock(tp, 0); in tg3_start()
11609 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_start()
11611 err = tg3_init_hw(tp, reset_phy); in tg3_start()
11613 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_start()
11614 tg3_free_rings(tp); in tg3_start()
11617 tg3_full_unlock(tp); in tg3_start()
11622 if (test_irq && tg3_flag(tp, USING_MSI)) { in tg3_start()
11623 err = tg3_test_msi(tp); in tg3_start()
11626 tg3_full_lock(tp, 0); in tg3_start()
11627 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_start()
11628 tg3_free_rings(tp); in tg3_start()
11629 tg3_full_unlock(tp); in tg3_start()
11634 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { in tg3_start()
11642 tg3_phy_start(tp); in tg3_start()
11644 tg3_hwmon_open(tp); in tg3_start()
11646 tg3_full_lock(tp, 0); in tg3_start()
11648 tg3_timer_start(tp); in tg3_start()
11649 tg3_flag_set(tp, INIT_COMPLETE); in tg3_start()
11650 tg3_enable_ints(tp); in tg3_start()
11652 tg3_ptp_resume(tp); in tg3_start()
11654 tg3_full_unlock(tp); in tg3_start()
11668 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11669 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11674 tg3_napi_disable(tp); in tg3_start()
11675 tg3_napi_fini(tp); in tg3_start()
11676 tg3_free_consistent(tp); in tg3_start()
11679 tg3_ints_fini(tp); in tg3_start()
11684 static void tg3_stop(struct tg3 *tp) in tg3_stop() argument
11688 tg3_reset_task_cancel(tp); in tg3_stop()
11689 tg3_netif_stop(tp); in tg3_stop()
11691 tg3_timer_stop(tp); in tg3_stop()
11693 tg3_hwmon_close(tp); in tg3_stop()
11695 tg3_phy_stop(tp); in tg3_stop()
11697 tg3_full_lock(tp, 1); in tg3_stop()
11699 tg3_disable_ints(tp); in tg3_stop()
11701 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_stop()
11702 tg3_free_rings(tp); in tg3_stop()
11703 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_stop()
11705 tg3_full_unlock(tp); in tg3_stop()
11707 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11708 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11712 tg3_ints_fini(tp); in tg3_stop()
11714 tg3_napi_fini(tp); in tg3_stop()
11716 tg3_free_consistent(tp); in tg3_stop()
11721 struct tg3 *tp = netdev_priv(dev); in tg3_open() local
11724 if (tp->pcierr_recovery) { in tg3_open()
11730 if (tp->fw_needed) { in tg3_open()
11731 err = tg3_request_firmware(tp); in tg3_open()
11732 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_open()
11734 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11735 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11736 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11737 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11738 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11740 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { in tg3_open()
11744 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11745 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_open()
11746 } else if (!tg3_flag(tp, TSO_CAPABLE)) { in tg3_open()
11747 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11748 tg3_flag_set(tp, TSO_CAPABLE); in tg3_open()
11752 tg3_carrier_off(tp); in tg3_open()
11754 err = tg3_power_up(tp); in tg3_open()
11758 tg3_full_lock(tp, 0); in tg3_open()
11760 tg3_disable_ints(tp); in tg3_open()
11761 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_open()
11763 tg3_full_unlock(tp); in tg3_open()
11765 err = tg3_start(tp, in tg3_open()
11766 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11769 tg3_frob_aux_power(tp, false); in tg3_open()
11770 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11778 struct tg3 *tp = netdev_priv(dev); in tg3_close() local
11780 if (tp->pcierr_recovery) { in tg3_close()
11786 tg3_stop(tp); in tg3_close()
11788 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11789 tg3_power_down_prepare(tp); in tg3_close()
11791 tg3_carrier_off(tp); in tg3_close()
11801 static u64 tg3_calc_crc_errors(struct tg3 *tp) in tg3_calc_crc_errors() argument
11803 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11805 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11806 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_calc_crc_errors()
11807 tg3_asic_rev(tp) == ASIC_REV_5701)) { in tg3_calc_crc_errors()
11810 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { in tg3_calc_crc_errors()
11811 tg3_writephy(tp, MII_TG3_TEST1, in tg3_calc_crc_errors()
11813 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); in tg3_calc_crc_errors()
11817 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11819 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11829 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats) in tg3_get_estats() argument
11831 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11832 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
11913 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats) in tg3_get_nstats() argument
11915 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
11916 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
11958 tg3_calc_crc_errors(tp); in tg3_get_nstats()
11963 stats->rx_dropped = tp->rx_dropped; in tg3_get_nstats()
11964 stats->tx_dropped = tp->tx_dropped; in tg3_get_nstats()
11975 struct tg3 *tp = netdev_priv(dev); in tg3_get_regs() local
11981 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
11984 tg3_full_lock(tp, 0); in tg3_get_regs()
11986 tg3_dump_legacy_regs(tp, (u32 *)_p); in tg3_get_regs()
11988 tg3_full_unlock(tp); in tg3_get_regs()
11993 struct tg3 *tp = netdev_priv(dev); in tg3_get_eeprom_len() local
11995 return tp->nvram_size; in tg3_get_eeprom_len()
12000 struct tg3 *tp = netdev_priv(dev); in tg3_get_eeprom() local
12006 if (tg3_flag(tp, NO_NVRAM)) in tg3_get_eeprom()
12016 if (tg3_flag(tp, CPMU_PRESENT)) { in tg3_get_eeprom()
12026 tg3_override_clk(tp); in tg3_get_eeprom()
12036 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
12048 ret = tg3_nvram_read_be32(tp, offset + i, &val); in tg3_get_eeprom()
12072 ret = tg3_nvram_read_be32(tp, b_offset, &val); in tg3_get_eeprom()
12082 tg3_restore_clk(tp); in tg3_get_eeprom()
12091 struct tg3 *tp = netdev_priv(dev); in tg3_set_eeprom() local
12097 if (tg3_flag(tp, NO_NVRAM) || in tg3_set_eeprom()
12106 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12120 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12137 ret = tg3_nvram_write_block(tp, offset, len, buf); in tg3_set_eeprom()
12148 struct tg3 *tp = netdev_priv(dev); in tg3_get_link_ksettings() local
12151 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_get_link_ksettings()
12153 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_link_ksettings()
12155 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_get_link_ksettings()
12163 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_link_ksettings()
12167 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12181 advertising = tp->link_config.advertising; in tg3_get_link_ksettings()
12182 if (tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_get_link_ksettings()
12183 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_link_ksettings()
12184 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12190 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12197 if (netif_running(dev) && tp->link_up) { in tg3_get_link_ksettings()
12198 cmd->base.speed = tp->link_config.active_speed; in tg3_get_link_ksettings()
12199 cmd->base.duplex = tp->link_config.active_duplex; in tg3_get_link_ksettings()
12202 tp->link_config.rmt_adv); in tg3_get_link_ksettings()
12204 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12205 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_link_ksettings()
12215 cmd->base.phy_address = tp->phy_addr; in tg3_get_link_ksettings()
12216 cmd->base.autoneg = tp->link_config.autoneg; in tg3_get_link_ksettings()
12223 struct tg3 *tp = netdev_priv(dev); in tg3_set_link_ksettings() local
12227 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_link_ksettings()
12229 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_link_ksettings()
12231 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_link_ksettings()
12252 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_link_ksettings()
12256 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_link_ksettings()
12277 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_link_ksettings()
12290 tg3_full_lock(tp, 0); in tg3_set_link_ksettings()
12292 tp->link_config.autoneg = cmd->base.autoneg; in tg3_set_link_ksettings()
12294 tp->link_config.advertising = (advertising | in tg3_set_link_ksettings()
12296 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_link_ksettings()
12297 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_link_ksettings()
12299 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12300 tp->link_config.speed = speed; in tg3_set_link_ksettings()
12301 tp->link_config.duplex = cmd->base.duplex; in tg3_set_link_ksettings()
12304 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_link_ksettings()
12306 tg3_warn_mgmt_link_flap(tp); in tg3_set_link_ksettings()
12309 tg3_setup_phy(tp, true); in tg3_set_link_ksettings()
12311 tg3_full_unlock(tp); in tg3_set_link_ksettings()
12318 struct tg3 *tp = netdev_priv(dev); in tg3_get_drvinfo() local
12321 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12322 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12327 struct tg3 *tp = netdev_priv(dev); in tg3_get_wol() local
12329 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12334 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12341 struct tg3 *tp = netdev_priv(dev); in tg3_set_wol() local
12342 struct device *dp = &tp->pdev->dev; in tg3_set_wol()
12347 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) in tg3_set_wol()
12353 tg3_flag_set(tp, WOL_ENABLE); in tg3_set_wol()
12355 tg3_flag_clear(tp, WOL_ENABLE); in tg3_set_wol()
12362 struct tg3 *tp = netdev_priv(dev); in tg3_get_msglevel() local
12363 return tp->msg_enable; in tg3_get_msglevel()
12368 struct tg3 *tp = netdev_priv(dev); in tg3_set_msglevel() local
12369 tp->msg_enable = value; in tg3_set_msglevel()
12374 struct tg3 *tp = netdev_priv(dev); in tg3_nway_reset() local
12380 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12383 tg3_warn_mgmt_link_flap(tp); in tg3_nway_reset()
12385 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_nway_reset()
12386 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12388 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_nway_reset()
12392 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12394 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_nway_reset()
12395 if (!tg3_readphy(tp, MII_BMCR, &bmcr) && in tg3_nway_reset()
12397 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12398 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | in tg3_nway_reset()
12402 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12410 struct tg3 *tp = netdev_priv(dev); in tg3_get_ringparam() local
12412 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12413 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
12414 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12420 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12421 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
12422 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12426 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12431 struct tg3 *tp = netdev_priv(dev); in tg3_set_ringparam() local
12435 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12436 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12439 (tg3_flag(tp, TSO_BUG) && in tg3_set_ringparam()
12444 tg3_phy_stop(tp); in tg3_set_ringparam()
12445 tg3_netif_stop(tp); in tg3_set_ringparam()
12449 tg3_full_lock(tp, irq_sync); in tg3_set_ringparam()
12451 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12453 if (tg3_flag(tp, MAX_RXPEND_64) && in tg3_set_ringparam()
12454 tp->rx_pending > 63) in tg3_set_ringparam()
12455 tp->rx_pending = 63; in tg3_set_ringparam()
12457 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_set_ringparam()
12458 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12460 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12461 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12464 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_set_ringparam()
12466 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_ringparam()
12467 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_set_ringparam()
12468 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_set_ringparam()
12471 err = tg3_restart_hw(tp, reset_phy); in tg3_set_ringparam()
12473 tg3_netif_start(tp); in tg3_set_ringparam()
12476 tg3_full_unlock(tp); in tg3_set_ringparam()
12479 tg3_phy_start(tp); in tg3_set_ringparam()
12486 struct tg3 *tp = netdev_priv(dev); in tg3_get_pauseparam() local
12488 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12490 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12495 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12503 struct tg3 *tp = netdev_priv(dev); in tg3_set_pauseparam() local
12507 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12508 tg3_warn_mgmt_link_flap(tp); in tg3_set_pauseparam()
12510 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_pauseparam()
12513 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_pauseparam()
12518 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12521 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12524 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12527 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12531 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12533 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12535 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12548 tg3_setup_flow_control(tp, 0, 0); in tg3_set_pauseparam()
12554 tg3_netif_stop(tp); in tg3_set_pauseparam()
12558 tg3_full_lock(tp, irq_sync); in tg3_set_pauseparam()
12561 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12563 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12565 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12567 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12569 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12571 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12574 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_set_pauseparam()
12576 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_pauseparam()
12577 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_set_pauseparam()
12578 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_set_pauseparam()
12581 err = tg3_restart_hw(tp, reset_phy); in tg3_set_pauseparam()
12583 tg3_netif_start(tp); in tg3_set_pauseparam()
12586 tg3_full_unlock(tp); in tg3_set_pauseparam()
12589 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12609 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxnfc() local
12611 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxnfc()
12616 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12617 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12634 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxfh_indir_size() local
12636 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxfh_indir_size()
12644 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxfh() local
12653 indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12661 struct tg3 *tp = netdev_priv(dev); in tg3_set_rxfh() local
12675 tp->rss_ind_tbl[i] = indir[i]; in tg3_set_rxfh()
12677 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS)) in tg3_set_rxfh()
12683 tg3_full_lock(tp, 0); in tg3_set_rxfh()
12684 tg3_rss_write_indir_tbl(tp); in tg3_set_rxfh()
12685 tg3_full_unlock(tp); in tg3_set_rxfh()
12693 struct tg3 *tp = netdev_priv(dev); in tg3_get_channels() local
12696 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12697 channel->max_tx = tp->txq_max; in tg3_get_channels()
12700 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12701 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12703 if (tp->rxq_req) in tg3_get_channels()
12704 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12706 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12708 if (tp->txq_req) in tg3_get_channels()
12709 channel->tx_count = tp->txq_req; in tg3_get_channels()
12711 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12718 struct tg3 *tp = netdev_priv(dev); in tg3_set_channels() local
12720 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_set_channels()
12723 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12724 channel->tx_count > tp->txq_max) in tg3_set_channels()
12727 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12728 tp->txq_req = channel->tx_count; in tg3_set_channels()
12733 tg3_stop(tp); in tg3_set_channels()
12735 tg3_carrier_off(tp); in tg3_set_channels()
12737 tg3_start(tp, true, false, false); in tg3_set_channels()
12760 struct tg3 *tp = netdev_priv(dev); in tg3_set_phys_id() local
12782 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12792 struct tg3 *tp = netdev_priv(dev); in tg3_get_ethtool_stats() local
12794 if (tp->hw_stats) in tg3_get_ethtool_stats()
12795 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats); in tg3_get_ethtool_stats()
12800 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen) in tg3_vpd_readblock() argument
12807 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) in tg3_vpd_readblock()
12814 if (tg3_nvram_read(tp, offset, &val)) in tg3_vpd_readblock()
12824 if (tg3_nvram_read(tp, offset + 4, &offset)) in tg3_vpd_readblock()
12827 offset = tg3_nvram_logical_addr(tp, offset); in tg3_vpd_readblock()
12846 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) in tg3_vpd_readblock()
12856 cnt = pci_read_vpd(tp->pdev, pos, in tg3_vpd_readblock()
12886 static int tg3_test_nvram(struct tg3 *tp) in tg3_test_nvram() argument
12892 if (tg3_flag(tp, NO_NVRAM)) in tg3_test_nvram()
12895 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_test_nvram()
12938 err = tg3_nvram_read_be32(tp, i, &buf[j]); in tg3_test_nvram()
13029 buf = tg3_vpd_readblock(tp, &len); in tg3_test_nvram()
13068 static int tg3_test_link(struct tg3 *tp) in tg3_test_link() argument
13072 if (!netif_running(tp->dev)) in tg3_test_link()
13075 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13081 if (tp->link_up) in tg3_test_link()
13092 static int tg3_test_registers(struct tg3 *tp) in tg3_test_registers() argument
13242 if (tg3_flag(tp, 5705_PLUS)) { in tg3_test_registers()
13244 if (tg3_flag(tp, 5750_PLUS)) in tg3_test_registers()
13255 if (tg3_flag(tp, IS_5788) && in tg3_test_registers()
13305 if (netif_msg_hw(tp)) in tg3_test_registers()
13306 netdev_err(tp->dev, in tg3_test_registers()
13312 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) in tg3_do_mem_test() argument
13322 tg3_write_mem(tp, offset + j, test_pattern[i]); in tg3_do_mem_test()
13323 tg3_read_mem(tp, offset + j, &val); in tg3_do_mem_test()
13331 static int tg3_test_memory(struct tg3 *tp) in tg3_test_memory() argument
13378 if (tg3_flag(tp, 5717_PLUS)) in tg3_test_memory()
13380 else if (tg3_flag(tp, 57765_CLASS) || in tg3_test_memory()
13381 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_test_memory()
13383 else if (tg3_flag(tp, 5755_PLUS)) in tg3_test_memory()
13385 else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_test_memory()
13387 else if (tg3_flag(tp, 5705_PLUS)) in tg3_test_memory()
13393 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); in tg3_test_memory()
13424 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) in tg3_run_loopback() argument
13435 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13437 tnapi = &tp->napi[0]; in tg3_run_loopback()
13438 rnapi = &tp->napi[0]; in tg3_run_loopback()
13439 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13440 if (tg3_flag(tp, ENABLE_RSS)) in tg3_run_loopback()
13441 rnapi = &tp->napi[1]; in tg3_run_loopback()
13442 if (tg3_flag(tp, ENABLE_TSS)) in tg3_run_loopback()
13443 tnapi = &tp->napi[1]; in tg3_run_loopback()
13450 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13455 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13479 if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
13480 tg3_flag(tp, HW_TSO_2) || in tg3_run_loopback()
13481 tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
13489 if (tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
13494 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_run_loopback()
13496 else if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
13497 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_run_loopback()
13508 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in tg3_run_loopback()
13516 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE); in tg3_run_loopback()
13517 if (pci_dma_mapping_error(tp->pdev, map)) { in tg3_run_loopback()
13526 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13553 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13615 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, in tg3_run_loopback()
13618 rx_data += TG3_RX_OFFSET(tp); in tg3_run_loopback()
13640 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) in tg3_test_loopback() argument
13646 if (tp->dma_limit) in tg3_test_loopback()
13647 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13649 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13650 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13652 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13660 err = tg3_reset_hw(tp, true); in tg3_test_loopback()
13669 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_test_loopback()
13683 if (tg3_asic_rev(tp) != ASIC_REV_5780 && in tg3_test_loopback()
13684 !tg3_flag(tp, CPMU_PRESENT)) { in tg3_test_loopback()
13685 tg3_mac_loopback(tp, true); in tg3_test_loopback()
13687 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13690 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13691 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13694 tg3_mac_loopback(tp, false); in tg3_test_loopback()
13697 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13698 !tg3_flag(tp, USE_PHYLIB)) { in tg3_test_loopback()
13701 tg3_phy_lpbk_set(tp, 0, false); in tg3_test_loopback()
13710 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13712 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
13713 tg3_run_loopback(tp, ETH_FRAME_LEN, true)) in tg3_test_loopback()
13715 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13716 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13720 tg3_phy_lpbk_set(tp, 0, true); in tg3_test_loopback()
13728 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13731 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
13732 tg3_run_loopback(tp, ETH_FRAME_LEN, true)) in tg3_test_loopback()
13735 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13736 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13742 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13743 tg3_phy_toggle_apd(tp, true); in tg3_test_loopback()
13750 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13758 struct tg3 *tp = netdev_priv(dev); in tg3_self_test() local
13761 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13762 if (tg3_power_up(tp)) { in tg3_self_test()
13767 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_self_test()
13772 if (tg3_test_nvram(tp) != 0) { in tg3_self_test()
13776 if (!doextlpbk && tg3_test_link(tp)) { in tg3_self_test()
13784 tg3_phy_stop(tp); in tg3_self_test()
13785 tg3_netif_stop(tp); in tg3_self_test()
13789 tg3_full_lock(tp, irq_sync); in tg3_self_test()
13790 tg3_halt(tp, RESET_KIND_SUSPEND, 1); in tg3_self_test()
13791 err = tg3_nvram_lock(tp); in tg3_self_test()
13792 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_self_test()
13793 if (!tg3_flag(tp, 5705_PLUS)) in tg3_self_test()
13794 tg3_halt_cpu(tp, TX_CPU_BASE); in tg3_self_test()
13796 tg3_nvram_unlock(tp); in tg3_self_test()
13798 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13799 tg3_phy_reset(tp); in tg3_self_test()
13801 if (tg3_test_registers(tp) != 0) { in tg3_self_test()
13806 if (tg3_test_memory(tp) != 0) { in tg3_self_test()
13814 if (tg3_test_loopback(tp, data, doextlpbk)) in tg3_self_test()
13817 tg3_full_unlock(tp); in tg3_self_test()
13819 if (tg3_test_interrupt(tp) != 0) { in tg3_self_test()
13824 tg3_full_lock(tp, 0); in tg3_self_test()
13826 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_self_test()
13828 tg3_flag_set(tp, INIT_COMPLETE); in tg3_self_test()
13829 err2 = tg3_restart_hw(tp, true); in tg3_self_test()
13831 tg3_netif_start(tp); in tg3_self_test()
13834 tg3_full_unlock(tp); in tg3_self_test()
13837 tg3_phy_start(tp); in tg3_self_test()
13839 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13840 tg3_power_down_prepare(tp); in tg3_self_test()
13846 struct tg3 *tp = netdev_priv(dev); in tg3_hwtstamp_set() local
13849 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_hwtstamp_set()
13864 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13867 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13871 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13875 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13879 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13883 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13887 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13891 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13895 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13899 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13903 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13907 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13911 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13918 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
13920 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
13923 tg3_flag_set(tp, TX_TSTAMP_EN); in tg3_hwtstamp_set()
13925 tg3_flag_clear(tp, TX_TSTAMP_EN); in tg3_hwtstamp_set()
13933 struct tg3 *tp = netdev_priv(dev); in tg3_hwtstamp_get() local
13936 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_hwtstamp_get()
13940 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ? in tg3_hwtstamp_get()
13943 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
13995 struct tg3 *tp = netdev_priv(dev); in tg3_ioctl() local
13998 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_ioctl()
14000 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
14002 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_ioctl()
14008 data->phy_id = tp->phy_addr; in tg3_ioctl()
14014 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14020 spin_lock_bh(&tp->lock); in tg3_ioctl()
14021 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14023 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14031 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14037 spin_lock_bh(&tp->lock); in tg3_ioctl()
14038 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14040 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14059 struct tg3 *tp = netdev_priv(dev); in tg3_get_coalesce() local
14061 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14067 struct tg3 *tp = netdev_priv(dev); in tg3_set_coalesce() local
14071 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_set_coalesce()
14093 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14094 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14095 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14096 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14097 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14098 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14099 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14100 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14101 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14104 tg3_full_lock(tp, 0); in tg3_set_coalesce()
14105 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14106 tg3_full_unlock(tp); in tg3_set_coalesce()
14113 struct tg3 *tp = netdev_priv(dev); in tg3_set_eee() local
14115 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14116 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14120 if (edata->advertised != tp->eee.advertised) { in tg3_set_eee()
14121 netdev_warn(tp->dev, in tg3_set_eee()
14127 netdev_warn(tp->dev, in tg3_set_eee()
14133 tp->eee = *edata; in tg3_set_eee()
14135 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14136 tg3_warn_mgmt_link_flap(tp); in tg3_set_eee()
14138 if (netif_running(tp->dev)) { in tg3_set_eee()
14139 tg3_full_lock(tp, 0); in tg3_set_eee()
14140 tg3_setup_eee(tp); in tg3_set_eee()
14141 tg3_phy_reset(tp); in tg3_set_eee()
14142 tg3_full_unlock(tp); in tg3_set_eee()
14150 struct tg3 *tp = netdev_priv(dev); in tg3_get_eee() local
14152 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14153 netdev_warn(tp->dev, in tg3_get_eee()
14158 *edata = tp->eee; in tg3_get_eee()
14207 struct tg3 *tp = netdev_priv(dev); in tg3_get_stats64() local
14209 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14210 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) { in tg3_get_stats64()
14211 *stats = tp->net_stats_prev; in tg3_get_stats64()
14212 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14216 tg3_get_nstats(tp, stats); in tg3_get_stats64()
14217 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14222 struct tg3 *tp = netdev_priv(dev); in tg3_set_rx_mode() local
14227 tg3_full_lock(tp, 0); in tg3_set_rx_mode()
14229 tg3_full_unlock(tp); in tg3_set_rx_mode()
14232 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, in tg3_set_mtu() argument
14238 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
14240 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_set_mtu()
14242 tg3_flag_set(tp, JUMBO_RING_ENABLE); in tg3_set_mtu()
14245 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
14246 tg3_flag_set(tp, TSO_CAPABLE); in tg3_set_mtu()
14249 tg3_flag_clear(tp, JUMBO_RING_ENABLE); in tg3_set_mtu()
14255 struct tg3 *tp = netdev_priv(dev); in tg3_change_mtu() local
14263 tg3_set_mtu(dev, tp, new_mtu); in tg3_change_mtu()
14267 tg3_phy_stop(tp); in tg3_change_mtu()
14269 tg3_netif_stop(tp); in tg3_change_mtu()
14271 tg3_set_mtu(dev, tp, new_mtu); in tg3_change_mtu()
14273 tg3_full_lock(tp, 1); in tg3_change_mtu()
14275 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_change_mtu()
14280 if (tg3_asic_rev(tp) == ASIC_REV_57766 || in tg3_change_mtu()
14281 tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_change_mtu()
14282 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_change_mtu()
14283 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_change_mtu()
14286 err = tg3_restart_hw(tp, reset_phy); in tg3_change_mtu()
14289 tg3_netif_start(tp); in tg3_change_mtu()
14291 tg3_full_unlock(tp); in tg3_change_mtu()
14294 tg3_phy_start(tp); in tg3_change_mtu()
14317 static void tg3_get_eeprom_size(struct tg3 *tp) in tg3_get_eeprom_size() argument
14321 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14323 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_get_eeprom_size()
14338 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14339 if (tg3_nvram_read(tp, cursize, &val) != 0) in tg3_get_eeprom_size()
14348 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14351 static void tg3_get_nvram_size(struct tg3 *tp) in tg3_get_nvram_size() argument
14355 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) in tg3_get_nvram_size()
14360 tg3_get_eeprom_size(tp); in tg3_get_nvram_size()
14364 if (tg3_nvram_read(tp, 0xf0, &val) == 0) { in tg3_get_nvram_size()
14377 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14381 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14384 static void tg3_get_nvram_info(struct tg3 *tp) in tg3_get_nvram_info() argument
14390 tg3_flag_set(tp, FLASH); in tg3_get_nvram_info()
14396 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_get_nvram_info()
14397 tg3_flag(tp, 5780_CLASS)) { in tg3_get_nvram_info()
14400 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14401 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14402 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14405 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14406 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14409 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14410 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14411 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14414 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14415 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14416 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14419 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14420 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14424 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14425 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14429 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14430 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14431 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14435 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) in tg3_nvram_get_pagesize() argument
14439 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14442 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14445 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14448 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14451 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14454 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14457 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14462 static void tg3_get_5752_nvram_info(struct tg3 *tp) in tg3_get_5752_nvram_info() argument
14470 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5752_nvram_info()
14475 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14476 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14479 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14480 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14481 tg3_flag_set(tp, FLASH); in tg3_get_5752_nvram_info()
14486 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14487 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14488 tg3_flag_set(tp, FLASH); in tg3_get_5752_nvram_info()
14492 if (tg3_flag(tp, FLASH)) { in tg3_get_5752_nvram_info()
14493 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5752_nvram_info()
14496 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14503 static void tg3_get_5755_nvram_info(struct tg3 *tp) in tg3_get_5755_nvram_info() argument
14511 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5755_nvram_info()
14521 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14522 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5755_nvram_info()
14523 tg3_flag_set(tp, FLASH); in tg3_get_5755_nvram_info()
14524 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14527 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14530 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14533 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14539 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14540 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5755_nvram_info()
14541 tg3_flag_set(tp, FLASH); in tg3_get_5755_nvram_info()
14542 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14544 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14548 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14552 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14559 static void tg3_get_5787_nvram_info(struct tg3 *tp) in tg3_get_5787_nvram_info() argument
14570 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14571 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14572 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14581 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14582 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14583 tg3_flag_set(tp, FLASH); in tg3_get_5787_nvram_info()
14584 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14589 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14590 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14591 tg3_flag_set(tp, FLASH); in tg3_get_5787_nvram_info()
14592 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14597 static void tg3_get_5761_nvram_info(struct tg3 *tp) in tg3_get_5761_nvram_info() argument
14605 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5761_nvram_info()
14619 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14620 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5761_nvram_info()
14621 tg3_flag_set(tp, FLASH); in tg3_get_5761_nvram_info()
14622 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5761_nvram_info()
14623 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14633 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14634 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5761_nvram_info()
14635 tg3_flag_set(tp, FLASH); in tg3_get_5761_nvram_info()
14636 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14641 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14648 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14654 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14660 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14666 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14672 static void tg3_get_5906_nvram_info(struct tg3 *tp) in tg3_get_5906_nvram_info() argument
14674 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14675 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5906_nvram_info()
14676 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14679 static void tg3_get_57780_nvram_info(struct tg3 *tp) in tg3_get_57780_nvram_info() argument
14688 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14689 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14690 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14702 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14703 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14704 tg3_flag_set(tp, FLASH); in tg3_get_57780_nvram_info()
14710 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14714 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14718 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14725 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14726 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14727 tg3_flag_set(tp, FLASH); in tg3_get_57780_nvram_info()
14731 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14734 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14737 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14742 tg3_flag_set(tp, NO_NVRAM); in tg3_get_57780_nvram_info()
14746 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_57780_nvram_info()
14747 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14748 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_57780_nvram_info()
14752 static void tg3_get_5717_nvram_info(struct tg3 *tp) in tg3_get_5717_nvram_info() argument
14761 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14762 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14763 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14775 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14776 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14777 tg3_flag_set(tp, FLASH); in tg3_get_5717_nvram_info()
14785 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14788 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14802 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14803 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14804 tg3_flag_set(tp, FLASH); in tg3_get_5717_nvram_info()
14813 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14816 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14821 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5717_nvram_info()
14825 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5717_nvram_info()
14826 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14827 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5717_nvram_info()
14830 static void tg3_get_5720_nvram_info(struct tg3 *tp) in tg3_get_5720_nvram_info() argument
14837 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_get_5720_nvram_info()
14839 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14849 tp->nvram_pagesize = 4096; in tg3_get_5720_nvram_info()
14850 tp->nvram_jedecnum = JEDEC_MACRONIX; in tg3_get_5720_nvram_info()
14851 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14852 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5720_nvram_info()
14853 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14855 tp->nvram_size = in tg3_get_5720_nvram_info()
14879 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14880 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14885 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14887 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14901 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14902 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14903 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14909 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14914 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14918 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14921 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_get_5720_nvram_info()
14922 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14944 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
14945 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14946 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14953 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14959 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14965 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14968 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_get_5720_nvram_info()
14969 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14974 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14978 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5720_nvram_info()
14979 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
14980 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5720_nvram_info()
14982 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_get_5720_nvram_info()
14985 if (tg3_nvram_read(tp, 0, &val)) in tg3_get_5720_nvram_info()
14990 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14995 static void tg3_nvram_init(struct tg3 *tp) in tg3_nvram_init() argument
14997 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_nvram_init()
14999 tg3_flag_clear(tp, NVRAM); in tg3_nvram_init()
15000 tg3_flag_clear(tp, NVRAM_BUFFERED); in tg3_nvram_init()
15001 tg3_flag_set(tp, NO_NVRAM); in tg3_nvram_init()
15017 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_nvram_init()
15018 tg3_asic_rev(tp) != ASIC_REV_5701) { in tg3_nvram_init()
15019 tg3_flag_set(tp, NVRAM); in tg3_nvram_init()
15021 if (tg3_nvram_lock(tp)) { in tg3_nvram_init()
15022 netdev_warn(tp->dev, in tg3_nvram_init()
15027 tg3_enable_nvram_access(tp); in tg3_nvram_init()
15029 tp->nvram_size = 0; in tg3_nvram_init()
15031 if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_nvram_init()
15032 tg3_get_5752_nvram_info(tp); in tg3_nvram_init()
15033 else if (tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_nvram_init()
15034 tg3_get_5755_nvram_info(tp); in tg3_nvram_init()
15035 else if (tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_nvram_init()
15036 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_nvram_init()
15037 tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_nvram_init()
15038 tg3_get_5787_nvram_info(tp); in tg3_nvram_init()
15039 else if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_nvram_init()
15040 tg3_get_5761_nvram_info(tp); in tg3_nvram_init()
15041 else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_nvram_init()
15042 tg3_get_5906_nvram_info(tp); in tg3_nvram_init()
15043 else if (tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_nvram_init()
15044 tg3_flag(tp, 57765_CLASS)) in tg3_nvram_init()
15045 tg3_get_57780_nvram_info(tp); in tg3_nvram_init()
15046 else if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_nvram_init()
15047 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_nvram_init()
15048 tg3_get_5717_nvram_info(tp); in tg3_nvram_init()
15049 else if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_nvram_init()
15050 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_nvram_init()
15051 tg3_get_5720_nvram_info(tp); in tg3_nvram_init()
15053 tg3_get_nvram_info(tp); in tg3_nvram_init()
15055 if (tp->nvram_size == 0) in tg3_nvram_init()
15056 tg3_get_nvram_size(tp); in tg3_nvram_init()
15058 tg3_disable_nvram_access(tp); in tg3_nvram_init()
15059 tg3_nvram_unlock(tp); in tg3_nvram_init()
15062 tg3_flag_clear(tp, NVRAM); in tg3_nvram_init()
15063 tg3_flag_clear(tp, NVRAM_BUFFERED); in tg3_nvram_init()
15065 tg3_get_eeprom_size(tp); in tg3_nvram_init()
15138 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp) in tg3_lookup_by_subsys() argument
15144 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15146 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15152 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) in tg3_get_eeprom_hw_cfg() argument
15156 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15157 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15160 tg3_flag_set(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15161 tg3_flag_set(tp, WOL_CAP); in tg3_get_eeprom_hw_cfg()
15163 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_eeprom_hw_cfg()
15165 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15166 tg3_flag_set(tp, IS_NIC); in tg3_get_eeprom_hw_cfg()
15170 tg3_flag_set(tp, ASPM_WORKAROUND); in tg3_get_eeprom_hw_cfg()
15173 tg3_flag_set(tp, WOL_ENABLE); in tg3_get_eeprom_hw_cfg()
15174 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15179 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); in tg3_get_eeprom_hw_cfg()
15186 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); in tg3_get_eeprom_hw_cfg()
15187 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15189 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); in tg3_get_eeprom_hw_cfg()
15191 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_get_eeprom_hw_cfg()
15192 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_get_eeprom_hw_cfg()
15193 tg3_asic_rev(tp) != ASIC_REV_5703 && in tg3_get_eeprom_hw_cfg()
15195 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); in tg3_get_eeprom_hw_cfg()
15197 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_get_eeprom_hw_cfg()
15198 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); in tg3_get_eeprom_hw_cfg()
15200 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_eeprom_hw_cfg()
15201 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_eeprom_hw_cfg()
15202 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_get_eeprom_hw_cfg()
15203 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5); in tg3_get_eeprom_hw_cfg()
15209 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); in tg3_get_eeprom_hw_cfg()
15220 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15222 if (!tg3_flag(tp, 5705_PLUS)) in tg3_get_eeprom_hw_cfg()
15223 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15225 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15228 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15237 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15241 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15245 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15250 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
15251 tg3_asic_rev(tp) == ASIC_REV_5701) in tg3_get_eeprom_hw_cfg()
15252 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15257 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15258 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && in tg3_get_eeprom_hw_cfg()
15259 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1) in tg3_get_eeprom_hw_cfg()
15260 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15263 if (tg3_flag(tp, 5717_PLUS) || in tg3_get_eeprom_hw_cfg()
15264 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_eeprom_hw_cfg()
15265 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15271 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15275 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15276 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) in tg3_get_eeprom_hw_cfg()
15277 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15283 if ((tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
15284 tg3_asic_rev(tp) == ASIC_REV_5701) && in tg3_get_eeprom_hw_cfg()
15285 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15286 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15288 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) in tg3_get_eeprom_hw_cfg()
15289 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15292 tg3_flag_set(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15293 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15295 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15296 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15297 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15299 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15300 tg3_flag_set(tp, IS_NIC); in tg3_get_eeprom_hw_cfg()
15304 tg3_flag_set(tp, ENABLE_ASF); in tg3_get_eeprom_hw_cfg()
15305 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15306 tg3_flag_set(tp, ASF_NEW_HANDSHAKE); in tg3_get_eeprom_hw_cfg()
15310 tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15311 tg3_flag_set(tp, ENABLE_APE); in tg3_get_eeprom_hw_cfg()
15313 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15315 tg3_flag_clear(tp, WOL_CAP); in tg3_get_eeprom_hw_cfg()
15317 if (tg3_flag(tp, WOL_CAP) && in tg3_get_eeprom_hw_cfg()
15319 tg3_flag_set(tp, WOL_ENABLE); in tg3_get_eeprom_hw_cfg()
15320 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15324 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15329 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15331 if ((tg3_flag(tp, 57765_PLUS) || in tg3_get_eeprom_hw_cfg()
15332 (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_get_eeprom_hw_cfg()
15333 tg3_chip_rev(tp) != CHIPREV_5784_AX)) && in tg3_get_eeprom_hw_cfg()
15335 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15337 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_get_eeprom_hw_cfg()
15340 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); in tg3_get_eeprom_hw_cfg()
15341 if (tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_get_eeprom_hw_cfg()
15342 !tg3_flag(tp, 57765_PLUS) && in tg3_get_eeprom_hw_cfg()
15344 tg3_flag_set(tp, ASPM_WORKAROUND); in tg3_get_eeprom_hw_cfg()
15346 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15348 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15352 tg3_flag_set(tp, RGMII_INBAND_DISABLE); in tg3_get_eeprom_hw_cfg()
15354 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); in tg3_get_eeprom_hw_cfg()
15356 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); in tg3_get_eeprom_hw_cfg()
15359 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15362 if (tg3_flag(tp, WOL_CAP)) in tg3_get_eeprom_hw_cfg()
15363 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15364 tg3_flag(tp, WOL_ENABLE)); in tg3_get_eeprom_hw_cfg()
15366 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15369 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val) in tg3_ape_otp_read() argument
15374 err = tg3_nvram_lock(tp); in tg3_ape_otp_read()
15378 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE); in tg3_ape_otp_read()
15379 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN | in tg3_ape_otp_read()
15381 tg3_ape_read32(tp, TG3_APE_OTP_CTRL); in tg3_ape_otp_read()
15385 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS); in tg3_ape_otp_read()
15387 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA); in tg3_ape_otp_read()
15393 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0); in tg3_ape_otp_read()
15395 tg3_nvram_unlock(tp); in tg3_ape_otp_read()
15402 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd) in tg3_issue_otp_command() argument
15425 static u32 tg3_read_otp_phycfg(struct tg3 *tp) in tg3_read_otp_phycfg() argument
15431 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) in tg3_read_otp_phycfg()
15436 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
15443 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
15451 static void tg3_phy_init_link_config(struct tg3 *tp) in tg3_phy_init_link_config() argument
15455 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15456 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15461 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15470 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15471 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15472 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15473 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15474 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15475 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15477 tp->old_link = -1; in tg3_phy_init_link_config()
15480 static int tg3_phy_probe(struct tg3 *tp) in tg3_phy_probe() argument
15487 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_phy_probe()
15488 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15490 if (tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
15491 switch (tp->pci_fn) { in tg3_phy_probe()
15493 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15496 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15499 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15502 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15507 if (!tg3_flag(tp, ENABLE_ASF) && in tg3_phy_probe()
15508 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15509 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15510 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15513 if (tg3_flag(tp, USE_PHYLIB)) in tg3_phy_probe()
15514 return tg3_phy_init(tp); in tg3_phy_probe()
15520 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
15528 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); in tg3_phy_probe()
15529 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); in tg3_phy_probe()
15539 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15541 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15543 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15545 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15555 p = tg3_lookup_by_subsys(tp); in tg3_phy_probe()
15557 tp->phy_id = p->phy_id; in tg3_phy_probe()
15558 } else if (!tg3_flag(tp, IS_SSB_CORE)) { in tg3_phy_probe()
15569 if (!tp->phy_id || in tg3_phy_probe()
15570 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15571 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15575 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15576 (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_phy_probe()
15577 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_phy_probe()
15578 tg3_asic_rev(tp) == ASIC_REV_57766 || in tg3_phy_probe()
15579 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_phy_probe()
15580 (tg3_asic_rev(tp) == ASIC_REV_5717 && in tg3_phy_probe()
15581 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) || in tg3_phy_probe()
15582 (tg3_asic_rev(tp) == ASIC_REV_57765 && in tg3_phy_probe()
15583 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) { in tg3_phy_probe()
15584 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15586 tp->eee.supported = SUPPORTED_100baseT_Full | in tg3_phy_probe()
15588 tp->eee.advertised = ADVERTISED_100baseT_Full | in tg3_phy_probe()
15590 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15591 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15592 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15595 tg3_phy_init_link_config(tp); in tg3_phy_probe()
15597 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15598 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15599 !tg3_flag(tp, ENABLE_APE) && in tg3_phy_probe()
15600 !tg3_flag(tp, ENABLE_ASF)) { in tg3_phy_probe()
15603 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_phy_probe()
15604 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_phy_probe()
15608 err = tg3_phy_reset(tp); in tg3_phy_probe()
15612 tg3_phy_set_wirespeed(tp); in tg3_phy_probe()
15614 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) { in tg3_phy_probe()
15615 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15616 tp->link_config.flowctrl); in tg3_phy_probe()
15618 tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()
15624 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15625 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
15629 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
15635 static void tg3_read_vpd(struct tg3 *tp) in tg3_read_vpd() argument
15642 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); in tg3_read_vpd()
15678 if (len >= sizeof(tp->fw_ver)) in tg3_read_vpd()
15679 len = sizeof(tp->fw_ver) - 1; in tg3_read_vpd()
15680 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15681 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, in tg3_read_vpd()
15698 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15702 if (tp->board_part_number[0]) in tg3_read_vpd()
15706 if (tg3_asic_rev(tp) == ASIC_REV_5717) { in tg3_read_vpd()
15707 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15708 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15709 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15710 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15711 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15714 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_read_vpd()
15715 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15716 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15717 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15718 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15719 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15720 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15721 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15722 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15725 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) { in tg3_read_vpd()
15726 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15727 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15728 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15729 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15730 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15731 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15732 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15733 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15734 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15735 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15736 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15737 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15740 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_read_vpd()
15741 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15742 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15743 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15744 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15745 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15746 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15747 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15748 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15751 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_read_vpd()
15752 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15755 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15759 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) in tg3_fw_img_is_valid() argument
15763 if (tg3_nvram_read(tp, offset, &val) || in tg3_fw_img_is_valid()
15765 tg3_nvram_read(tp, offset + 4, &val) || in tg3_fw_img_is_valid()
15772 static void tg3_read_bc_ver(struct tg3 *tp) in tg3_read_bc_ver() argument
15778 if (tg3_nvram_read(tp, 0xc, &offset) || in tg3_read_bc_ver()
15779 tg3_nvram_read(tp, 0x4, &start)) in tg3_read_bc_ver()
15782 offset = tg3_nvram_logical_addr(tp, offset); in tg3_read_bc_ver()
15784 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_bc_ver()
15788 if (tg3_nvram_read(tp, offset + 4, &val)) in tg3_read_bc_ver()
15795 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15799 tg3_nvram_read(tp, offset + 8, &ver_offset)) in tg3_read_bc_ver()
15805 if (tg3_nvram_read_be32(tp, offset + i, &v)) in tg3_read_bc_ver()
15808 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15813 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) in tg3_read_bc_ver()
15819 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15824 static void tg3_read_hwsb_ver(struct tg3 *tp) in tg3_read_hwsb_ver() argument
15829 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) in tg3_read_hwsb_ver()
15837 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15840 static void tg3_read_sb_ver(struct tg3 *tp, u32 val) in tg3_read_sb_ver() argument
15844 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15872 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_sb_ver()
15884 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15885 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15889 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15891 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15895 static void tg3_read_mgmtfw_ver(struct tg3 *tp) in tg3_read_mgmtfw_ver() argument
15903 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_mgmtfw_ver()
15913 if (!tg3_flag(tp, 5705_PLUS)) in tg3_read_mgmtfw_ver()
15915 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15918 if (tg3_nvram_read(tp, offset + 4, &offset) || in tg3_read_mgmtfw_ver()
15919 !tg3_fw_img_is_valid(tp, offset) || in tg3_read_mgmtfw_ver()
15920 tg3_nvram_read(tp, offset + 8, &val)) in tg3_read_mgmtfw_ver()
15925 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15927 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15928 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
15932 if (tg3_nvram_read_be32(tp, offset, &v)) in tg3_read_mgmtfw_ver()
15938 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
15942 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
15947 static void tg3_probe_ncsi(struct tg3 *tp) in tg3_probe_ncsi() argument
15951 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_probe_ncsi()
15955 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_probe_ncsi()
15959 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) in tg3_probe_ncsi()
15960 tg3_flag_set(tp, APE_HAS_NCSI); in tg3_probe_ncsi()
15963 static void tg3_read_dash_ver(struct tg3 *tp) in tg3_read_dash_ver() argument
15969 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); in tg3_read_dash_ver()
15971 if (tg3_flag(tp, APE_HAS_NCSI)) in tg3_read_dash_ver()
15973 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
15978 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
15980 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
15988 static void tg3_read_otp_ver(struct tg3 *tp) in tg3_read_otp_ver() argument
15992 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_read_otp_ver()
15995 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) && in tg3_read_otp_ver()
15996 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) && in tg3_read_otp_ver()
16008 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
16009 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
16013 static void tg3_read_fw_ver(struct tg3 *tp) in tg3_read_fw_ver() argument
16018 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
16021 if (tg3_flag(tp, NO_NVRAM)) { in tg3_read_fw_ver()
16022 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
16023 tg3_read_otp_ver(tp); in tg3_read_fw_ver()
16027 if (tg3_nvram_read(tp, 0, &val)) in tg3_read_fw_ver()
16031 tg3_read_bc_ver(tp); in tg3_read_fw_ver()
16033 tg3_read_sb_ver(tp, val); in tg3_read_fw_ver()
16035 tg3_read_hwsb_ver(tp); in tg3_read_fw_ver()
16037 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_read_fw_ver()
16038 if (tg3_flag(tp, ENABLE_APE)) { in tg3_read_fw_ver()
16039 tg3_probe_ncsi(tp); in tg3_read_fw_ver()
16041 tg3_read_dash_ver(tp); in tg3_read_fw_ver()
16043 tg3_read_mgmtfw_ver(tp); in tg3_read_fw_ver()
16047 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
16050 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) in tg3_rx_ret_ring_size() argument
16052 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_rx_ret_ring_size()
16054 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) in tg3_rx_ret_ring_size()
16067 static struct pci_dev *tg3_find_peer(struct tg3 *tp) in tg3_find_peer() argument
16070 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16073 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16074 if (peer && peer != tp->pdev) in tg3_find_peer()
16082 peer = tp->pdev; in tg3_find_peer()
16095 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) in tg3_detect_asic_rev() argument
16097 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16098 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) { in tg3_detect_asic_rev()
16104 tg3_flag_set(tp, CPMU_PRESENT); in tg3_detect_asic_rev()
16106 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16107 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16108 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16109 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16110 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16111 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16112 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16113 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16114 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16115 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16116 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16118 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16119 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16120 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16121 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16122 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16123 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16124 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16125 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16126 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16127 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16132 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16138 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW) in tg3_detect_asic_rev()
16139 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16141 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0) in tg3_detect_asic_rev()
16142 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16144 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_detect_asic_rev()
16145 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_detect_asic_rev()
16146 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_detect_asic_rev()
16147 tg3_flag_set(tp, 5717_PLUS); in tg3_detect_asic_rev()
16149 if (tg3_asic_rev(tp) == ASIC_REV_57765 || in tg3_detect_asic_rev()
16150 tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_detect_asic_rev()
16151 tg3_flag_set(tp, 57765_CLASS); in tg3_detect_asic_rev()
16153 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) || in tg3_detect_asic_rev()
16154 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_detect_asic_rev()
16155 tg3_flag_set(tp, 57765_PLUS); in tg3_detect_asic_rev()
16158 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_detect_asic_rev()
16159 tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_detect_asic_rev()
16160 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_detect_asic_rev()
16161 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_detect_asic_rev()
16162 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_detect_asic_rev()
16163 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_detect_asic_rev()
16164 tg3_flag(tp, 57765_PLUS)) in tg3_detect_asic_rev()
16165 tg3_flag_set(tp, 5755_PLUS); in tg3_detect_asic_rev()
16167 if (tg3_asic_rev(tp) == ASIC_REV_5780 || in tg3_detect_asic_rev()
16168 tg3_asic_rev(tp) == ASIC_REV_5714) in tg3_detect_asic_rev()
16169 tg3_flag_set(tp, 5780_CLASS); in tg3_detect_asic_rev()
16171 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_detect_asic_rev()
16172 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_detect_asic_rev()
16173 tg3_asic_rev(tp) == ASIC_REV_5906 || in tg3_detect_asic_rev()
16174 tg3_flag(tp, 5755_PLUS) || in tg3_detect_asic_rev()
16175 tg3_flag(tp, 5780_CLASS)) in tg3_detect_asic_rev()
16176 tg3_flag_set(tp, 5750_PLUS); in tg3_detect_asic_rev()
16178 if (tg3_asic_rev(tp) == ASIC_REV_5705 || in tg3_detect_asic_rev()
16179 tg3_flag(tp, 5750_PLUS)) in tg3_detect_asic_rev()
16180 tg3_flag_set(tp, 5705_PLUS); in tg3_detect_asic_rev()
16183 static bool tg3_10_100_only_device(struct tg3 *tp, in tg3_10_100_only_device() argument
16188 if ((tg3_asic_rev(tp) == ASIC_REV_5703 && in tg3_10_100_only_device()
16190 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16194 if (tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_10_100_only_device()
16205 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) in tg3_get_invariants() argument
16220 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16222 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16229 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16231 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16233 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16234 tp->misc_host_ctrl); in tg3_get_invariants()
16236 tg3_detect_asic_rev(tp, misc_ctrl_reg); in tg3_get_invariants()
16255 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) || in tg3_get_invariants()
16256 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) { in tg3_get_invariants()
16288 tp->pdev->bus->number)) { in tg3_get_invariants()
16289 tg3_flag_set(tp, ICH_WORKAROUND); in tg3_get_invariants()
16296 if (tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_get_invariants()
16318 tp->pdev->bus->number) && in tg3_get_invariants()
16320 tp->pdev->bus->number)) { in tg3_get_invariants()
16321 tg3_flag_set(tp, 5701_DMA_BUG); in tg3_get_invariants()
16334 if (tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16335 tg3_flag_set(tp, 40BIT_DMA_BUG); in tg3_get_invariants()
16336 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16346 tp->pdev->bus->number) && in tg3_get_invariants()
16348 tp->pdev->bus->number)) { in tg3_get_invariants()
16349 tg3_flag_set(tp, 40BIT_DMA_BUG); in tg3_get_invariants()
16356 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_invariants()
16357 tg3_asic_rev(tp) == ASIC_REV_5714) in tg3_get_invariants()
16358 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16361 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0) in tg3_get_invariants()
16363 else if (tg3_flag(tp, 57765_PLUS)) in tg3_get_invariants()
16364 tg3_flag_set(tp, HW_TSO_3); in tg3_get_invariants()
16365 else if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16366 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16367 tg3_flag_set(tp, HW_TSO_2); in tg3_get_invariants()
16368 else if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
16369 tg3_flag_set(tp, HW_TSO_1); in tg3_get_invariants()
16370 tg3_flag_set(tp, TSO_BUG); in tg3_get_invariants()
16371 if (tg3_asic_rev(tp) == ASIC_REV_5750 && in tg3_get_invariants()
16372 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2) in tg3_get_invariants()
16373 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16374 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_get_invariants()
16375 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_get_invariants()
16376 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_get_invariants()
16377 tg3_flag_set(tp, FW_TSO); in tg3_get_invariants()
16378 tg3_flag_set(tp, TSO_BUG); in tg3_get_invariants()
16379 if (tg3_asic_rev(tp) == ASIC_REV_5705) in tg3_get_invariants()
16380 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16382 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16386 if (tg3_flag(tp, HW_TSO_1) || in tg3_get_invariants()
16387 tg3_flag(tp, HW_TSO_2) || in tg3_get_invariants()
16388 tg3_flag(tp, HW_TSO_3) || in tg3_get_invariants()
16389 tg3_flag(tp, FW_TSO)) { in tg3_get_invariants()
16394 tg3_flag_set(tp, TSO_CAPABLE); in tg3_get_invariants()
16396 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16397 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16398 tp->fw_needed = NULL; in tg3_get_invariants()
16401 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) in tg3_get_invariants()
16402 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16404 if (tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_get_invariants()
16405 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16407 tp->irq_max = 1; in tg3_get_invariants()
16409 if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
16410 tg3_flag_set(tp, SUPPORT_MSI); in tg3_get_invariants()
16411 if (tg3_chip_rev(tp) == CHIPREV_5750_AX || in tg3_get_invariants()
16412 tg3_chip_rev(tp) == CHIPREV_5750_BX || in tg3_get_invariants()
16413 (tg3_asic_rev(tp) == ASIC_REV_5714 && in tg3_get_invariants()
16414 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 && in tg3_get_invariants()
16415 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16416 tg3_flag_clear(tp, SUPPORT_MSI); in tg3_get_invariants()
16418 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16419 tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16420 tg3_flag_set(tp, 1SHOT_MSI); in tg3_get_invariants()
16423 if (tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
16424 tg3_flag_set(tp, SUPPORT_MSIX); in tg3_get_invariants()
16425 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16429 tp->txq_max = 1; in tg3_get_invariants()
16430 tp->rxq_max = 1; in tg3_get_invariants()
16431 if (tp->irq_max > 1) { in tg3_get_invariants()
16432 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16433 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS); in tg3_get_invariants()
16435 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16436 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_get_invariants()
16437 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16440 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16441 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16442 tg3_flag_set(tp, SHORT_DMA_BUG); in tg3_get_invariants()
16444 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_get_invariants()
16445 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16447 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16448 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16449 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_get_invariants()
16450 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16451 tg3_flag_set(tp, LRG_PROD_RING_CAP); in tg3_get_invariants()
16453 if (tg3_flag(tp, 57765_PLUS) && in tg3_get_invariants()
16454 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0) in tg3_get_invariants()
16455 tg3_flag_set(tp, USE_JUMBO_BDFLAG); in tg3_get_invariants()
16457 if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
16458 tg3_flag(tp, 5780_CLASS) || in tg3_get_invariants()
16459 tg3_flag(tp, USE_JUMBO_BDFLAG)) in tg3_get_invariants()
16460 tg3_flag_set(tp, JUMBO_CAPABLE); in tg3_get_invariants()
16462 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16465 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16468 tg3_flag_set(tp, PCI_EXPRESS); in tg3_get_invariants()
16470 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16472 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16473 tg3_flag_clear(tp, HW_TSO_2); in tg3_get_invariants()
16474 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16476 if (tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_get_invariants()
16477 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_get_invariants()
16478 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 || in tg3_get_invariants()
16479 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1) in tg3_get_invariants()
16480 tg3_flag_set(tp, CLKREQ_BUG); in tg3_get_invariants()
16481 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) { in tg3_get_invariants()
16482 tg3_flag_set(tp, L1PLLPD_EN); in tg3_get_invariants()
16484 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_get_invariants()
16489 tg3_flag_set(tp, PCI_EXPRESS); in tg3_get_invariants()
16490 } else if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
16491 tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16492 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16493 if (!tp->pcix_cap) { in tg3_get_invariants()
16494 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16500 tg3_flag_set(tp, PCIX_MODE); in tg3_get_invariants()
16510 !tg3_flag(tp, PCI_EXPRESS)) in tg3_get_invariants()
16511 tg3_flag_set(tp, MBOX_WRITE_REORDER); in tg3_get_invariants()
16513 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16514 &tp->pci_cacheline_sz); in tg3_get_invariants()
16515 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16516 &tp->pci_lat_timer); in tg3_get_invariants()
16517 if (tg3_asic_rev(tp) == ASIC_REV_5703 && in tg3_get_invariants()
16518 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16519 tp->pci_lat_timer = 64; in tg3_get_invariants()
16520 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16521 tp->pci_lat_timer); in tg3_get_invariants()
16527 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) { in tg3_get_invariants()
16531 tg3_flag_set(tp, TXD_MBOX_HWBUG); in tg3_get_invariants()
16538 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16541 tg3_flag_set(tp, PCIX_TARGET_HWBUG); in tg3_get_invariants()
16547 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16548 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16552 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16553 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16557 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16559 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16564 tg3_flag_set(tp, PCI_HIGH_SPEED); in tg3_get_invariants()
16566 tg3_flag_set(tp, PCI_32BIT); in tg3_get_invariants()
16569 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) && in tg3_get_invariants()
16572 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16576 tp->read32 = tg3_read32; in tg3_get_invariants()
16577 tp->write32 = tg3_write32; in tg3_get_invariants()
16578 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16579 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16580 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16581 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16584 if (tg3_flag(tp, PCIX_TARGET_HWBUG)) in tg3_get_invariants()
16585 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16586 else if (tg3_asic_rev(tp) == ASIC_REV_5701 || in tg3_get_invariants()
16587 (tg3_flag(tp, PCI_EXPRESS) && in tg3_get_invariants()
16588 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) { in tg3_get_invariants()
16596 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16599 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { in tg3_get_invariants()
16600 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16601 if (tg3_flag(tp, MBOX_WRITE_REORDER)) in tg3_get_invariants()
16602 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16605 if (tg3_flag(tp, ICH_WORKAROUND)) { in tg3_get_invariants()
16606 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16607 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16608 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16609 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16610 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16611 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16613 iounmap(tp->regs); in tg3_get_invariants()
16614 tp->regs = NULL; in tg3_get_invariants()
16616 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16618 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16620 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16621 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16622 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16623 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16624 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16627 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16628 (tg3_flag(tp, PCIX_MODE) && in tg3_get_invariants()
16629 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16630 tg3_asic_rev(tp) == ASIC_REV_5701))) in tg3_get_invariants()
16631 tg3_flag_set(tp, SRAM_USE_CONFIG); in tg3_get_invariants()
16641 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16642 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_invariants()
16643 tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16644 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16645 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16646 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16648 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16650 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16651 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16652 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_get_invariants()
16653 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); in tg3_get_invariants()
16657 if (tg3_asic_rev(tp) == ASIC_REV_5717) in tg3_get_invariants()
16658 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16660 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16664 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { in tg3_get_invariants()
16665 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16666 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16677 tg3_get_eeprom_hw_cfg(tp); in tg3_get_invariants()
16679 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) { in tg3_get_invariants()
16680 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16681 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16682 tp->fw_needed = NULL; in tg3_get_invariants()
16685 if (tg3_flag(tp, ENABLE_APE)) { in tg3_get_invariants()
16692 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16695 tg3_ape_lock_init(tp); in tg3_get_invariants()
16696 tp->ape_hb_interval = in tg3_get_invariants()
16705 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16706 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16707 tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_get_invariants()
16708 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16713 else if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_get_invariants()
16714 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16716 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_get_invariants()
16717 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_get_invariants()
16718 tg3_flag(tp, 57765_CLASS)) in tg3_get_invariants()
16719 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16721 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16722 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16724 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16725 if (tg3_flag(tp, IS_NIC)) in tg3_get_invariants()
16727 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16731 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16732 tp->grc_local_ctrl |= in tg3_get_invariants()
16736 tg3_pwrsrc_switch_to_vmain(tp); in tg3_get_invariants()
16741 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16742 tg3_flag_set(tp, JUMBO_RING_ENABLE); in tg3_get_invariants()
16745 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16746 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
16747 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || in tg3_get_invariants()
16748 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) { in tg3_get_invariants()
16749 tg3_flag_clear(tp, WOL_SPEED_100MB); in tg3_get_invariants()
16751 tg3_flag_set(tp, WOL_SPEED_100MB); in tg3_get_invariants()
16754 if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16755 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16758 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16759 (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_get_invariants()
16760 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) && in tg3_get_invariants()
16761 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) || in tg3_get_invariants()
16762 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16763 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16764 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16766 if (tg3_chip_rev(tp) == CHIPREV_5703_AX || in tg3_get_invariants()
16767 tg3_chip_rev(tp) == CHIPREV_5704_AX) in tg3_get_invariants()
16768 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16769 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) in tg3_get_invariants()
16770 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16772 if (tg3_flag(tp, 5705_PLUS) && in tg3_get_invariants()
16773 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16774 tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_get_invariants()
16775 tg3_asic_rev(tp) != ASIC_REV_57780 && in tg3_get_invariants()
16776 !tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
16777 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_get_invariants()
16778 tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_get_invariants()
16779 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_get_invariants()
16780 tg3_asic_rev(tp) == ASIC_REV_5761) { in tg3_get_invariants()
16781 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16782 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16783 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16784 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16785 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16787 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16790 if (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_get_invariants()
16791 tg3_chip_rev(tp) != CHIPREV_5784_AX) { in tg3_get_invariants()
16792 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16793 if (tp->phy_otp == 0) in tg3_get_invariants()
16794 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16797 if (tg3_flag(tp, CPMU_PRESENT)) in tg3_get_invariants()
16798 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16800 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16802 tp->coalesce_mode = 0; in tg3_get_invariants()
16803 if (tg3_chip_rev(tp) != CHIPREV_5700_AX && in tg3_get_invariants()
16804 tg3_chip_rev(tp) != CHIPREV_5700_BX) in tg3_get_invariants()
16805 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16808 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16809 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_get_invariants()
16810 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_get_invariants()
16811 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) { in tg3_get_invariants()
16812 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16813 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16816 if (tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_get_invariants()
16817 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_get_invariants()
16818 tg3_flag_set(tp, USE_PHYLIB); in tg3_get_invariants()
16820 err = tg3_mdio_init(tp); in tg3_get_invariants()
16826 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_get_invariants()
16827 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16836 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16838 tg3_switch_clocks(tp); in tg3_get_invariants()
16846 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16849 !tg3_flag(tp, PCIX_TARGET_HWBUG)) { in tg3_get_invariants()
16850 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
16851 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || in tg3_get_invariants()
16852 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 || in tg3_get_invariants()
16853 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) { in tg3_get_invariants()
16860 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16866 tg3_flag_set(tp, PCIX_TARGET_HWBUG); in tg3_get_invariants()
16871 tg3_nvram_init(tp); in tg3_get_invariants()
16874 if (tg3_asic_rev(tp) == ASIC_REV_57766 && in tg3_get_invariants()
16875 !tg3_flag(tp, NO_NVRAM)) in tg3_get_invariants()
16876 tp->fw_needed = NULL; in tg3_get_invariants()
16881 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_get_invariants()
16884 tg3_flag_set(tp, IS_5788); in tg3_get_invariants()
16886 if (!tg3_flag(tp, IS_5788) && in tg3_get_invariants()
16887 tg3_asic_rev(tp) != ASIC_REV_5700) in tg3_get_invariants()
16888 tg3_flag_set(tp, TAGGED_STATUS); in tg3_get_invariants()
16889 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_get_invariants()
16890 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16893 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16894 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16895 tp->misc_host_ctrl); in tg3_get_invariants()
16899 if (tg3_flag(tp, ENABLE_APE)) in tg3_get_invariants()
16900 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16902 tp->mac_mode = 0; in tg3_get_invariants()
16904 if (tg3_10_100_only_device(tp, ent)) in tg3_get_invariants()
16905 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16907 err = tg3_phy_probe(tp); in tg3_get_invariants()
16909 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16911 tg3_mdio_fini(tp); in tg3_get_invariants()
16914 tg3_read_vpd(tp); in tg3_get_invariants()
16915 tg3_read_fw_ver(tp); in tg3_get_invariants()
16917 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16918 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16920 if (tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_get_invariants()
16921 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16923 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16930 if (tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_get_invariants()
16931 tg3_flag_set(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16933 tg3_flag_clear(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16939 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
16940 tg3_asic_rev(tp) == ASIC_REV_5701 && in tg3_get_invariants()
16941 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
16942 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16943 tg3_flag_set(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16947 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
16948 tg3_flag_set(tp, POLL_SERDES); in tg3_get_invariants()
16950 tg3_flag_clear(tp, POLL_SERDES); in tg3_get_invariants()
16952 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF)) in tg3_get_invariants()
16953 tg3_flag_set(tp, POLL_CPMU_LINK); in tg3_get_invariants()
16955 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
16956 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
16957 if (tg3_asic_rev(tp) == ASIC_REV_5701 && in tg3_get_invariants()
16958 tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16959 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
16961 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
16965 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
16966 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
16967 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
16969 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
16974 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_get_invariants()
16975 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_get_invariants()
16976 tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_get_invariants()
16977 tp->rx_std_max_post = 8; in tg3_get_invariants()
16979 if (tg3_flag(tp, ASPM_WORKAROUND)) in tg3_get_invariants()
16980 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
16986 static int tg3_get_device_address(struct tg3 *tp) in tg3_get_device_address() argument
16988 struct net_device *dev = tp->dev; in tg3_get_device_address()
16993 if (!eth_platform_get_mac_address(&tp->pdev->dev, dev->dev_addr)) in tg3_get_device_address()
16996 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_get_device_address()
16997 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]); in tg3_get_device_address()
17003 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_device_address()
17004 tg3_flag(tp, 5780_CLASS)) { in tg3_get_device_address()
17007 if (tg3_nvram_lock(tp)) in tg3_get_device_address()
17010 tg3_nvram_unlock(tp); in tg3_get_device_address()
17011 } else if (tg3_flag(tp, 5717_PLUS)) { in tg3_get_device_address()
17012 if (tp->pci_fn & 1) in tg3_get_device_address()
17014 if (tp->pci_fn > 1) in tg3_get_device_address()
17016 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_device_address()
17020 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); in tg3_get_device_address()
17025 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); in tg3_get_device_address()
17036 if (!tg3_flag(tp, NO_NVRAM) && in tg3_get_device_address()
17037 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && in tg3_get_device_address()
17038 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { in tg3_get_device_address()
17064 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val) in tg3_calc_dma_bndry() argument
17070 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17079 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_calc_dma_bndry()
17080 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_calc_dma_bndry()
17081 !tg3_flag(tp, PCI_EXPRESS)) in tg3_calc_dma_bndry()
17094 if (tg3_flag(tp, 57765_PLUS)) { in tg3_calc_dma_bndry()
17113 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
17138 } else if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
17205 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, in tg3_do_test_dma() argument
17256 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17258 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17260 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17293 static int tg3_test_dma(struct tg3 *tp) in tg3_test_dma() argument
17299 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17306 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17309 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17311 if (tg3_flag(tp, 57765_PLUS)) in tg3_test_dma()
17314 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_test_dma()
17316 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17317 } else if (!tg3_flag(tp, PCIX_MODE)) { in tg3_test_dma()
17318 if (tg3_asic_rev(tp) == ASIC_REV_5705 || in tg3_test_dma()
17319 tg3_asic_rev(tp) == ASIC_REV_5750) in tg3_test_dma()
17320 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17322 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17324 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_test_dma()
17325 tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_test_dma()
17333 if (tg3_flag(tp, 40BIT_DMA_BUG) && in tg3_test_dma()
17334 tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_test_dma()
17335 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17337 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17339 if (tg3_asic_rev(tp) == ASIC_REV_5703) in tg3_test_dma()
17342 tp->dma_rwctrl |= in tg3_test_dma()
17346 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) { in tg3_test_dma()
17348 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17349 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_test_dma()
17351 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17353 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17356 if (tg3_flag(tp, ONE_DMA_AT_ONCE)) in tg3_test_dma()
17357 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17359 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_test_dma()
17360 tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_test_dma()
17361 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17363 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_test_dma()
17364 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_test_dma()
17366 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17378 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17381 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17384 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_test_dma()
17385 tg3_asic_rev(tp) != ASIC_REV_5701) in tg3_test_dma()
17391 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17392 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17393 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17402 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true); in tg3_test_dma()
17404 dev_err(&tp->pdev->dev, in tg3_test_dma()
17411 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false); in tg3_test_dma()
17413 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17423 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17425 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17426 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17427 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17430 dev_err(&tp->pdev->dev, in tg3_test_dma()
17444 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17451 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17452 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17455 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17458 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17462 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17467 static void tg3_init_bufmgr_config(struct tg3 *tp) in tg3_init_bufmgr_config() argument
17469 if (tg3_flag(tp, 57765_PLUS)) { in tg3_init_bufmgr_config()
17470 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17472 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17474 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17477 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17479 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17481 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17483 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_bufmgr_config()
17484 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17486 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17488 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17490 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_init_bufmgr_config()
17491 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17493 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17497 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17499 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17501 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17504 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17506 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17508 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17511 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17513 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17515 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17519 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17520 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17523 static char *tg3_phy_string(struct tg3 *tp) in tg3_phy_string() argument
17525 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17555 static char *tg3_bus_string(struct tg3 *tp, char *str) in tg3_bus_string() argument
17557 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_bus_string()
17560 } else if (tg3_flag(tp, PCIX_MODE)) { in tg3_bus_string()
17579 if (tg3_flag(tp, PCI_HIGH_SPEED)) in tg3_bus_string()
17584 if (tg3_flag(tp, PCI_32BIT)) in tg3_bus_string()
17591 static void tg3_init_coal(struct tg3 *tp) in tg3_init_coal() argument
17593 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17607 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17615 if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_coal()
17626 struct tg3 *tp; in tg3_init_one() local
17647 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); in tg3_init_one()
17655 tp = netdev_priv(dev); in tg3_init_one()
17656 tp->pdev = pdev; in tg3_init_one()
17657 tp->dev = dev; in tg3_init_one()
17658 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17659 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17660 tp->irq_sync = 1; in tg3_init_one()
17661 tp->pcierr_recovery = false; in tg3_init_one()
17664 tp->msg_enable = tg3_debug; in tg3_init_one()
17666 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17669 tg3_flag_set(tp, IS_SSB_CORE); in tg3_init_one()
17671 tg3_flag_set(tp, FLUSH_POSTED_WRITES); in tg3_init_one()
17673 tg3_flag_set(tp, ONE_DMA_AT_ONCE); in tg3_init_one()
17675 tg3_flag_set(tp, USE_PHYLIB); in tg3_init_one()
17676 tg3_flag_set(tp, ROBOSWITCH); in tg3_init_one()
17679 tg3_flag_set(tp, RGMII_MODE); in tg3_init_one()
17686 tp->misc_host_ctrl = in tg3_init_one()
17698 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17701 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17703 spin_lock_init(&tp->lock); in tg3_init_one()
17704 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17705 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17707 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17708 if (!tp->regs) { in tg3_init_one()
17714 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17715 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17716 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17717 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17718 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17719 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17720 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17721 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17722 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17723 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17724 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17725 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17726 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17727 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17728 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17729 tg3_flag_set(tp, ENABLE_APE); in tg3_init_one()
17730 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17731 if (!tp->aperegs) { in tg3_init_one()
17739 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17740 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17747 err = tg3_get_invariants(tp, ent); in tg3_init_one()
17760 if (tg3_flag(tp, IS_5788)) in tg3_init_one()
17762 else if (tg3_flag(tp, 40BIT_DMA_BUG)) { in tg3_init_one()
17793 tg3_init_bufmgr_config(tp); in tg3_init_one()
17798 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) { in tg3_init_one()
17801 if (tg3_flag(tp, 5755_PLUS)) in tg3_init_one()
17809 if ((tg3_flag(tp, HW_TSO_1) || in tg3_init_one()
17810 tg3_flag(tp, HW_TSO_2) || in tg3_init_one()
17811 tg3_flag(tp, HW_TSO_3)) && in tg3_init_one()
17814 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { in tg3_init_one()
17817 if (tg3_flag(tp, HW_TSO_3) || in tg3_init_one()
17818 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_init_one()
17819 (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_init_one()
17820 tg3_chip_rev(tp) != CHIPREV_5784_AX) || in tg3_init_one()
17821 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_init_one()
17822 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_init_one()
17835 if (tg3_asic_rev(tp) != ASIC_REV_5780 && in tg3_init_one()
17836 !tg3_flag(tp, CPMU_PRESENT)) in tg3_init_one()
17845 dev->max_mtu = TG3_MAX_MTU(tp); in tg3_init_one()
17847 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 && in tg3_init_one()
17848 !tg3_flag(tp, TSO_CAPABLE) && in tg3_init_one()
17850 tg3_flag_set(tp, MAX_RXPEND_64); in tg3_init_one()
17851 tp->rx_pending = 63; in tg3_init_one()
17854 err = tg3_get_device_address(tp); in tg3_init_one()
17864 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17865 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17867 tnapi->tp = tp; in tg3_init_one()
17884 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_init_one()
17912 tg3_full_lock(tp, 0); in tg3_init_one()
17914 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_init_one()
17915 tg3_full_unlock(tp); in tg3_init_one()
17918 err = tg3_test_dma(tp); in tg3_init_one()
17924 tg3_init_coal(tp); in tg3_init_one()
17928 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_init_one()
17929 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_init_one()
17930 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_init_one()
17931 tg3_flag_set(tp, PTP_CAPABLE); in tg3_init_one()
17933 tg3_timer_init(tp); in tg3_init_one()
17935 tg3_carrier_off(tp); in tg3_init_one()
17943 if (tg3_flag(tp, PTP_CAPABLE)) { in tg3_init_one()
17944 tg3_ptp_init(tp); in tg3_init_one()
17945 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
17946 &tp->pdev->dev); in tg3_init_one()
17947 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
17948 tp->ptp_clock = NULL; in tg3_init_one()
17952 tp->board_part_number, in tg3_init_one()
17953 tg3_chip_rev_id(tp), in tg3_init_one()
17954 tg3_bus_string(tp, str), in tg3_init_one()
17957 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { in tg3_init_one()
17960 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
17962 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
17969 tg3_phy_string(tp), ethtype, in tg3_init_one()
17970 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
17971 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
17976 tg3_flag(tp, USE_LINKCHG_REG) != 0, in tg3_init_one()
17977 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
17978 tg3_flag(tp, ENABLE_ASF) != 0, in tg3_init_one()
17979 tg3_flag(tp, TSO_CAPABLE) != 0); in tg3_init_one()
17981 tp->dma_rwctrl, in tg3_init_one()
17990 if (tp->aperegs) { in tg3_init_one()
17991 iounmap(tp->aperegs); in tg3_init_one()
17992 tp->aperegs = NULL; in tg3_init_one()
17996 if (tp->regs) { in tg3_init_one()
17997 iounmap(tp->regs); in tg3_init_one()
17998 tp->regs = NULL; in tg3_init_one()
18018 struct tg3 *tp = netdev_priv(dev); in tg3_remove_one() local
18020 tg3_ptp_fini(tp); in tg3_remove_one()
18022 release_firmware(tp->fw); in tg3_remove_one()
18024 tg3_reset_task_cancel(tp); in tg3_remove_one()
18026 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_remove_one()
18027 tg3_phy_fini(tp); in tg3_remove_one()
18028 tg3_mdio_fini(tp); in tg3_remove_one()
18032 if (tp->aperegs) { in tg3_remove_one()
18033 iounmap(tp->aperegs); in tg3_remove_one()
18034 tp->aperegs = NULL; in tg3_remove_one()
18036 if (tp->regs) { in tg3_remove_one()
18037 iounmap(tp->regs); in tg3_remove_one()
18038 tp->regs = NULL; in tg3_remove_one()
18050 struct tg3 *tp = netdev_priv(dev); in tg3_suspend() local
18058 tg3_reset_task_cancel(tp); in tg3_suspend()
18059 tg3_phy_stop(tp); in tg3_suspend()
18060 tg3_netif_stop(tp); in tg3_suspend()
18062 tg3_timer_stop(tp); in tg3_suspend()
18064 tg3_full_lock(tp, 1); in tg3_suspend()
18065 tg3_disable_ints(tp); in tg3_suspend()
18066 tg3_full_unlock(tp); in tg3_suspend()
18070 tg3_full_lock(tp, 0); in tg3_suspend()
18071 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_suspend()
18072 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_suspend()
18073 tg3_full_unlock(tp); in tg3_suspend()
18075 err = tg3_power_down_prepare(tp); in tg3_suspend()
18079 tg3_full_lock(tp, 0); in tg3_suspend()
18081 tg3_flag_set(tp, INIT_COMPLETE); in tg3_suspend()
18082 err2 = tg3_restart_hw(tp, true); in tg3_suspend()
18086 tg3_timer_start(tp); in tg3_suspend()
18089 tg3_netif_start(tp); in tg3_suspend()
18092 tg3_full_unlock(tp); in tg3_suspend()
18095 tg3_phy_start(tp); in tg3_suspend()
18106 struct tg3 *tp = netdev_priv(dev); in tg3_resume() local
18116 tg3_full_lock(tp, 0); in tg3_resume()
18118 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_resume()
18120 tg3_flag_set(tp, INIT_COMPLETE); in tg3_resume()
18121 err = tg3_restart_hw(tp, in tg3_resume()
18122 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18126 tg3_timer_start(tp); in tg3_resume()
18128 tg3_netif_start(tp); in tg3_resume()
18131 tg3_full_unlock(tp); in tg3_resume()
18134 tg3_phy_start(tp); in tg3_resume()
18147 struct tg3 *tp = netdev_priv(dev); in tg3_shutdown() local
18149 tg3_reset_task_cancel(tp); in tg3_shutdown()
18158 tg3_power_down(tp); in tg3_shutdown()
18177 struct tg3 *tp = netdev_priv(netdev); in tg3_io_error_detected() local
18185 if (!netdev || tp->pcierr_recovery || !netif_running(netdev)) in tg3_io_error_detected()
18190 tp->pcierr_recovery = true; in tg3_io_error_detected()
18192 tg3_phy_stop(tp); in tg3_io_error_detected()
18194 tg3_netif_stop(tp); in tg3_io_error_detected()
18196 tg3_timer_stop(tp); in tg3_io_error_detected()
18199 tg3_reset_task_cancel(tp); in tg3_io_error_detected()
18204 tg3_full_lock(tp, 0); in tg3_io_error_detected()
18205 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_io_error_detected()
18206 tg3_full_unlock(tp); in tg3_io_error_detected()
18211 tg3_napi_enable(tp); in tg3_io_error_detected()
18236 struct tg3 *tp = netdev_priv(netdev); in tg3_io_slot_reset() local
18257 err = tg3_power_up(tp); in tg3_io_slot_reset()
18265 tg3_napi_enable(tp); in tg3_io_slot_reset()
18283 struct tg3 *tp = netdev_priv(netdev); in tg3_io_resume() local
18291 tg3_full_lock(tp, 0); in tg3_io_resume()
18292 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_io_resume()
18293 tg3_flag_set(tp, INIT_COMPLETE); in tg3_io_resume()
18294 err = tg3_restart_hw(tp, true); in tg3_io_resume()
18296 tg3_full_unlock(tp); in tg3_io_resume()
18303 tg3_timer_start(tp); in tg3_io_resume()
18305 tg3_netif_start(tp); in tg3_io_resume()
18307 tg3_full_unlock(tp); in tg3_io_resume()
18309 tg3_phy_start(tp); in tg3_io_resume()
18312 tp->pcierr_recovery = false; in tg3_io_resume()