80 #define RTL_W8(tp, reg, val8)	writeb((val8), tp->mmio_addr + (reg))  argument
81 #define RTL_W16(tp, reg, val16)	writew((val16), tp->mmio_addr + (reg))  argument
82 #define RTL_W32(tp, reg, val32)	writel((val32), tp->mmio_addr + (reg))  argument
83 #define RTL_R8(tp, reg)		readb(tp->mmio_addr + (reg))  argument
84 #define RTL_R16(tp, reg)		readw(tp->mmio_addr + (reg))  argument
85 #define RTL_R32(tp, reg)		readl(tp->mmio_addr + (reg))  argument
635 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
664 static inline struct device *tp_to_dev(struct rtl8169_private *tp)  in tp_to_dev()  argument
666 	return &tp->pci_dev->dev;  in tp_to_dev()
669 static void rtl_lock_config_regs(struct rtl8169_private *tp)  in rtl_lock_config_regs()  argument
671 	RTL_W8(tp, Cfg9346, Cfg9346_Lock);  in rtl_lock_config_regs()
674 static void rtl_unlock_config_regs(struct rtl8169_private *tp)  in rtl_unlock_config_regs()  argument
676 	RTL_W8(tp, Cfg9346, Cfg9346_Unlock);  in rtl_unlock_config_regs()
679 static void rtl_pci_commit(struct rtl8169_private *tp)  in rtl_pci_commit()  argument
682 	RTL_R8(tp, ChipCmd);  in rtl_pci_commit()
685 static bool rtl_is_8125(struct rtl8169_private *tp)  in rtl_is_8125()  argument
687 	return tp->mac_version >= RTL_GIGA_MAC_VER_60;  in rtl_is_8125()
690 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)  in rtl_is_8168evl_up()  argument
692 	return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&  in rtl_is_8168evl_up()
693 	       tp->mac_version != RTL_GIGA_MAC_VER_39 &&  in rtl_is_8168evl_up()
694 	       tp->mac_version <= RTL_GIGA_MAC_VER_52;  in rtl_is_8168evl_up()
697 static bool rtl_supports_eee(struct rtl8169_private *tp)  in rtl_supports_eee()  argument
699 	return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&  in rtl_supports_eee()
700 	       tp->mac_version != RTL_GIGA_MAC_VER_37 &&  in rtl_supports_eee()
701 	       tp->mac_version != RTL_GIGA_MAC_VER_39;  in rtl_supports_eee()
725 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)  in rtl_read_mac_from_reg()  argument
730 		mac[i] = RTL_R8(tp, reg + i);  in rtl_read_mac_from_reg()
738 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,  in rtl_loop_wait()  argument
744 		if (c->check(tp) == high)  in rtl_loop_wait()
750 		netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",  in rtl_loop_wait()
755 static bool rtl_loop_wait_high(struct rtl8169_private *tp,  in rtl_loop_wait_high()  argument
759 	return rtl_loop_wait(tp, c, d, n, true);  in rtl_loop_wait_high()
762 static bool rtl_loop_wait_low(struct rtl8169_private *tp,  in rtl_loop_wait_low()  argument
766 	return rtl_loop_wait(tp, c, d, n, false);  in rtl_loop_wait_low()
777 static bool name ## _check(struct rtl8169_private *tp)
779 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)  in rtl_ocp_reg_failure()  argument
783 			netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg);  in rtl_ocp_reg_failure()
791 	return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;  in DECLARE_RTL_COND()
794 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)  in r8168_phy_ocp_write()  argument
796 	if (rtl_ocp_reg_failure(tp, reg))  in r8168_phy_ocp_write()
799 	RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);  in r8168_phy_ocp_write()
801 	rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);  in r8168_phy_ocp_write()
804 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)  in r8168_phy_ocp_read()  argument
806 	if (rtl_ocp_reg_failure(tp, reg))  in r8168_phy_ocp_read()
809 	RTL_W32(tp, GPHY_OCP, reg << 15);  in r8168_phy_ocp_read()
811 	return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?  in r8168_phy_ocp_read()
812 		(RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;  in r8168_phy_ocp_read()
815 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)  in r8168_mac_ocp_write()  argument
817 	if (rtl_ocp_reg_failure(tp, reg))  in r8168_mac_ocp_write()
820 	RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);  in r8168_mac_ocp_write()
823 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)  in r8168_mac_ocp_read()  argument
825 	if (rtl_ocp_reg_failure(tp, reg))  in r8168_mac_ocp_read()
828 	RTL_W32(tp, OCPDR, reg << 15);  in r8168_mac_ocp_read()
830 	return RTL_R32(tp, OCPDR);  in r8168_mac_ocp_read()
833 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,  in r8168_mac_ocp_modify()  argument
836 	u16 data = r8168_mac_ocp_read(tp, reg);  in r8168_mac_ocp_modify()
838 	r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);  in r8168_mac_ocp_modify()
841 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8168g_mdio_write()  argument
844 		tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;  in r8168g_mdio_write()
848 	if (tp->ocp_base != OCP_STD_PHY_BASE)  in r8168g_mdio_write()
851 	r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);  in r8168g_mdio_write()
854 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)  in r8168g_mdio_read()  argument
857 		return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;  in r8168g_mdio_read()
859 	if (tp->ocp_base != OCP_STD_PHY_BASE)  in r8168g_mdio_read()
862 	return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);  in r8168g_mdio_read()
865 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)  in mac_mcu_write()  argument
868 		tp->ocp_base = value << 4;  in mac_mcu_write()
872 	r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);  in mac_mcu_write()
875 static int mac_mcu_read(struct rtl8169_private *tp, int reg)  in mac_mcu_read()  argument
877 	return r8168_mac_ocp_read(tp, tp->ocp_base + reg);  in mac_mcu_read()
882 	return RTL_R32(tp, PHYAR) & 0x80000000;  in DECLARE_RTL_COND()
885 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8169_mdio_write()  argument
887 	RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));  in r8169_mdio_write()
889 	rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);  in r8169_mdio_write()
897 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)  in r8169_mdio_read()  argument
901 	RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);  in r8169_mdio_read()
903 	value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?  in r8169_mdio_read()
904 		RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;  in r8169_mdio_read()
917 	return RTL_R32(tp, OCPAR) & OCPAR_FLAG;  in DECLARE_RTL_COND()
920 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)  in r8168dp_1_mdio_access()  argument
922 	RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));  in r8168dp_1_mdio_access()
923 	RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);  in r8168dp_1_mdio_access()
924 	RTL_W32(tp, EPHY_RXER_NUM, 0);  in r8168dp_1_mdio_access()
926 	rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);  in r8168dp_1_mdio_access()
929 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8168dp_1_mdio_write()  argument
931 	r8168dp_1_mdio_access(tp, reg,  in r8168dp_1_mdio_write()
935 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)  in r8168dp_1_mdio_read()  argument
937 	r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);  in r8168dp_1_mdio_read()
940 	RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);  in r8168dp_1_mdio_read()
941 	RTL_W32(tp, EPHY_RXER_NUM, 0);  in r8168dp_1_mdio_read()
943 	return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?  in r8168dp_1_mdio_read()
944 		RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;  in r8168dp_1_mdio_read()
949 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)  in r8168dp_2_mdio_start()  argument
951 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_start()
954 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)  in r8168dp_2_mdio_stop()  argument
956 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_stop()
959 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8168dp_2_mdio_write()  argument
961 	r8168dp_2_mdio_start(tp);  in r8168dp_2_mdio_write()
963 	r8169_mdio_write(tp, reg, value);  in r8168dp_2_mdio_write()
965 	r8168dp_2_mdio_stop(tp);  in r8168dp_2_mdio_write()
968 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)  in r8168dp_2_mdio_read()  argument
976 	r8168dp_2_mdio_start(tp);  in r8168dp_2_mdio_read()
978 	value = r8169_mdio_read(tp, reg);  in r8168dp_2_mdio_read()
980 	r8168dp_2_mdio_stop(tp);  in r8168dp_2_mdio_read()
985 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)  in rtl_writephy()  argument
987 	switch (tp->mac_version) {  in rtl_writephy()
989 		r8168dp_1_mdio_write(tp, location, val);  in rtl_writephy()
993 		r8168dp_2_mdio_write(tp, location, val);  in rtl_writephy()
996 		r8168g_mdio_write(tp, location, val);  in rtl_writephy()
999 		r8169_mdio_write(tp, location, val);  in rtl_writephy()
1004 static int rtl_readphy(struct rtl8169_private *tp, int location)  in rtl_readphy()  argument
1006 	switch (tp->mac_version) {  in rtl_readphy()
1008 		return r8168dp_1_mdio_read(tp, location);  in rtl_readphy()
1011 		return r8168dp_2_mdio_read(tp, location);  in rtl_readphy()
1013 		return r8168g_mdio_read(tp, location);  in rtl_readphy()
1015 		return r8169_mdio_read(tp, location);  in rtl_readphy()
1021 	return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;  in DECLARE_RTL_COND()
1024 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)  in rtl_ephy_write()  argument
1026 	RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |  in rtl_ephy_write()
1029 	rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);  in rtl_ephy_write()
1034 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)  in rtl_ephy_read()  argument
1036 	RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);  in rtl_ephy_read()
1038 	return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?  in rtl_ephy_read()
1039 		RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;  in rtl_ephy_read()
1042 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)  in r8168fp_adjust_ocp_cmd()  argument
1045 	if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)  in r8168fp_adjust_ocp_cmd()
1051 	return RTL_R32(tp, ERIAR) & ERIAR_FLAG;  in DECLARE_RTL_COND()
1054 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,  in _rtl_eri_write()  argument
1060 	RTL_W32(tp, ERIDR, val);  in _rtl_eri_write()
1061 	r8168fp_adjust_ocp_cmd(tp, &cmd, type);  in _rtl_eri_write()
1062 	RTL_W32(tp, ERIAR, cmd);  in _rtl_eri_write()
1064 	rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);  in _rtl_eri_write()
1067 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,  in rtl_eri_write()  argument
1070 	_rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);  in rtl_eri_write()
1073 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)  in _rtl_eri_read()  argument
1077 	r8168fp_adjust_ocp_cmd(tp, &cmd, type);  in _rtl_eri_read()
1078 	RTL_W32(tp, ERIAR, cmd);  in _rtl_eri_read()
1080 	return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?  in _rtl_eri_read()
1081 		RTL_R32(tp, ERIDR) : ~0;  in _rtl_eri_read()
1084 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)  in rtl_eri_read()  argument
1086 	return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);  in rtl_eri_read()
1089 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)  in rtl_w0w1_eri()  argument
1091 	u32 val = rtl_eri_read(tp, addr);  in rtl_w0w1_eri()
1093 	rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);  in rtl_w0w1_eri()
1096 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)  in rtl_eri_set_bits()  argument
1098 	rtl_w0w1_eri(tp, addr, p, 0);  in rtl_eri_set_bits()
1101 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)  in rtl_eri_clear_bits()  argument
1103 	rtl_w0w1_eri(tp, addr, 0, m);  in rtl_eri_clear_bits()
1106 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)  in r8168dp_ocp_read()  argument
1108 	RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));  in r8168dp_ocp_read()
1109 	return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?  in r8168dp_ocp_read()
1110 		RTL_R32(tp, OCPDR) : ~0;  in r8168dp_ocp_read()
1113 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)  in r8168ep_ocp_read()  argument
1115 	return _rtl_eri_read(tp, reg, ERIAR_OOB);  in r8168ep_ocp_read()
1118 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,  in r8168dp_ocp_write()  argument
1121 	RTL_W32(tp, OCPDR, data);  in r8168dp_ocp_write()
1122 	RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));  in r8168dp_ocp_write()
1123 	rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);  in r8168dp_ocp_write()
1126 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,  in r8168ep_ocp_write()  argument
1129 	_rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,  in r8168ep_ocp_write()
1133 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)  in r8168dp_oob_notify()  argument
1135 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);  in r8168dp_oob_notify()
1137 	r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);  in r8168dp_oob_notify()
1144 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)  in rtl8168_get_ocp_reg()  argument
1146 	return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;  in rtl8168_get_ocp_reg()
1153 	reg = rtl8168_get_ocp_reg(tp);  in DECLARE_RTL_COND()
1155 	return r8168dp_ocp_read(tp, reg) & 0x00000800;  in DECLARE_RTL_COND()
1160 	return r8168ep_ocp_read(tp, 0x124) & 0x00000001;  in DECLARE_RTL_COND()
1165 	return RTL_R8(tp, IBISR0) & 0x20;  in DECLARE_RTL_COND()
1168 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)  in rtl8168ep_stop_cmac()  argument
1170 	RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);  in rtl8168ep_stop_cmac()
1171 	rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);  in rtl8168ep_stop_cmac()
1172 	RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);  in rtl8168ep_stop_cmac()
1173 	RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);  in rtl8168ep_stop_cmac()
1176 static void rtl8168dp_driver_start(struct rtl8169_private *tp)  in rtl8168dp_driver_start()  argument
1178 	r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);  in rtl8168dp_driver_start()
1179 	rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);  in rtl8168dp_driver_start()
1182 static void rtl8168ep_driver_start(struct rtl8169_private *tp)  in rtl8168ep_driver_start()  argument
1184 	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);  in rtl8168ep_driver_start()
1185 	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);  in rtl8168ep_driver_start()
1186 	rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);  in rtl8168ep_driver_start()
1189 static void rtl8168_driver_start(struct rtl8169_private *tp)  in rtl8168_driver_start()  argument
1191 	switch (tp->mac_version) {  in rtl8168_driver_start()
1195 		rtl8168dp_driver_start(tp);  in rtl8168_driver_start()
1198 		rtl8168ep_driver_start(tp);  in rtl8168_driver_start()
1206 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)  in rtl8168dp_driver_stop()  argument
1208 	r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);  in rtl8168dp_driver_stop()
1209 	rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);  in rtl8168dp_driver_stop()
1212 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)  in rtl8168ep_driver_stop()  argument
1214 	rtl8168ep_stop_cmac(tp);  in rtl8168ep_driver_stop()
1215 	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);  in rtl8168ep_driver_stop()
1216 	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);  in rtl8168ep_driver_stop()
1217 	rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);  in rtl8168ep_driver_stop()
1220 static void rtl8168_driver_stop(struct rtl8169_private *tp)  in rtl8168_driver_stop()  argument
1222 	switch (tp->mac_version) {  in rtl8168_driver_stop()
1226 		rtl8168dp_driver_stop(tp);  in rtl8168_driver_stop()
1229 		rtl8168ep_driver_stop(tp);  in rtl8168_driver_stop()
1237 static bool r8168dp_check_dash(struct rtl8169_private *tp)  in r8168dp_check_dash()  argument
1239 	u16 reg = rtl8168_get_ocp_reg(tp);  in r8168dp_check_dash()
1241 	return !!(r8168dp_ocp_read(tp, reg) & 0x00008000);  in r8168dp_check_dash()
1244 static bool r8168ep_check_dash(struct rtl8169_private *tp)  in r8168ep_check_dash()  argument
1246 	return r8168ep_ocp_read(tp, 0x128) & 0x00000001;  in r8168ep_check_dash()
1249 static bool r8168_check_dash(struct rtl8169_private *tp)  in r8168_check_dash()  argument
1251 	switch (tp->mac_version) {  in r8168_check_dash()
1255 		return r8168dp_check_dash(tp);  in r8168_check_dash()
1257 		return r8168ep_check_dash(tp);  in r8168_check_dash()
1263 static void rtl_reset_packet_filter(struct rtl8169_private *tp)  in rtl_reset_packet_filter()  argument
1265 	rtl_eri_clear_bits(tp, 0xdc, BIT(0));  in rtl_reset_packet_filter()
1266 	rtl_eri_set_bits(tp, 0xdc, BIT(0));  in rtl_reset_packet_filter()
1271 	return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;  in DECLARE_RTL_COND()
1274 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)  in rtl8168d_efuse_read()  argument
1276 	RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);  in rtl8168d_efuse_read()
1278 	return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?  in rtl8168d_efuse_read()
1279 		RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;  in rtl8168d_efuse_read()
1282 static u32 rtl_get_events(struct rtl8169_private *tp)  in rtl_get_events()  argument
1284 	if (rtl_is_8125(tp))  in rtl_get_events()
1285 		return RTL_R32(tp, IntrStatus_8125);  in rtl_get_events()
1287 		return RTL_R16(tp, IntrStatus);  in rtl_get_events()
1290 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)  in rtl_ack_events()  argument
1292 	if (rtl_is_8125(tp))  in rtl_ack_events()
1293 		RTL_W32(tp, IntrStatus_8125, bits);  in rtl_ack_events()
1295 		RTL_W16(tp, IntrStatus, bits);  in rtl_ack_events()
1298 static void rtl_irq_disable(struct rtl8169_private *tp)  in rtl_irq_disable()  argument
1300 	if (rtl_is_8125(tp))  in rtl_irq_disable()
1301 		RTL_W32(tp, IntrMask_8125, 0);  in rtl_irq_disable()
1303 		RTL_W16(tp, IntrMask, 0);  in rtl_irq_disable()
1306 static void rtl_irq_enable(struct rtl8169_private *tp)  in rtl_irq_enable()  argument
1308 	if (rtl_is_8125(tp))  in rtl_irq_enable()
1309 		RTL_W32(tp, IntrMask_8125, tp->irq_mask);  in rtl_irq_enable()
1311 		RTL_W16(tp, IntrMask, tp->irq_mask);  in rtl_irq_enable()
1314 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)  in rtl8169_irq_mask_and_ack()  argument
1316 	rtl_irq_disable(tp);  in rtl8169_irq_mask_and_ack()
1317 	rtl_ack_events(tp, 0xffffffff);  in rtl8169_irq_mask_and_ack()
1318 	rtl_pci_commit(tp);  in rtl8169_irq_mask_and_ack()
1321 static void rtl_link_chg_patch(struct rtl8169_private *tp)  in rtl_link_chg_patch()  argument
1323 	struct phy_device *phydev = tp->phydev;  in rtl_link_chg_patch()
1325 	if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||  in rtl_link_chg_patch()
1326 	    tp->mac_version == RTL_GIGA_MAC_VER_38) {  in rtl_link_chg_patch()
1328 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);  in rtl_link_chg_patch()
1329 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);  in rtl_link_chg_patch()
1331 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);  in rtl_link_chg_patch()
1332 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);  in rtl_link_chg_patch()
1334 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);  in rtl_link_chg_patch()
1335 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);  in rtl_link_chg_patch()
1337 		rtl_reset_packet_filter(tp);  in rtl_link_chg_patch()
1338 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||  in rtl_link_chg_patch()
1339 		   tp->mac_version == RTL_GIGA_MAC_VER_36) {  in rtl_link_chg_patch()
1341 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);  in rtl_link_chg_patch()
1342 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);  in rtl_link_chg_patch()
1344 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);  in rtl_link_chg_patch()
1345 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);  in rtl_link_chg_patch()
1347 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {  in rtl_link_chg_patch()
1349 			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);  in rtl_link_chg_patch()
1350 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);  in rtl_link_chg_patch()
1352 			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);  in rtl_link_chg_patch()
1361 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_wol()  local
1364 	wol->wolopts = tp->saved_wolopts;  in rtl8169_get_wol()
1367 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)  in __rtl8169_set_wol()  argument
1384 	rtl_unlock_config_regs(tp);  in __rtl8169_set_wol()
1386 	if (rtl_is_8168evl_up(tp)) {  in __rtl8169_set_wol()
1389 			rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);  in __rtl8169_set_wol()
1391 			rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);  in __rtl8169_set_wol()
1392 	} else if (rtl_is_8125(tp)) {  in __rtl8169_set_wol()
1395 			r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));  in __rtl8169_set_wol()
1397 			r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);  in __rtl8169_set_wol()
1401 		options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;  in __rtl8169_set_wol()
1404 		RTL_W8(tp, cfg[i].reg, options);  in __rtl8169_set_wol()
1407 	switch (tp->mac_version) {  in __rtl8169_set_wol()
1409 		options = RTL_R8(tp, Config1) & ~PMEnable;  in __rtl8169_set_wol()
1412 		RTL_W8(tp, Config1, options);  in __rtl8169_set_wol()
1417 		options = RTL_R8(tp, Config2) & ~PME_SIGNAL;  in __rtl8169_set_wol()
1420 		RTL_W8(tp, Config2, options);  in __rtl8169_set_wol()
1426 	rtl_lock_config_regs(tp);  in __rtl8169_set_wol()
1428 	device_set_wakeup_enable(tp_to_dev(tp), wolopts);  in __rtl8169_set_wol()
1429 	tp->dev->wol_enabled = wolopts ? 1 : 0;  in __rtl8169_set_wol()
1434 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_wol()  local
1439 	tp->saved_wolopts = wol->wolopts;  in rtl8169_set_wol()
1440 	__rtl8169_set_wol(tp, tp->saved_wolopts);  in rtl8169_set_wol()
1448 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_drvinfo()  local
1449 	struct rtl_fw *rtl_fw = tp->rtl_fw;  in rtl8169_get_drvinfo()
1452 	strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));  in rtl8169_get_drvinfo()
1467 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_fix_features()  local
1473 	    tp->mac_version > RTL_GIGA_MAC_VER_06)  in rtl8169_fix_features()
1479 static void rtl_set_rx_config_features(struct rtl8169_private *tp,  in rtl_set_rx_config_features()  argument
1482 	u32 rx_config = RTL_R32(tp, RxConfig);  in rtl_set_rx_config_features()
1489 	if (rtl_is_8125(tp)) {  in rtl_set_rx_config_features()
1496 	RTL_W32(tp, RxConfig, rx_config);  in rtl_set_rx_config_features()
1502 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_features()  local
1504 	rtl_set_rx_config_features(tp, features);  in rtl8169_set_features()
1507 		tp->cp_cmd |= RxChkSum;  in rtl8169_set_features()
1509 		tp->cp_cmd &= ~RxChkSum;  in rtl8169_set_features()
1511 	if (!rtl_is_8125(tp)) {  in rtl8169_set_features()
1513 			tp->cp_cmd |= RxVlan;  in rtl8169_set_features()
1515 			tp->cp_cmd &= ~RxVlan;  in rtl8169_set_features()
1518 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl8169_set_features()
1519 	rtl_pci_commit(tp);  in rtl8169_set_features()
1541 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_regs()  local
1542 	u32 __iomem *data = tp->mmio_addr;  in rtl8169_get_regs()
1578 	return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);  in DECLARE_RTL_COND()
1581 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)  in rtl8169_do_counters()  argument
1583 	dma_addr_t paddr = tp->counters_phys_addr;  in rtl8169_do_counters()
1586 	RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);  in rtl8169_do_counters()
1587 	rtl_pci_commit(tp);  in rtl8169_do_counters()
1589 	RTL_W32(tp, CounterAddrLow, cmd);  in rtl8169_do_counters()
1590 	RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);  in rtl8169_do_counters()
1592 	rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);  in rtl8169_do_counters()
1595 static void rtl8169_reset_counters(struct rtl8169_private *tp)  in rtl8169_reset_counters()  argument
1601 	if (tp->mac_version >= RTL_GIGA_MAC_VER_19)  in rtl8169_reset_counters()
1602 		rtl8169_do_counters(tp, CounterReset);  in rtl8169_reset_counters()
1605 static void rtl8169_update_counters(struct rtl8169_private *tp)  in rtl8169_update_counters()  argument
1607 	u8 val = RTL_R8(tp, ChipCmd);  in rtl8169_update_counters()
1614 		rtl8169_do_counters(tp, CounterDump);  in rtl8169_update_counters()
1617 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)  in rtl8169_init_counter_offsets()  argument
1619 	struct rtl8169_counters *counters = tp->counters;  in rtl8169_init_counter_offsets()
1636 	if (tp->tc_offset.inited)  in rtl8169_init_counter_offsets()
1639 	rtl8169_reset_counters(tp);  in rtl8169_init_counter_offsets()
1640 	rtl8169_update_counters(tp);  in rtl8169_init_counter_offsets()
1642 	tp->tc_offset.tx_errors = counters->tx_errors;  in rtl8169_init_counter_offsets()
1643 	tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;  in rtl8169_init_counter_offsets()
1644 	tp->tc_offset.tx_aborted = counters->tx_aborted;  in rtl8169_init_counter_offsets()
1645 	tp->tc_offset.rx_missed = counters->rx_missed;  in rtl8169_init_counter_offsets()
1646 	tp->tc_offset.inited = true;  in rtl8169_init_counter_offsets()
1652 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_ethtool_stats()  local
1655 	counters = tp->counters;  in rtl8169_get_ethtool_stats()
1656 	rtl8169_update_counters(tp);  in rtl8169_get_ethtool_stats()
1736 rtl_coalesce_info(struct rtl8169_private *tp)  in rtl_coalesce_info()  argument
1740 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)  in rtl_coalesce_info()
1746 	if (tp->phydev->speed == SPEED_UNKNOWN)  in rtl_coalesce_info()
1750 		if (tp->phydev->speed == ci->speed)  in rtl_coalesce_info()
1759 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_get_coalesce()  local
1764 	if (rtl_is_8125(tp))  in rtl_get_coalesce()
1770 	ci = rtl_coalesce_info(tp);  in rtl_get_coalesce()
1774 	scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];  in rtl_get_coalesce()
1776 	intrmit = RTL_R16(tp, IntrMitigate);  in rtl_get_coalesce()
1795 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,  in rtl_coalesce_choose_scale()  argument
1801 	ci = rtl_coalesce_info(tp);  in rtl_coalesce_choose_scale()
1817 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_set_coalesce()  local
1824 	if (rtl_is_8125(tp))  in rtl_set_coalesce()
1831 	scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);  in rtl_set_coalesce()
1863 	RTL_W16(tp, IntrMitigate, w);  in rtl_set_coalesce()
1866 	if (rtl_is_8168evl_up(tp)) {  in rtl_set_coalesce()
1869 			tp->cp_cmd |= PktCntrDisable;  in rtl_set_coalesce()
1871 			tp->cp_cmd &= ~PktCntrDisable;  in rtl_set_coalesce()
1874 	tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;  in rtl_set_coalesce()
1875 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl_set_coalesce()
1876 	rtl_pci_commit(tp);  in rtl_set_coalesce()
1883 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_eee()  local
1885 	if (!rtl_supports_eee(tp))  in rtl8169_get_eee()
1888 	return phy_ethtool_get_eee(tp->phydev, data);  in rtl8169_get_eee()
1893 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_eee()  local
1896 	if (!rtl_supports_eee(tp))  in rtl8169_set_eee()
1899 	ret = phy_ethtool_set_eee(tp->phydev, data);  in rtl8169_set_eee()
1902 		tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,  in rtl8169_set_eee()
1929 static void rtl_enable_eee(struct rtl8169_private *tp)  in rtl_enable_eee()  argument
1931 	struct phy_device *phydev = tp->phydev;  in rtl_enable_eee()
1935 	if (tp->eee_adv >= 0)  in rtl_enable_eee()
1936 		adv = tp->eee_adv;  in rtl_enable_eee()
2069 static void rtl_release_firmware(struct rtl8169_private *tp)  in rtl_release_firmware()  argument
2071 	if (tp->rtl_fw) {  in rtl_release_firmware()
2072 		rtl_fw_release_firmware(tp->rtl_fw);  in rtl_release_firmware()
2073 		kfree(tp->rtl_fw);  in rtl_release_firmware()
2074 		tp->rtl_fw = NULL;  in rtl_release_firmware()
2078 void r8169_apply_firmware(struct rtl8169_private *tp)  in r8169_apply_firmware()  argument
2083 	if (tp->rtl_fw) {  in r8169_apply_firmware()
2084 		rtl_fw_write_firmware(tp, tp->rtl_fw);  in r8169_apply_firmware()
2086 		tp->ocp_base = OCP_STD_PHY_BASE;  in r8169_apply_firmware()
2089 		phy_read_poll_timeout(tp->phydev, MII_BMCR, val,  in r8169_apply_firmware()
2095 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)  in rtl8168_config_eee_mac()  argument
2098 	if (tp->mac_version != RTL_GIGA_MAC_VER_38)  in rtl8168_config_eee_mac()
2099 		RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);  in rtl8168_config_eee_mac()
2101 	rtl_eri_set_bits(tp, 0x1b0, 0x0003);  in rtl8168_config_eee_mac()
2104 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)  in rtl8125a_config_eee_mac()  argument
2106 	r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));  in rtl8125a_config_eee_mac()
2107 	r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));  in rtl8125a_config_eee_mac()
2110 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)  in rtl8125_set_eee_txidle_timer()  argument
2112 	RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);  in rtl8125_set_eee_txidle_timer()
2115 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)  in rtl8125b_config_eee_mac()  argument
2117 	rtl8125_set_eee_txidle_timer(tp);  in rtl8125b_config_eee_mac()
2118 	r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));  in rtl8125b_config_eee_mac()
2121 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)  in rtl_rar_exgmac_set()  argument
2129 	rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));  in rtl_rar_exgmac_set()
2130 	rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);  in rtl_rar_exgmac_set()
2131 	rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);  in rtl_rar_exgmac_set()
2132 	rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));  in rtl_rar_exgmac_set()
2135 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)  in rtl8168h_2_get_adc_bias_ioffset()  argument
2139 	r8168_mac_ocp_write(tp, 0xdd02, 0x807d);  in rtl8168h_2_get_adc_bias_ioffset()
2140 	data1 = r8168_mac_ocp_read(tp, 0xdd02);  in rtl8168h_2_get_adc_bias_ioffset()
2141 	data2 = r8168_mac_ocp_read(tp, 0xdd00);  in rtl8168h_2_get_adc_bias_ioffset()
2151 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)  in rtl_schedule_task()  argument
2153 	set_bit(flag, tp->wk.flags);  in rtl_schedule_task()
2154 	schedule_work(&tp->wk.work);  in rtl_schedule_task()
2157 static void rtl8169_init_phy(struct rtl8169_private *tp)  in rtl8169_init_phy()  argument
2159 	r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);  in rtl8169_init_phy()
2161 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {  in rtl8169_init_phy()
2162 		pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);  in rtl8169_init_phy()
2163 		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);  in rtl8169_init_phy()
2165 		RTL_W8(tp, 0x82, 0x01);  in rtl8169_init_phy()
2168 	if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&  in rtl8169_init_phy()
2169 	    tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&  in rtl8169_init_phy()
2170 	    tp->pci_dev->subsystem_device == 0xe000)  in rtl8169_init_phy()
2171 		phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);  in rtl8169_init_phy()
2174 	phy_speed_up(tp->phydev);  in rtl8169_init_phy()
2176 	if (rtl_supports_eee(tp))  in rtl8169_init_phy()
2177 		rtl_enable_eee(tp);  in rtl8169_init_phy()
2179 	genphy_soft_reset(tp->phydev);  in rtl8169_init_phy()
2182 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)  in rtl_rar_set()  argument
2184 	rtl_unlock_config_regs(tp);  in rtl_rar_set()
2186 	RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);  in rtl_rar_set()
2187 	rtl_pci_commit(tp);  in rtl_rar_set()
2189 	RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);  in rtl_rar_set()
2190 	rtl_pci_commit(tp);  in rtl_rar_set()
2192 	if (tp->mac_version == RTL_GIGA_MAC_VER_34)  in rtl_rar_set()
2193 		rtl_rar_exgmac_set(tp, addr);  in rtl_rar_set()
2195 	rtl_lock_config_regs(tp);  in rtl_rar_set()
2200 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_set_mac_address()  local
2207 	rtl_rar_set(tp, dev->dev_addr);  in rtl_set_mac_address()
2212 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)  in rtl_wol_suspend_quirk()  argument
2214 	switch (tp->mac_version) {  in rtl_wol_suspend_quirk()
2223 		RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |  in rtl_wol_suspend_quirk()
2231 static void rtl_pll_power_down(struct rtl8169_private *tp)  in rtl_pll_power_down()  argument
2233 	if (r8168_check_dash(tp))  in rtl_pll_power_down()
2236 	if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||  in rtl_pll_power_down()
2237 	    tp->mac_version == RTL_GIGA_MAC_VER_33)  in rtl_pll_power_down()
2238 		rtl_ephy_write(tp, 0x19, 0xff64);  in rtl_pll_power_down()
2240 	if (device_may_wakeup(tp_to_dev(tp))) {  in rtl_pll_power_down()
2241 		phy_speed_down(tp->phydev, false);  in rtl_pll_power_down()
2242 		rtl_wol_suspend_quirk(tp);  in rtl_pll_power_down()
2246 	switch (tp->mac_version) {  in rtl_pll_power_down()
2259 		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);  in rtl_pll_power_down()
2264 		rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);  in rtl_pll_power_down()
2265 		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);  in rtl_pll_power_down()
2272 static void rtl_pll_power_up(struct rtl8169_private *tp)  in rtl_pll_power_up()  argument
2274 	switch (tp->mac_version) {  in rtl_pll_power_up()
2281 		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);  in rtl_pll_power_up()
2289 		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);  in rtl_pll_power_up()
2294 		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);  in rtl_pll_power_up()
2295 		rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);  in rtl_pll_power_up()
2301 	phy_resume(tp->phydev);  in rtl_pll_power_up()
2304 static void rtl_init_rxcfg(struct rtl8169_private *tp)  in rtl_init_rxcfg()  argument
2306 	switch (tp->mac_version) {  in rtl_init_rxcfg()
2309 		RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);  in rtl_init_rxcfg()
2314 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);  in rtl_init_rxcfg()
2317 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);  in rtl_init_rxcfg()
2320 		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);  in rtl_init_rxcfg()
2323 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);  in rtl_init_rxcfg()
2328 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)  in rtl8169_init_ring_indexes()  argument
2330 	tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;  in rtl8169_init_ring_indexes()
2333 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168c_hw_jumbo_enable()  argument
2335 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);  in r8168c_hw_jumbo_enable()
2336 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);  in r8168c_hw_jumbo_enable()
2339 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168c_hw_jumbo_disable()  argument
2341 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);  in r8168c_hw_jumbo_disable()
2342 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);  in r8168c_hw_jumbo_disable()
2345 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168dp_hw_jumbo_enable()  argument
2347 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);  in r8168dp_hw_jumbo_enable()
2350 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168dp_hw_jumbo_disable()  argument
2352 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);  in r8168dp_hw_jumbo_disable()
2355 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168e_hw_jumbo_enable()  argument
2357 	RTL_W8(tp, MaxTxPacketSize, 0x24);  in r8168e_hw_jumbo_enable()
2358 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);  in r8168e_hw_jumbo_enable()
2359 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);  in r8168e_hw_jumbo_enable()
2362 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168e_hw_jumbo_disable()  argument
2364 	RTL_W8(tp, MaxTxPacketSize, 0x3f);  in r8168e_hw_jumbo_disable()
2365 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);  in r8168e_hw_jumbo_disable()
2366 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);  in r8168e_hw_jumbo_disable()
2369 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168b_1_hw_jumbo_enable()  argument
2371 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));  in r8168b_1_hw_jumbo_enable()
2374 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168b_1_hw_jumbo_disable()  argument
2376 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));  in r8168b_1_hw_jumbo_disable()
2379 static void rtl_jumbo_config(struct rtl8169_private *tp)  in rtl_jumbo_config()  argument
2381 	bool jumbo = tp->dev->mtu > ETH_DATA_LEN;  in rtl_jumbo_config()
2384 	rtl_unlock_config_regs(tp);  in rtl_jumbo_config()
2385 	switch (tp->mac_version) {  in rtl_jumbo_config()
2390 			r8168b_1_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2392 			r8168b_1_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2398 			r8168c_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2400 			r8168c_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2405 			r8168dp_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2407 			r8168dp_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2411 			pcie_set_readrq(tp->pci_dev, 512);  in rtl_jumbo_config()
2412 			r8168e_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2414 			r8168e_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2420 	rtl_lock_config_regs(tp);  in rtl_jumbo_config()
2422 	if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)  in rtl_jumbo_config()
2423 		pcie_set_readrq(tp->pci_dev, readrq);  in rtl_jumbo_config()
2427 			 tp->phydev->advertising, !jumbo);  in rtl_jumbo_config()
2429 			 tp->phydev->advertising, !jumbo);  in rtl_jumbo_config()
2430 	phy_start_aneg(tp->phydev);  in rtl_jumbo_config()
2435 	return RTL_R8(tp, ChipCmd) & CmdReset;  in DECLARE_RTL_COND()
2438 static void rtl_hw_reset(struct rtl8169_private *tp)  in rtl_hw_reset()  argument
2440 	RTL_W8(tp, ChipCmd, CmdReset);  in rtl_hw_reset()
2442 	rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);  in rtl_hw_reset()
2445 static void rtl_request_firmware(struct rtl8169_private *tp)  in rtl_request_firmware()  argument
2450 	if (tp->rtl_fw || !tp->fw_name)  in rtl_request_firmware()
2461 	rtl_fw->fw_name = tp->fw_name;  in rtl_request_firmware()
2462 	rtl_fw->dev = tp_to_dev(tp);  in rtl_request_firmware()
2467 		tp->rtl_fw = rtl_fw;  in rtl_request_firmware()
2470 static void rtl_rx_close(struct rtl8169_private *tp)  in rtl_rx_close()  argument
2472 	RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);  in rtl_rx_close()
2477 	return RTL_R8(tp, TxPoll) & NPQ;  in DECLARE_RTL_COND()
2482 	return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;  in DECLARE_RTL_COND()
2487 	return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;  in DECLARE_RTL_COND()
2493 	return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;  in DECLARE_RTL_COND()
2496 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)  in rtl_wait_txrx_fifo_empty()  argument
2498 	switch (tp->mac_version) {  in rtl_wait_txrx_fifo_empty()
2500 		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2501 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2504 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2507 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);  in rtl_wait_txrx_fifo_empty()
2508 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2509 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);  in rtl_wait_txrx_fifo_empty()
2516 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)  in rtl_enable_rxdvgate()  argument
2518 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);  in rtl_enable_rxdvgate()
2520 	rtl_wait_txrx_fifo_empty(tp);  in rtl_enable_rxdvgate()
2523 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)  in rtl_set_tx_config_registers()  argument
2528 	if (rtl_is_8168evl_up(tp))  in rtl_set_tx_config_registers()
2531 	RTL_W32(tp, TxConfig, val);  in rtl_set_tx_config_registers()
2534 static void rtl_set_rx_max_size(struct rtl8169_private *tp)  in rtl_set_rx_max_size()  argument
2537 	RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);  in rtl_set_rx_max_size()
2540 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)  in rtl_set_rx_tx_desc_registers()  argument
2547 	RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);  in rtl_set_rx_tx_desc_registers()
2548 	RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));  in rtl_set_rx_tx_desc_registers()
2549 	RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);  in rtl_set_rx_tx_desc_registers()
2550 	RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));  in rtl_set_rx_tx_desc_registers()
2553 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)  in rtl8169_set_magic_reg()  argument
2557 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)  in rtl8169_set_magic_reg()
2559 	else if (tp->mac_version == RTL_GIGA_MAC_VER_06)  in rtl8169_set_magic_reg()
2564 	if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)  in rtl8169_set_magic_reg()
2567 	RTL_W32(tp, 0x7c, val);  in rtl8169_set_magic_reg()
2575 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_set_rx_mode()  local
2582 		   tp->mac_version == RTL_GIGA_MAC_VER_35) {  in rtl_set_rx_mode()
2595 		if (tp->mac_version > RTL_GIGA_MAC_VER_06) {  in rtl_set_rx_mode()
2602 	RTL_W32(tp, MAR0 + 4, mc_filter[1]);  in rtl_set_rx_mode()
2603 	RTL_W32(tp, MAR0 + 0, mc_filter[0]);  in rtl_set_rx_mode()
2605 	tmp = RTL_R32(tp, RxConfig);  in rtl_set_rx_mode()
2606 	RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);  in rtl_set_rx_mode()
2611 	return RTL_R32(tp, CSIAR) & CSIAR_FLAG;  in DECLARE_RTL_COND()
2614 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)  in rtl_csi_write()  argument
2616 	u32 func = PCI_FUNC(tp->pci_dev->devfn);  in rtl_csi_write()
2618 	RTL_W32(tp, CSIDR, value);  in rtl_csi_write()
2619 	RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |  in rtl_csi_write()
2622 	rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);  in rtl_csi_write()
2625 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)  in rtl_csi_read()  argument
2627 	u32 func = PCI_FUNC(tp->pci_dev->devfn);  in rtl_csi_read()
2629 	RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |  in rtl_csi_read()
2632 	return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?  in rtl_csi_read()
2633 		RTL_R32(tp, CSIDR) : ~0;  in rtl_csi_read()
2636 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)  in rtl_csi_access_enable()  argument
2638 	struct pci_dev *pdev = tp->pci_dev;  in rtl_csi_access_enable()
2649 	netdev_notice_once(tp->dev,  in rtl_csi_access_enable()
2651 	csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;  in rtl_csi_access_enable()
2652 	rtl_csi_write(tp, 0x070c, csi | val << 24);  in rtl_csi_access_enable()
2655 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)  in rtl_set_def_aspm_entry_latency()  argument
2657 	rtl_csi_access_enable(tp, 0x27);  in rtl_set_def_aspm_entry_latency()
2666 static void __rtl_ephy_init(struct rtl8169_private *tp,  in __rtl_ephy_init()  argument
2672 		w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;  in __rtl_ephy_init()
2673 		rtl_ephy_write(tp, e->offset, w);  in __rtl_ephy_init()
2678 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))  argument
2680 static void rtl_disable_clock_request(struct rtl8169_private *tp)  in rtl_disable_clock_request()  argument
2682 	pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,  in rtl_disable_clock_request()
2686 static void rtl_enable_clock_request(struct rtl8169_private *tp)  in rtl_enable_clock_request()  argument
2688 	pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,  in rtl_enable_clock_request()
2692 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)  in rtl_pcie_state_l2l3_disable()  argument
2695 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);  in rtl_pcie_state_l2l3_disable()
2698 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)  in rtl_hw_aspm_clkreq_enable()  argument
2701 	if (enable && tp->aspm_manageable) {  in rtl_hw_aspm_clkreq_enable()
2702 		RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);  in rtl_hw_aspm_clkreq_enable()
2703 		RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);  in rtl_hw_aspm_clkreq_enable()
2705 		RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);  in rtl_hw_aspm_clkreq_enable()
2706 		RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);  in rtl_hw_aspm_clkreq_enable()
2712 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,  in rtl_set_fifo_size()  argument
2718 	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);  in rtl_set_fifo_size()
2719 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);  in rtl_set_fifo_size()
2722 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,  in rtl8168g_set_pause_thresholds()  argument
2726 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);  in rtl8168g_set_pause_thresholds()
2727 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);  in rtl8168g_set_pause_thresholds()
2730 static void rtl_hw_start_8168b(struct rtl8169_private *tp)  in rtl_hw_start_8168b()  argument
2732 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8168b()
2735 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)  in __rtl_hw_start_8168cp()  argument
2737 	RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);  in __rtl_hw_start_8168cp()
2739 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in __rtl_hw_start_8168cp()
2741 	rtl_disable_clock_request(tp);  in __rtl_hw_start_8168cp()
2744 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)  in rtl_hw_start_8168cp_1()  argument
2754 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168cp_1()
2756 	rtl_ephy_init(tp, e_info_8168cp);  in rtl_hw_start_8168cp_1()
2758 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168cp_1()
2761 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)  in rtl_hw_start_8168cp_2()  argument
2763 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168cp_2()
2765 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8168cp_2()
2768 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)  in rtl_hw_start_8168cp_3()  argument
2770 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168cp_3()
2772 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8168cp_3()
2775 	RTL_W8(tp, DBG_REG, 0x20);  in rtl_hw_start_8168cp_3()
2778 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)  in rtl_hw_start_8168c_1()  argument
2786 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168c_1()
2788 	RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);  in rtl_hw_start_8168c_1()
2790 	rtl_ephy_init(tp, e_info_8168c_1);  in rtl_hw_start_8168c_1()
2792 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168c_1()
2795 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)  in rtl_hw_start_8168c_2()  argument
2802 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168c_2()
2804 	rtl_ephy_init(tp, e_info_8168c_2);  in rtl_hw_start_8168c_2()
2806 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168c_2()
2809 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)  in rtl_hw_start_8168c_3()  argument
2811 	rtl_hw_start_8168c_2(tp);  in rtl_hw_start_8168c_3()
2814 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)  in rtl_hw_start_8168c_4()  argument
2816 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168c_4()
2818 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168c_4()
2821 static void rtl_hw_start_8168d(struct rtl8169_private *tp)  in rtl_hw_start_8168d()  argument
2823 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168d()
2825 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168d()
2828 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)  in rtl_hw_start_8168d_4()  argument
2837 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168d_4()
2839 	rtl_ephy_init(tp, e_info_8168d_4);  in rtl_hw_start_8168d_4()
2841 	rtl_enable_clock_request(tp);  in rtl_hw_start_8168d_4()
2844 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)  in rtl_hw_start_8168e_1()  argument
2862 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168e_1()
2864 	rtl_ephy_init(tp, e_info_8168e_1);  in rtl_hw_start_8168e_1()
2866 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168e_1()
2869 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);  in rtl_hw_start_8168e_1()
2870 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);  in rtl_hw_start_8168e_1()
2872 	RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);  in rtl_hw_start_8168e_1()
2875 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)  in rtl_hw_start_8168e_2()  argument
2884 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168e_2()
2886 	rtl_ephy_init(tp, e_info_8168e_2);  in rtl_hw_start_8168e_2()
2888 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168e_2()
2889 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);  in rtl_hw_start_8168e_2()
2890 	rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);  in rtl_hw_start_8168e_2()
2891 	rtl_eri_set_bits(tp, 0x0d4, 0x1f00);  in rtl_hw_start_8168e_2()
2892 	rtl_eri_set_bits(tp, 0x1d0, BIT(1));  in rtl_hw_start_8168e_2()
2893 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168e_2()
2894 	rtl_eri_set_bits(tp, 0x1b0, BIT(4));  in rtl_hw_start_8168e_2()
2895 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);  in rtl_hw_start_8168e_2()
2896 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);  in rtl_hw_start_8168e_2()
2898 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168e_2()
2900 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_start_8168e_2()
2902 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168e_2()
2904 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);  in rtl_hw_start_8168e_2()
2905 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);  in rtl_hw_start_8168e_2()
2906 	RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);  in rtl_hw_start_8168e_2()
2908 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8168e_2()
2911 static void rtl_hw_start_8168f(struct rtl8169_private *tp)  in rtl_hw_start_8168f()  argument
2913 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168f()
2915 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168f()
2916 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);  in rtl_hw_start_8168f()
2917 	rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);  in rtl_hw_start_8168f()
2918 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168f()
2919 	rtl_eri_set_bits(tp, 0x1b0, BIT(4));  in rtl_hw_start_8168f()
2920 	rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));  in rtl_hw_start_8168f()
2921 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);  in rtl_hw_start_8168f()
2922 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);  in rtl_hw_start_8168f()
2924 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168f()
2926 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_start_8168f()
2927 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);  in rtl_hw_start_8168f()
2928 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);  in rtl_hw_start_8168f()
2929 	RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);  in rtl_hw_start_8168f()
2931 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168f()
2934 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)  in rtl_hw_start_8168f_1()  argument
2945 	rtl_hw_start_8168f(tp);  in rtl_hw_start_8168f_1()
2947 	rtl_ephy_init(tp, e_info_8168f_1);  in rtl_hw_start_8168f_1()
2949 	rtl_eri_set_bits(tp, 0x0d4, 0x1f00);  in rtl_hw_start_8168f_1()
2952 static void rtl_hw_start_8411(struct rtl8169_private *tp)  in rtl_hw_start_8411()  argument
2962 	rtl_hw_start_8168f(tp);  in rtl_hw_start_8411()
2963 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8411()
2965 	rtl_ephy_init(tp, e_info_8168f_1);  in rtl_hw_start_8411()
2967 	rtl_eri_set_bits(tp, 0x0d4, 0x0c00);  in rtl_hw_start_8411()
2970 static void rtl_hw_start_8168g(struct rtl8169_private *tp)  in rtl_hw_start_8168g()  argument
2972 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8168g()
2973 	rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);  in rtl_hw_start_8168g()
2975 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168g()
2977 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168g()
2978 	rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);  in rtl_hw_start_8168g()
2980 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8168g()
2982 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168g()
2983 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168g()
2984 	rtl_eri_set_bits(tp, 0x0d4, 0x1f80);  in rtl_hw_start_8168g()
2986 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168g()
2988 	rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);  in rtl_hw_start_8168g()
2989 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));  in rtl_hw_start_8168g()
2991 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8168g()
2994 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)  in rtl_hw_start_8168g_1()  argument
3003 	rtl_hw_start_8168g(tp);  in rtl_hw_start_8168g_1()
3006 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8168g_1()
3007 	rtl_ephy_init(tp, e_info_8168g_1);  in rtl_hw_start_8168g_1()
3008 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8168g_1()
3011 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)  in rtl_hw_start_8168g_2()  argument
3025 	rtl_hw_start_8168g(tp);  in rtl_hw_start_8168g_2()
3028 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8168g_2()
3029 	rtl_ephy_init(tp, e_info_8168g_2);  in rtl_hw_start_8168g_2()
3032 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)  in rtl_hw_start_8411_2()  argument
3047 	rtl_hw_start_8168g(tp);  in rtl_hw_start_8411_2()
3050 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8411_2()
3051 	rtl_ephy_init(tp, e_info_8411_2);  in rtl_hw_start_8411_2()
3056 	r8168_mac_ocp_write(tp, 0xFC28, 0x0000);  in rtl_hw_start_8411_2()
3057 	r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);  in rtl_hw_start_8411_2()
3058 	r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);  in rtl_hw_start_8411_2()
3059 	r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);  in rtl_hw_start_8411_2()
3060 	r8168_mac_ocp_write(tp, 0xFC30, 0x0000);  in rtl_hw_start_8411_2()
3061 	r8168_mac_ocp_write(tp, 0xFC32, 0x0000);  in rtl_hw_start_8411_2()
3062 	r8168_mac_ocp_write(tp, 0xFC34, 0x0000);  in rtl_hw_start_8411_2()
3063 	r8168_mac_ocp_write(tp, 0xFC36, 0x0000);  in rtl_hw_start_8411_2()
3065 	r8168_mac_ocp_write(tp, 0xFC26, 0x0000);  in rtl_hw_start_8411_2()
3067 	r8168_mac_ocp_write(tp, 0xF800, 0xE008);  in rtl_hw_start_8411_2()
3068 	r8168_mac_ocp_write(tp, 0xF802, 0xE00A);  in rtl_hw_start_8411_2()
3069 	r8168_mac_ocp_write(tp, 0xF804, 0xE00C);  in rtl_hw_start_8411_2()
3070 	r8168_mac_ocp_write(tp, 0xF806, 0xE00E);  in rtl_hw_start_8411_2()
3071 	r8168_mac_ocp_write(tp, 0xF808, 0xE027);  in rtl_hw_start_8411_2()
3072 	r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);  in rtl_hw_start_8411_2()
3073 	r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);  in rtl_hw_start_8411_2()
3074 	r8168_mac_ocp_write(tp, 0xF80E, 0xE065);  in rtl_hw_start_8411_2()
3075 	r8168_mac_ocp_write(tp, 0xF810, 0xC602);  in rtl_hw_start_8411_2()
3076 	r8168_mac_ocp_write(tp, 0xF812, 0xBE00);  in rtl_hw_start_8411_2()
3077 	r8168_mac_ocp_write(tp, 0xF814, 0x0000);  in rtl_hw_start_8411_2()
3078 	r8168_mac_ocp_write(tp, 0xF816, 0xC502);  in rtl_hw_start_8411_2()
3079 	r8168_mac_ocp_write(tp, 0xF818, 0xBD00);  in rtl_hw_start_8411_2()
3080 	r8168_mac_ocp_write(tp, 0xF81A, 0x074C);  in rtl_hw_start_8411_2()
3081 	r8168_mac_ocp_write(tp, 0xF81C, 0xC302);  in rtl_hw_start_8411_2()
3082 	r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);  in rtl_hw_start_8411_2()
3083 	r8168_mac_ocp_write(tp, 0xF820, 0x080A);  in rtl_hw_start_8411_2()
3084 	r8168_mac_ocp_write(tp, 0xF822, 0x6420);  in rtl_hw_start_8411_2()
3085 	r8168_mac_ocp_write(tp, 0xF824, 0x48C2);  in rtl_hw_start_8411_2()
3086 	r8168_mac_ocp_write(tp, 0xF826, 0x8C20);  in rtl_hw_start_8411_2()
3087 	r8168_mac_ocp_write(tp, 0xF828, 0xC516);  in rtl_hw_start_8411_2()
3088 	r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);  in rtl_hw_start_8411_2()
3089 	r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);  in rtl_hw_start_8411_2()
3090 	r8168_mac_ocp_write(tp, 0xF82E, 0xF009);  in rtl_hw_start_8411_2()
3091 	r8168_mac_ocp_write(tp, 0xF830, 0x74A2);  in rtl_hw_start_8411_2()
3092 	r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);  in rtl_hw_start_8411_2()
3093 	r8168_mac_ocp_write(tp, 0xF834, 0x74A0);  in rtl_hw_start_8411_2()
3094 	r8168_mac_ocp_write(tp, 0xF836, 0xC50E);  in rtl_hw_start_8411_2()
3095 	r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);  in rtl_hw_start_8411_2()
3096 	r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);  in rtl_hw_start_8411_2()
3097 	r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);  in rtl_hw_start_8411_2()
3098 	r8168_mac_ocp_write(tp, 0xF83E, 0xE006);  in rtl_hw_start_8411_2()
3099 	r8168_mac_ocp_write(tp, 0xF840, 0x74F8);  in rtl_hw_start_8411_2()
3100 	r8168_mac_ocp_write(tp, 0xF842, 0x48C4);  in rtl_hw_start_8411_2()
3101 	r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);  in rtl_hw_start_8411_2()
3102 	r8168_mac_ocp_write(tp, 0xF846, 0xC404);  in rtl_hw_start_8411_2()
3103 	r8168_mac_ocp_write(tp, 0xF848, 0xBC00);  in rtl_hw_start_8411_2()
3104 	r8168_mac_ocp_write(tp, 0xF84A, 0xC403);  in rtl_hw_start_8411_2()
3105 	r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);  in rtl_hw_start_8411_2()
3106 	r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);  in rtl_hw_start_8411_2()
3107 	r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);  in rtl_hw_start_8411_2()
3108 	r8168_mac_ocp_write(tp, 0xF852, 0xE434);  in rtl_hw_start_8411_2()
3109 	r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);  in rtl_hw_start_8411_2()
3110 	r8168_mac_ocp_write(tp, 0xF856, 0x49D9);  in rtl_hw_start_8411_2()
3111 	r8168_mac_ocp_write(tp, 0xF858, 0xF01F);  in rtl_hw_start_8411_2()
3112 	r8168_mac_ocp_write(tp, 0xF85A, 0xC526);  in rtl_hw_start_8411_2()
3113 	r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);  in rtl_hw_start_8411_2()
3114 	r8168_mac_ocp_write(tp, 0xF85E, 0x1400);  in rtl_hw_start_8411_2()
3115 	r8168_mac_ocp_write(tp, 0xF860, 0xF007);  in rtl_hw_start_8411_2()
3116 	r8168_mac_ocp_write(tp, 0xF862, 0x0C01);  in rtl_hw_start_8411_2()
3117 	r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);  in rtl_hw_start_8411_2()
3118 	r8168_mac_ocp_write(tp, 0xF866, 0x1C15);  in rtl_hw_start_8411_2()
3119 	r8168_mac_ocp_write(tp, 0xF868, 0xC51B);  in rtl_hw_start_8411_2()
3120 	r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);  in rtl_hw_start_8411_2()
3121 	r8168_mac_ocp_write(tp, 0xF86C, 0xE013);  in rtl_hw_start_8411_2()
3122 	r8168_mac_ocp_write(tp, 0xF86E, 0xC519);  in rtl_hw_start_8411_2()
3123 	r8168_mac_ocp_write(tp, 0xF870, 0x74A0);  in rtl_hw_start_8411_2()
3124 	r8168_mac_ocp_write(tp, 0xF872, 0x48C4);  in rtl_hw_start_8411_2()
3125 	r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);  in rtl_hw_start_8411_2()
3126 	r8168_mac_ocp_write(tp, 0xF876, 0xC516);  in rtl_hw_start_8411_2()
3127 	r8168_mac_ocp_write(tp, 0xF878, 0x74A4);  in rtl_hw_start_8411_2()
3128 	r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);  in rtl_hw_start_8411_2()
3129 	r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);  in rtl_hw_start_8411_2()
3130 	r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);  in rtl_hw_start_8411_2()
3131 	r8168_mac_ocp_write(tp, 0xF880, 0xC512);  in rtl_hw_start_8411_2()
3132 	r8168_mac_ocp_write(tp, 0xF882, 0x1B00);  in rtl_hw_start_8411_2()
3133 	r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);  in rtl_hw_start_8411_2()
3134 	r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);  in rtl_hw_start_8411_2()
3135 	r8168_mac_ocp_write(tp, 0xF888, 0x483F);  in rtl_hw_start_8411_2()
3136 	r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);  in rtl_hw_start_8411_2()
3137 	r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);  in rtl_hw_start_8411_2()
3138 	r8168_mac_ocp_write(tp, 0xF88E, 0xC508);  in rtl_hw_start_8411_2()
3139 	r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);  in rtl_hw_start_8411_2()
3140 	r8168_mac_ocp_write(tp, 0xF892, 0xC505);  in rtl_hw_start_8411_2()
3141 	r8168_mac_ocp_write(tp, 0xF894, 0xBD00);  in rtl_hw_start_8411_2()
3142 	r8168_mac_ocp_write(tp, 0xF896, 0xC502);  in rtl_hw_start_8411_2()
3143 	r8168_mac_ocp_write(tp, 0xF898, 0xBD00);  in rtl_hw_start_8411_2()
3144 	r8168_mac_ocp_write(tp, 0xF89A, 0x0300);  in rtl_hw_start_8411_2()
3145 	r8168_mac_ocp_write(tp, 0xF89C, 0x051E);  in rtl_hw_start_8411_2()
3146 	r8168_mac_ocp_write(tp, 0xF89E, 0xE434);  in rtl_hw_start_8411_2()
3147 	r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);  in rtl_hw_start_8411_2()
3148 	r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);  in rtl_hw_start_8411_2()
3149 	r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);  in rtl_hw_start_8411_2()
3150 	r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);  in rtl_hw_start_8411_2()
3151 	r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);  in rtl_hw_start_8411_2()
3152 	r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);  in rtl_hw_start_8411_2()
3153 	r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);  in rtl_hw_start_8411_2()
3154 	r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);  in rtl_hw_start_8411_2()
3155 	r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);  in rtl_hw_start_8411_2()
3156 	r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);  in rtl_hw_start_8411_2()
3157 	r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);  in rtl_hw_start_8411_2()
3158 	r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);  in rtl_hw_start_8411_2()
3159 	r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);  in rtl_hw_start_8411_2()
3160 	r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);  in rtl_hw_start_8411_2()
3161 	r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);  in rtl_hw_start_8411_2()
3162 	r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);  in rtl_hw_start_8411_2()
3163 	r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);  in rtl_hw_start_8411_2()
3164 	r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);  in rtl_hw_start_8411_2()
3165 	r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);  in rtl_hw_start_8411_2()
3166 	r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);  in rtl_hw_start_8411_2()
3167 	r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);  in rtl_hw_start_8411_2()
3168 	r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);  in rtl_hw_start_8411_2()
3169 	r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);  in rtl_hw_start_8411_2()
3170 	r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);  in rtl_hw_start_8411_2()
3171 	r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);  in rtl_hw_start_8411_2()
3172 	r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);  in rtl_hw_start_8411_2()
3173 	r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);  in rtl_hw_start_8411_2()
3174 	r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);  in rtl_hw_start_8411_2()
3175 	r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);  in rtl_hw_start_8411_2()
3176 	r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);  in rtl_hw_start_8411_2()
3177 	r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);  in rtl_hw_start_8411_2()
3179 	r8168_mac_ocp_write(tp, 0xFC26, 0x8000);  in rtl_hw_start_8411_2()
3181 	r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);  in rtl_hw_start_8411_2()
3182 	r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);  in rtl_hw_start_8411_2()
3183 	r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);  in rtl_hw_start_8411_2()
3184 	r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);  in rtl_hw_start_8411_2()
3185 	r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);  in rtl_hw_start_8411_2()
3186 	r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);  in rtl_hw_start_8411_2()
3187 	r8168_mac_ocp_write(tp, 0xFC36, 0x012D);  in rtl_hw_start_8411_2()
3189 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8411_2()
3192 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)  in rtl_hw_start_8168h_1()  argument
3205 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8168h_1()
3206 	rtl_ephy_init(tp, e_info_8168h_1);  in rtl_hw_start_8168h_1()
3208 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8168h_1()
3209 	rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);  in rtl_hw_start_8168h_1()
3211 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168h_1()
3213 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168h_1()
3215 	rtl_eri_set_bits(tp, 0xd4, 0x1f00);  in rtl_hw_start_8168h_1()
3216 	rtl_eri_set_bits(tp, 0xdc, 0x001c);  in rtl_hw_start_8168h_1()
3218 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);  in rtl_hw_start_8168h_1()
3220 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8168h_1()
3222 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168h_1()
3223 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168h_1()
3225 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168h_1()
3227 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8168h_1()
3228 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8168h_1()
3230 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);  in rtl_hw_start_8168h_1()
3232 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));  in rtl_hw_start_8168h_1()
3234 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8168h_1()
3236 	rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;  in rtl_hw_start_8168h_1()
3242 		r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);  in rtl_hw_start_8168h_1()
3245 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);  in rtl_hw_start_8168h_1()
3246 	r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);  in rtl_hw_start_8168h_1()
3247 	r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);  in rtl_hw_start_8168h_1()
3248 	r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);  in rtl_hw_start_8168h_1()
3250 	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);  in rtl_hw_start_8168h_1()
3251 	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);  in rtl_hw_start_8168h_1()
3252 	r8168_mac_ocp_write(tp, 0xc094, 0x0000);  in rtl_hw_start_8168h_1()
3253 	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);  in rtl_hw_start_8168h_1()
3255 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8168h_1()
3258 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)  in rtl_hw_start_8168ep()  argument
3260 	rtl8168ep_stop_cmac(tp);  in rtl_hw_start_8168ep()
3262 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8168ep()
3263 	rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);  in rtl_hw_start_8168ep()
3265 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168ep()
3267 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168ep()
3269 	rtl_eri_set_bits(tp, 0xd4, 0x1f80);  in rtl_hw_start_8168ep()
3271 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);  in rtl_hw_start_8168ep()
3273 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8168ep()
3275 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168ep()
3276 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168ep()
3278 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168ep()
3280 	rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);  in rtl_hw_start_8168ep()
3282 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);  in rtl_hw_start_8168ep()
3284 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8168ep()
3287 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)  in rtl_hw_start_8168ep_1()  argument
3298 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8168ep_1()
3299 	rtl_ephy_init(tp, e_info_8168ep_1);  in rtl_hw_start_8168ep_1()
3301 	rtl_hw_start_8168ep(tp);  in rtl_hw_start_8168ep_1()
3303 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8168ep_1()
3306 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)  in rtl_hw_start_8168ep_2()  argument
3315 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8168ep_2()
3316 	rtl_ephy_init(tp, e_info_8168ep_2);  in rtl_hw_start_8168ep_2()
3318 	rtl_hw_start_8168ep(tp);  in rtl_hw_start_8168ep_2()
3320 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8168ep_2()
3321 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8168ep_2()
3323 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8168ep_2()
3326 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)  in rtl_hw_start_8168ep_3()  argument
3336 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8168ep_3()
3337 	rtl_ephy_init(tp, e_info_8168ep_3);  in rtl_hw_start_8168ep_3()
3339 	rtl_hw_start_8168ep(tp);  in rtl_hw_start_8168ep_3()
3341 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8168ep_3()
3342 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8168ep_3()
3344 	r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);  in rtl_hw_start_8168ep_3()
3345 	r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);  in rtl_hw_start_8168ep_3()
3346 	r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);  in rtl_hw_start_8168ep_3()
3348 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8168ep_3()
3351 static void rtl_hw_start_8117(struct rtl8169_private *tp)  in rtl_hw_start_8117()  argument
3359 	rtl8168ep_stop_cmac(tp);  in rtl_hw_start_8117()
3362 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8117()
3363 	rtl_ephy_init(tp, e_info_8117);  in rtl_hw_start_8117()
3365 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8117()
3366 	rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);  in rtl_hw_start_8117()
3368 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8117()
3370 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8117()
3372 	rtl_eri_set_bits(tp, 0xd4, 0x1f90);  in rtl_hw_start_8117()
3374 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);  in rtl_hw_start_8117()
3376 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8117()
3378 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8117()
3379 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8117()
3381 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8117()
3383 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8117()
3384 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8117()
3386 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);  in rtl_hw_start_8117()
3388 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));  in rtl_hw_start_8117()
3390 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8117()
3392 	rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;  in rtl_hw_start_8117()
3397 		r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);  in rtl_hw_start_8117()
3400 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);  in rtl_hw_start_8117()
3401 	r8168_mac_ocp_write(tp, 0xea80, 0x0003);  in rtl_hw_start_8117()
3402 	r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);  in rtl_hw_start_8117()
3403 	r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);  in rtl_hw_start_8117()
3405 	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);  in rtl_hw_start_8117()
3406 	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);  in rtl_hw_start_8117()
3407 	r8168_mac_ocp_write(tp, 0xc094, 0x0000);  in rtl_hw_start_8117()
3408 	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);  in rtl_hw_start_8117()
3411 	r8169_apply_firmware(tp);  in rtl_hw_start_8117()
3413 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8117()
3416 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)  in rtl_hw_start_8102e_1()  argument
3430 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8102e_1()
3432 	RTL_W8(tp, DBG_REG, FIX_NAK_1);  in rtl_hw_start_8102e_1()
3434 	RTL_W8(tp, Config1,  in rtl_hw_start_8102e_1()
3436 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8102e_1()
3438 	cfg1 = RTL_R8(tp, Config1);  in rtl_hw_start_8102e_1()
3440 		RTL_W8(tp, Config1, cfg1 & ~LEDS0);  in rtl_hw_start_8102e_1()
3442 	rtl_ephy_init(tp, e_info_8102e_1);  in rtl_hw_start_8102e_1()
3445 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)  in rtl_hw_start_8102e_2()  argument
3447 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8102e_2()
3449 	RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);  in rtl_hw_start_8102e_2()
3450 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8102e_2()
3453 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)  in rtl_hw_start_8102e_3()  argument
3455 	rtl_hw_start_8102e_2(tp);  in rtl_hw_start_8102e_3()
3457 	rtl_ephy_write(tp, 0x03, 0xc2f9);  in rtl_hw_start_8102e_3()
3460 static void rtl_hw_start_8401(struct rtl8169_private *tp)  in rtl_hw_start_8401()  argument
3469 	rtl_ephy_init(tp, e_info_8401);  in rtl_hw_start_8401()
3470 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8401()
3473 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)  in rtl_hw_start_8105e_1()  argument
3487 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8105e_1()
3490 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);  in rtl_hw_start_8105e_1()
3492 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);  in rtl_hw_start_8105e_1()
3493 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);  in rtl_hw_start_8105e_1()
3495 	rtl_ephy_init(tp, e_info_8105e_1);  in rtl_hw_start_8105e_1()
3497 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8105e_1()
3500 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)  in rtl_hw_start_8105e_2()  argument
3502 	rtl_hw_start_8105e_1(tp);  in rtl_hw_start_8105e_2()
3503 	rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);  in rtl_hw_start_8105e_2()
3506 static void rtl_hw_start_8402(struct rtl8169_private *tp)  in rtl_hw_start_8402()  argument
3513 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8402()
3516 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8402()
3518 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_start_8402()
3520 	rtl_ephy_init(tp, e_info_8402);  in rtl_hw_start_8402()
3522 	rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);  in rtl_hw_start_8402()
3523 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8402()
3524 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8402()
3525 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8402()
3526 	rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);  in rtl_hw_start_8402()
3529 	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8402()
3531 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8402()
3534 static void rtl_hw_start_8106(struct rtl8169_private *tp)  in rtl_hw_start_8106()  argument
3536 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8106()
3539 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8106()
3541 	RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);  in rtl_hw_start_8106()
3542 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);  in rtl_hw_start_8106()
3543 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8106()
3545 	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8106()
3548 	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8106()
3550 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8106()
3551 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8106()
3556 	return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);  in DECLARE_RTL_COND()
3559 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)  in rtl_hw_start_8125_common()  argument
3561 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8125_common()
3563 	RTL_W16(tp, 0x382, 0x221b);  in rtl_hw_start_8125_common()
3564 	RTL_W8(tp, 0x4500, 0);  in rtl_hw_start_8125_common()
3565 	RTL_W16(tp, 0x4800, 0);  in rtl_hw_start_8125_common()
3568 	r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);  in rtl_hw_start_8125_common()
3570 	RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);  in rtl_hw_start_8125_common()
3572 	r8168_mac_ocp_write(tp, 0xc140, 0xffff);  in rtl_hw_start_8125_common()
3573 	r8168_mac_ocp_write(tp, 0xc142, 0xffff);  in rtl_hw_start_8125_common()
3575 	r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);  in rtl_hw_start_8125_common()
3576 	r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);  in rtl_hw_start_8125_common()
3577 	r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);  in rtl_hw_start_8125_common()
3580 	r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);  in rtl_hw_start_8125_common()
3582 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)  in rtl_hw_start_8125_common()
3583 		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);  in rtl_hw_start_8125_common()
3585 		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);  in rtl_hw_start_8125_common()
3587 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)  in rtl_hw_start_8125_common()
3588 		r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);  in rtl_hw_start_8125_common()
3590 		r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);  in rtl_hw_start_8125_common()
3592 	r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);  in rtl_hw_start_8125_common()
3593 	r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);  in rtl_hw_start_8125_common()
3594 	r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);  in rtl_hw_start_8125_common()
3595 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);  in rtl_hw_start_8125_common()
3596 	r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);  in rtl_hw_start_8125_common()
3597 	r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);  in rtl_hw_start_8125_common()
3598 	r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);  in rtl_hw_start_8125_common()
3599 	r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);  in rtl_hw_start_8125_common()
3600 	r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);  in rtl_hw_start_8125_common()
3601 	r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);  in rtl_hw_start_8125_common()
3603 	r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);  in rtl_hw_start_8125_common()
3604 	r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);  in rtl_hw_start_8125_common()
3606 	r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);  in rtl_hw_start_8125_common()
3607 	RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);  in rtl_hw_start_8125_common()
3609 	r8168_mac_ocp_write(tp, 0xe098, 0xc302);  in rtl_hw_start_8125_common()
3611 	rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);  in rtl_hw_start_8125_common()
3613 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)  in rtl_hw_start_8125_common()
3614 		rtl8125b_config_eee_mac(tp);  in rtl_hw_start_8125_common()
3616 		rtl8125a_config_eee_mac(tp);  in rtl_hw_start_8125_common()
3618 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_hw_start_8125_common()
3622 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)  in rtl_hw_start_8125a_1()  argument
3652 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8125a_1()
3655 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8125a_1()
3656 	rtl_ephy_init(tp, e_info_8125a_1);  in rtl_hw_start_8125a_1()
3658 	rtl_hw_start_8125_common(tp);  in rtl_hw_start_8125a_1()
3659 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8125a_1()
3662 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)  in rtl_hw_start_8125a_2()  argument
3680 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8125a_2()
3683 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8125a_2()
3684 	rtl_ephy_init(tp, e_info_8125a_2);  in rtl_hw_start_8125a_2()
3686 	rtl_hw_start_8125_common(tp);  in rtl_hw_start_8125a_2()
3687 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8125a_2()
3690 static void rtl_hw_start_8125b(struct rtl8169_private *tp)  in rtl_hw_start_8125b()  argument
3701 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8125b()
3702 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start_8125b()
3704 	rtl_ephy_init(tp, e_info_8125b);  in rtl_hw_start_8125b()
3705 	rtl_hw_start_8125_common(tp);  in rtl_hw_start_8125b()
3707 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start_8125b()
3710 static void rtl_hw_config(struct rtl8169_private *tp)  in rtl_hw_config()  argument
3763 	if (hw_configs[tp->mac_version])  in rtl_hw_config()
3764 		hw_configs[tp->mac_version](tp);  in rtl_hw_config()
3767 static void rtl_hw_start_8125(struct rtl8169_private *tp)  in rtl_hw_start_8125()  argument
3773 		RTL_W32(tp, i, 0);  in rtl_hw_start_8125()
3775 	rtl_hw_config(tp);  in rtl_hw_start_8125()
3778 static void rtl_hw_start_8168(struct rtl8169_private *tp)  in rtl_hw_start_8168()  argument
3780 	if (rtl_is_8168evl_up(tp))  in rtl_hw_start_8168()
3781 		RTL_W8(tp, MaxTxPacketSize, EarlySize);  in rtl_hw_start_8168()
3783 		RTL_W8(tp, MaxTxPacketSize, TxPacketMax);  in rtl_hw_start_8168()
3785 	rtl_hw_config(tp);  in rtl_hw_start_8168()
3788 	RTL_W16(tp, IntrMitigate, 0x0000);  in rtl_hw_start_8168()
3791 static void rtl_hw_start_8169(struct rtl8169_private *tp)  in rtl_hw_start_8169()  argument
3793 	RTL_W8(tp, EarlyTxThres, NoEarlyTx);  in rtl_hw_start_8169()
3795 	tp->cp_cmd |= PCIMulRW;  in rtl_hw_start_8169()
3797 	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||  in rtl_hw_start_8169()
3798 	    tp->mac_version == RTL_GIGA_MAC_VER_03)  in rtl_hw_start_8169()
3799 		tp->cp_cmd |= EnAnaPLL;  in rtl_hw_start_8169()
3801 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl_hw_start_8169()
3803 	rtl8169_set_magic_reg(tp);  in rtl_hw_start_8169()
3806 	RTL_W16(tp, IntrMitigate, 0x0000);  in rtl_hw_start_8169()
3809 static void rtl_hw_start(struct  rtl8169_private *tp)  in rtl_hw_start()  argument
3811 	rtl_unlock_config_regs(tp);  in rtl_hw_start()
3813 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl_hw_start()
3815 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)  in rtl_hw_start()
3816 		rtl_hw_start_8169(tp);  in rtl_hw_start()
3817 	else if (rtl_is_8125(tp))  in rtl_hw_start()
3818 		rtl_hw_start_8125(tp);  in rtl_hw_start()
3820 		rtl_hw_start_8168(tp);  in rtl_hw_start()
3822 	rtl_set_rx_max_size(tp);  in rtl_hw_start()
3823 	rtl_set_rx_tx_desc_registers(tp);  in rtl_hw_start()
3824 	rtl_lock_config_regs(tp);  in rtl_hw_start()
3826 	rtl_jumbo_config(tp);  in rtl_hw_start()
3829 	rtl_pci_commit(tp);  in rtl_hw_start()
3831 	RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);  in rtl_hw_start()
3832 	rtl_init_rxcfg(tp);  in rtl_hw_start()
3833 	rtl_set_tx_config_registers(tp);  in rtl_hw_start()
3834 	rtl_set_rx_config_features(tp, tp->dev->features);  in rtl_hw_start()
3835 	rtl_set_rx_mode(tp->dev);  in rtl_hw_start()
3836 	rtl_irq_enable(tp);  in rtl_hw_start()
3841 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_change_mtu()  local
3845 	rtl_jumbo_config(tp);  in rtl8169_change_mtu()
3847 	switch (tp->mac_version) {  in rtl8169_change_mtu()
3850 		rtl8125_set_eee_txidle_timer(tp);  in rtl8169_change_mtu()
3869 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,  in rtl8169_alloc_rx_data()  argument
3872 	struct device *d = tp_to_dev(tp);  in rtl8169_alloc_rx_data()
3883 		netdev_err(tp->dev, "Failed to map RX DMA!\n");  in rtl8169_alloc_rx_data()
3894 static void rtl8169_rx_clear(struct rtl8169_private *tp)  in rtl8169_rx_clear()  argument
3898 	for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {  in rtl8169_rx_clear()
3899 		dma_unmap_page(tp_to_dev(tp),  in rtl8169_rx_clear()
3900 			       le64_to_cpu(tp->RxDescArray[i].addr),  in rtl8169_rx_clear()
3902 		__free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));  in rtl8169_rx_clear()
3903 		tp->Rx_databuff[i] = NULL;  in rtl8169_rx_clear()
3904 		tp->RxDescArray[i].addr = 0;  in rtl8169_rx_clear()
3905 		tp->RxDescArray[i].opts1 = 0;  in rtl8169_rx_clear()
3909 static int rtl8169_rx_fill(struct rtl8169_private *tp)  in rtl8169_rx_fill()  argument
3916 		data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);  in rtl8169_rx_fill()
3918 			rtl8169_rx_clear(tp);  in rtl8169_rx_fill()
3921 		tp->Rx_databuff[i] = data;  in rtl8169_rx_fill()
3925 	tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);  in rtl8169_rx_fill()
3930 static int rtl8169_init_ring(struct rtl8169_private *tp)  in rtl8169_init_ring()  argument
3932 	rtl8169_init_ring_indexes(tp);  in rtl8169_init_ring()
3934 	memset(tp->tx_skb, 0, sizeof(tp->tx_skb));  in rtl8169_init_ring()
3935 	memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));  in rtl8169_init_ring()
3937 	return rtl8169_rx_fill(tp);  in rtl8169_init_ring()
3940 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)  in rtl8169_unmap_tx_skb()  argument
3942 	struct ring_info *tx_skb = tp->tx_skb + entry;  in rtl8169_unmap_tx_skb()
3943 	struct TxDesc *desc = tp->TxDescArray + entry;  in rtl8169_unmap_tx_skb()
3945 	dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,  in rtl8169_unmap_tx_skb()
3951 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,  in rtl8169_tx_clear_range()  argument
3958 		struct ring_info *tx_skb = tp->tx_skb + entry;  in rtl8169_tx_clear_range()
3964 			rtl8169_unmap_tx_skb(tp, entry);  in rtl8169_tx_clear_range()
3971 static void rtl8169_tx_clear(struct rtl8169_private *tp)  in rtl8169_tx_clear()  argument
3973 	rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);  in rtl8169_tx_clear()
3974 	netdev_reset_queue(tp->dev);  in rtl8169_tx_clear()
3977 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)  in rtl8169_cleanup()  argument
3979 	napi_disable(&tp->napi);  in rtl8169_cleanup()
3985 	rtl8169_irq_mask_and_ack(tp);  in rtl8169_cleanup()
3987 	rtl_rx_close(tp);  in rtl8169_cleanup()
3989 	if (going_down && tp->dev->wol_enabled)  in rtl8169_cleanup()
3992 	switch (tp->mac_version) {  in rtl8169_cleanup()
3996 		rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);  in rtl8169_cleanup()
3999 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);  in rtl8169_cleanup()
4000 		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);  in rtl8169_cleanup()
4003 		rtl_enable_rxdvgate(tp);  in rtl8169_cleanup()
4007 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);  in rtl8169_cleanup()
4012 	rtl_hw_reset(tp);  in rtl8169_cleanup()
4014 	rtl8169_tx_clear(tp);  in rtl8169_cleanup()
4015 	rtl8169_init_ring_indexes(tp);  in rtl8169_cleanup()
4018 static void rtl_reset_work(struct rtl8169_private *tp)  in rtl_reset_work()  argument
4022 	netif_stop_queue(tp->dev);  in rtl_reset_work()
4024 	rtl8169_cleanup(tp, false);  in rtl_reset_work()
4027 		rtl8169_mark_to_asic(tp->RxDescArray + i);  in rtl_reset_work()
4029 	napi_enable(&tp->napi);  in rtl_reset_work()
4030 	rtl_hw_start(tp);  in rtl_reset_work()
4035 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_tx_timeout()  local
4037 	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);  in rtl8169_tx_timeout()
4040 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,  in rtl8169_tx_map()  argument
4043 	struct TxDesc *txd = tp->TxDescArray + entry;  in rtl8169_tx_map()
4044 	struct device *d = tp_to_dev(tp);  in rtl8169_tx_map()
4053 			netdev_err(tp->dev, "Failed to map TX data!\n");  in rtl8169_tx_map()
4067 	tp->tx_skb[entry].len = len;  in rtl8169_tx_map()
4072 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,  in rtl8169_xmit_frags()  argument
4085 		if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))  in rtl8169_xmit_frags()
4092 	rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);  in rtl8169_xmit_frags()
4117 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,  in rtl8125_quirk_udp_padto()  argument
4122 	if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&  in rtl8125_quirk_udp_padto()
4144 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,  in rtl_quirk_packet_padto()  argument
4149 	padto = rtl8125_quirk_udp_padto(tp, skb);  in rtl_quirk_packet_padto()
4151 	switch (tp->mac_version) {  in rtl_quirk_packet_padto()
4183 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,  in rtl8169_tso_csum_v2()  argument
4232 		unsigned int padto = rtl_quirk_packet_padto(tp, skb);  in rtl8169_tso_csum_v2()
4241 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,  in rtl_tx_slots_avail()  argument
4244 	unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;  in rtl_tx_slots_avail()
4251 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)  in rtl_chip_supports_csum_v2()  argument
4253 	switch (tp->mac_version) {  in rtl_chip_supports_csum_v2()
4262 static void rtl8169_doorbell(struct rtl8169_private *tp)  in rtl8169_doorbell()  argument
4264 	if (rtl_is_8125(tp))  in rtl8169_doorbell()
4265 		RTL_W16(tp, TxPoll_8125, BIT(0));  in rtl8169_doorbell()
4267 		RTL_W8(tp, TxPoll, NPQ);  in rtl8169_doorbell()
4274 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_start_xmit()  local
4275 	unsigned int entry = tp->cur_tx % NUM_TX_DESC;  in rtl8169_start_xmit()
4280 	txd_first = tp->TxDescArray + entry;  in rtl8169_start_xmit()
4282 	if (unlikely(!rtl_tx_slots_avail(tp, frags))) {  in rtl8169_start_xmit()
4294 	if (!rtl_chip_supports_csum_v2(tp))  in rtl8169_start_xmit()
4296 	else if (!rtl8169_tso_csum_v2(tp, skb, opts))  in rtl8169_start_xmit()
4299 	if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,  in rtl8169_start_xmit()
4304 		if (rtl8169_xmit_frags(tp, skb, opts, entry))  in rtl8169_start_xmit()
4309 	txd_last = tp->TxDescArray + entry;  in rtl8169_start_xmit()
4311 	tp->tx_skb[entry].skb = skb;  in rtl8169_start_xmit()
4325 	tp->cur_tx += frags + 1;  in rtl8169_start_xmit()
4327 	stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);  in rtl8169_start_xmit()
4338 		rtl8169_doorbell(tp);  in rtl8169_start_xmit()
4349 		if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))  in rtl8169_start_xmit()
4356 	rtl8169_unmap_tx_skb(tp, entry);  in rtl8169_start_xmit()
4403 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_features_check()  local
4406 		if (tp->mac_version == RTL_GIGA_MAC_VER_34)  in rtl8169_features_check()
4410 		    rtl_chip_supports_csum_v2(tp))  in rtl8169_features_check()
4417 		if (rtl_quirk_packet_padto(tp, skb))  in rtl8169_features_check()
4421 		    rtl_chip_supports_csum_v2(tp))  in rtl8169_features_check()
4430 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_pcierr_interrupt()  local
4431 	struct pci_dev *pdev = tp->pci_dev;  in rtl8169_pcierr_interrupt()
4457 	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);  in rtl8169_pcierr_interrupt()
4460 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,  in rtl_tx()  argument
4465 	dirty_tx = tp->dirty_tx;  in rtl_tx()
4468 	for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) {  in rtl_tx()
4470 		struct sk_buff *skb = tp->tx_skb[entry].skb;  in rtl_tx()
4473 		status = le32_to_cpu(tp->TxDescArray[entry].opts1);  in rtl_tx()
4477 		rtl8169_unmap_tx_skb(tp, entry);  in rtl_tx()
4487 	if (tp->dirty_tx != dirty_tx) {  in rtl_tx()
4490 		rtl_inc_priv_stats(&tp->tx_stats, pkts_compl, bytes_compl);  in rtl_tx()
4492 		tp->dirty_tx = dirty_tx;  in rtl_tx()
4502 		    rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {  in rtl_tx()
4511 		if (tp->cur_tx != dirty_tx)  in rtl_tx()
4512 			rtl8169_doorbell(tp);  in rtl_tx()
4532 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)  in rtl_rx()  argument
4535 	struct device *d = tp_to_dev(tp);  in rtl_rx()
4537 	cur_rx = tp->cur_rx;  in rtl_rx()
4541 		struct RxDesc *desc = tp->RxDescArray + entry;  in rtl_rx()
4586 		skb = napi_alloc_skb(&tp->napi, pkt_size);  in rtl_rx()
4593 		rx_buf = page_address(tp->Rx_databuff[entry]);  in rtl_rx()
4610 		napi_gro_receive(&tp->napi, skb);  in rtl_rx()
4612 		rtl_inc_priv_stats(&tp->rx_stats, 1, pkt_size);  in rtl_rx()
4617 	count = cur_rx - tp->cur_rx;  in rtl_rx()
4618 	tp->cur_rx = cur_rx;  in rtl_rx()
4625 	struct rtl8169_private *tp = dev_instance;  in rtl8169_interrupt()  local
4626 	u32 status = rtl_get_events(tp);  in rtl8169_interrupt()
4628 	if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))  in rtl8169_interrupt()
4632 		rtl8169_pcierr_interrupt(tp->dev);  in rtl8169_interrupt()
4637 		phy_mac_interrupt(tp->phydev);  in rtl8169_interrupt()
4640 	    tp->mac_version == RTL_GIGA_MAC_VER_11)) {  in rtl8169_interrupt()
4641 		netif_stop_queue(tp->dev);  in rtl8169_interrupt()
4642 		rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);  in rtl8169_interrupt()
4645 	rtl_irq_disable(tp);  in rtl8169_interrupt()
4646 	napi_schedule(&tp->napi);  in rtl8169_interrupt()
4648 	rtl_ack_events(tp, status);  in rtl8169_interrupt()
4655 	struct rtl8169_private *tp =  in rtl_task()  local
4660 	if (!netif_running(tp->dev) ||  in rtl_task()
4661 	    !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))  in rtl_task()
4664 	if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {  in rtl_task()
4665 		rtl_reset_work(tp);  in rtl_task()
4666 		netif_wake_queue(tp->dev);  in rtl_task()
4674 	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);  in rtl8169_poll()  local
4675 	struct net_device *dev = tp->dev;  in rtl8169_poll()
4678 	work_done = rtl_rx(dev, tp, (u32) budget);  in rtl8169_poll()
4680 	rtl_tx(dev, tp, budget);  in rtl8169_poll()
4683 		rtl_irq_enable(tp);  in rtl8169_poll()
4690 	struct rtl8169_private *tp = netdev_priv(ndev);  in r8169_phylink_handler()  local
4693 		rtl_link_chg_patch(tp);  in r8169_phylink_handler()
4694 		pm_request_resume(&tp->pci_dev->dev);  in r8169_phylink_handler()
4696 		pm_runtime_idle(&tp->pci_dev->dev);  in r8169_phylink_handler()
4700 		phy_print_status(tp->phydev);  in r8169_phylink_handler()
4703 static int r8169_phy_connect(struct rtl8169_private *tp)  in r8169_phy_connect()  argument
4705 	struct phy_device *phydev = tp->phydev;  in r8169_phy_connect()
4709 	phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :  in r8169_phy_connect()
4712 	ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,  in r8169_phy_connect()
4717 	if (!tp->supports_gmii)  in r8169_phy_connect()
4725 static void rtl8169_down(struct rtl8169_private *tp)  in rtl8169_down()  argument
4728 	bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);  in rtl8169_down()
4730 	phy_stop(tp->phydev);  in rtl8169_down()
4732 	rtl8169_update_counters(tp);  in rtl8169_down()
4734 	pci_clear_master(tp->pci_dev);  in rtl8169_down()
4735 	rtl_pci_commit(tp);  in rtl8169_down()
4737 	rtl8169_cleanup(tp, true);  in rtl8169_down()
4739 	rtl_pll_power_down(tp);  in rtl8169_down()
4742 static void rtl8169_up(struct rtl8169_private *tp)  in rtl8169_up()  argument
4744 	pci_set_master(tp->pci_dev);  in rtl8169_up()
4745 	rtl_pll_power_up(tp);  in rtl8169_up()
4746 	rtl8169_init_phy(tp);  in rtl8169_up()
4747 	napi_enable(&tp->napi);  in rtl8169_up()
4748 	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);  in rtl8169_up()
4749 	rtl_reset_work(tp);  in rtl8169_up()
4751 	phy_start(tp->phydev);  in rtl8169_up()
4756 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_close()  local
4757 	struct pci_dev *pdev = tp->pci_dev;  in rtl8169_close()
4762 	rtl8169_down(tp);  in rtl8169_close()
4763 	rtl8169_rx_clear(tp);  in rtl8169_close()
4765 	cancel_work_sync(&tp->wk.work);  in rtl8169_close()
4767 	free_irq(pci_irq_vector(pdev, 0), tp);  in rtl8169_close()
4769 	phy_disconnect(tp->phydev);  in rtl8169_close()
4771 	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,  in rtl8169_close()
4772 			  tp->RxPhyAddr);  in rtl8169_close()
4773 	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,  in rtl8169_close()
4774 			  tp->TxPhyAddr);  in rtl8169_close()
4775 	tp->TxDescArray = NULL;  in rtl8169_close()
4776 	tp->RxDescArray = NULL;  in rtl8169_close()
4786 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_netpoll()  local
4788 	rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);  in rtl8169_netpoll()
4794 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_open()  local
4795 	struct pci_dev *pdev = tp->pci_dev;  in rtl_open()
4804 	tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,  in rtl_open()
4805 					     &tp->TxPhyAddr, GFP_KERNEL);  in rtl_open()
4806 	if (!tp->TxDescArray)  in rtl_open()
4809 	tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,  in rtl_open()
4810 					     &tp->RxPhyAddr, GFP_KERNEL);  in rtl_open()
4811 	if (!tp->RxDescArray)  in rtl_open()
4814 	retval = rtl8169_init_ring(tp);  in rtl_open()
4818 	rtl_request_firmware(tp);  in rtl_open()
4821 			     IRQF_SHARED, dev->name, tp);  in rtl_open()
4825 	retval = r8169_phy_connect(tp);  in rtl_open()
4829 	rtl8169_up(tp);  in rtl_open()
4830 	rtl8169_init_counter_offsets(tp);  in rtl_open()
4838 	free_irq(pci_irq_vector(pdev, 0), tp);  in rtl_open()
4840 	rtl_release_firmware(tp);  in rtl_open()
4841 	rtl8169_rx_clear(tp);  in rtl_open()
4843 	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,  in rtl_open()
4844 			  tp->RxPhyAddr);  in rtl_open()
4845 	tp->RxDescArray = NULL;  in rtl_open()
4847 	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,  in rtl_open()
4848 			  tp->TxPhyAddr);  in rtl_open()
4849 	tp->TxDescArray = NULL;  in rtl_open()
4858 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_stats64()  local
4859 	struct pci_dev *pdev = tp->pci_dev;  in rtl8169_get_stats64()
4860 	struct rtl8169_counters *counters = tp->counters;  in rtl8169_get_stats64()
4866 	rtl_get_priv_stats(&tp->rx_stats, &stats->rx_packets, &stats->rx_bytes);  in rtl8169_get_stats64()
4867 	rtl_get_priv_stats(&tp->tx_stats, &stats->tx_packets, &stats->tx_bytes);  in rtl8169_get_stats64()
4874 		rtl8169_update_counters(tp);  in rtl8169_get_stats64()
4881 		le64_to_cpu(tp->tc_offset.tx_errors);  in rtl8169_get_stats64()
4883 		le32_to_cpu(tp->tc_offset.tx_multi_collision);  in rtl8169_get_stats64()
4885 		le16_to_cpu(tp->tc_offset.tx_aborted);  in rtl8169_get_stats64()
4887 		le16_to_cpu(tp->tc_offset.rx_missed);  in rtl8169_get_stats64()
4892 static void rtl8169_net_suspend(struct rtl8169_private *tp)  in rtl8169_net_suspend()  argument
4894 	netif_device_detach(tp->dev);  in rtl8169_net_suspend()
4896 	if (netif_running(tp->dev))  in rtl8169_net_suspend()
4897 		rtl8169_down(tp);  in rtl8169_net_suspend()
4902 static int rtl8169_net_resume(struct rtl8169_private *tp)  in rtl8169_net_resume()  argument
4904 	rtl_rar_set(tp, tp->dev->dev_addr);  in rtl8169_net_resume()
4906 	if (tp->TxDescArray)  in rtl8169_net_resume()
4907 		rtl8169_up(tp);  in rtl8169_net_resume()
4909 	netif_device_attach(tp->dev);  in rtl8169_net_resume()
4916 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_suspend()  local
4919 	rtl8169_net_suspend(tp);  in rtl8169_suspend()
4920 	if (!device_may_wakeup(tp_to_dev(tp)))  in rtl8169_suspend()
4921 		clk_disable_unprepare(tp->clk);  in rtl8169_suspend()
4929 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_resume()  local
4931 	if (!device_may_wakeup(tp_to_dev(tp)))  in rtl8169_resume()
4932 		clk_prepare_enable(tp->clk);  in rtl8169_resume()
4935 	if (tp->mac_version == RTL_GIGA_MAC_VER_37)  in rtl8169_resume()
4936 		rtl_init_rxcfg(tp);  in rtl8169_resume()
4938 	return rtl8169_net_resume(tp);  in rtl8169_resume()
4943 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_runtime_suspend()  local
4945 	if (!tp->TxDescArray) {  in rtl8169_runtime_suspend()
4946 		netif_device_detach(tp->dev);  in rtl8169_runtime_suspend()
4951 	__rtl8169_set_wol(tp, WAKE_PHY);  in rtl8169_runtime_suspend()
4952 	rtl8169_net_suspend(tp);  in rtl8169_runtime_suspend()
4960 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_runtime_resume()  local
4962 	__rtl8169_set_wol(tp, tp->saved_wolopts);  in rtl8169_runtime_resume()
4964 	return rtl8169_net_resume(tp);  in rtl8169_runtime_resume()
4969 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_runtime_idle()  local
4971 	if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))  in rtl8169_runtime_idle()
4985 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)  in rtl_wol_shutdown_quirk()  argument
4988 	switch (tp->mac_version) {  in rtl_wol_shutdown_quirk()
4992 		pci_clear_master(tp->pci_dev);  in rtl_wol_shutdown_quirk()
4994 		RTL_W8(tp, ChipCmd, CmdRxEnb);  in rtl_wol_shutdown_quirk()
4995 		rtl_pci_commit(tp);  in rtl_wol_shutdown_quirk()
5004 	struct rtl8169_private *tp = pci_get_drvdata(pdev);  in rtl_shutdown()  local
5007 	rtl8169_net_suspend(tp);  in rtl_shutdown()
5011 	rtl_rar_set(tp, tp->dev->perm_addr);  in rtl_shutdown()
5014 		if (tp->saved_wolopts) {  in rtl_shutdown()
5015 			rtl_wol_suspend_quirk(tp);  in rtl_shutdown()
5016 			rtl_wol_shutdown_quirk(tp);  in rtl_shutdown()
5026 	struct rtl8169_private *tp = pci_get_drvdata(pdev);  in rtl_remove_one()  local
5031 	unregister_netdev(tp->dev);  in rtl_remove_one()
5033 	if (r8168_check_dash(tp))  in rtl_remove_one()
5034 		rtl8168_driver_stop(tp);  in rtl_remove_one()
5036 	rtl_release_firmware(tp);  in rtl_remove_one()
5039 	rtl_rar_set(tp, tp->dev->perm_addr);  in rtl_remove_one()
5062 static void rtl_set_irq_mask(struct rtl8169_private *tp)  in rtl_set_irq_mask()  argument
5064 	tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;  in rtl_set_irq_mask()
5066 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)  in rtl_set_irq_mask()
5067 		tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;  in rtl_set_irq_mask()
5068 	else if (tp->mac_version == RTL_GIGA_MAC_VER_11)  in rtl_set_irq_mask()
5070 		tp->irq_mask |= RxFIFOOver;  in rtl_set_irq_mask()
5072 		tp->irq_mask |= RxOverflow;  in rtl_set_irq_mask()
5075 static int rtl_alloc_irq(struct rtl8169_private *tp)  in rtl_alloc_irq()  argument
5079 	switch (tp->mac_version) {  in rtl_alloc_irq()
5081 		rtl_unlock_config_regs(tp);  in rtl_alloc_irq()
5082 		RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);  in rtl_alloc_irq()
5083 		rtl_lock_config_regs(tp);  in rtl_alloc_irq()
5093 	return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);  in rtl_alloc_irq()
5096 static void rtl_read_mac_address(struct rtl8169_private *tp,  in rtl_read_mac_address()  argument
5100 	if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {  in rtl_read_mac_address()
5101 		u32 value = rtl_eri_read(tp, 0xe0);  in rtl_read_mac_address()
5108 		value = rtl_eri_read(tp, 0xe4);  in rtl_read_mac_address()
5111 	} else if (rtl_is_8125(tp)) {  in rtl_read_mac_address()
5112 		rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);  in rtl_read_mac_address()
5118 	return RTL_R8(tp, MCU) & LINK_LIST_RDY;  in DECLARE_RTL_COND()
5121 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)  in r8168g_wait_ll_share_fifo_ready()  argument
5123 	rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);  in r8168g_wait_ll_share_fifo_ready()
5128 	struct rtl8169_private *tp = mii_bus->priv;  in r8169_mdio_read_reg()  local
5133 	return rtl_readphy(tp, phyreg);  in r8169_mdio_read_reg()
5139 	struct rtl8169_private *tp = mii_bus->priv;  in r8169_mdio_write_reg()  local
5144 	rtl_writephy(tp, phyreg, val);  in r8169_mdio_write_reg()
5149 static int r8169_mdio_register(struct rtl8169_private *tp)  in r8169_mdio_register()  argument
5151 	struct pci_dev *pdev = tp->pci_dev;  in r8169_mdio_register()
5160 	new_bus->priv = tp;  in r8169_mdio_register()
5173 	tp->phydev = mdiobus_get_phy(new_bus, 0);  in r8169_mdio_register()
5174 	if (!tp->phydev) {  in r8169_mdio_register()
5176 	} else if (!tp->phydev->drv) {  in r8169_mdio_register()
5181 			tp->phydev->phy_id);  in r8169_mdio_register()
5186 	phy_suspend(tp->phydev);  in r8169_mdio_register()
5191 static void rtl_hw_init_8168g(struct rtl8169_private *tp)  in rtl_hw_init_8168g()  argument
5193 	rtl_enable_rxdvgate(tp);  in rtl_hw_init_8168g()
5195 	RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));  in rtl_hw_init_8168g()
5197 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_init_8168g()
5199 	r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);  in rtl_hw_init_8168g()
5200 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8168g()
5202 	r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));  in rtl_hw_init_8168g()
5203 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8168g()
5206 static void rtl_hw_init_8125(struct rtl8169_private *tp)  in rtl_hw_init_8125()  argument
5208 	rtl_enable_rxdvgate(tp);  in rtl_hw_init_8125()
5210 	RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));  in rtl_hw_init_8125()
5212 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_init_8125()
5214 	r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);  in rtl_hw_init_8125()
5215 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8125()
5217 	r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);  in rtl_hw_init_8125()
5218 	r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);  in rtl_hw_init_8125()
5219 	r8168_mac_ocp_write(tp, 0xc01e, 0x5555);  in rtl_hw_init_8125()
5220 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8125()
5223 static void rtl_hw_initialize(struct rtl8169_private *tp)  in rtl_hw_initialize()  argument
5225 	switch (tp->mac_version) {  in rtl_hw_initialize()
5227 		rtl8168ep_stop_cmac(tp);  in rtl_hw_initialize()
5230 		rtl_hw_init_8168g(tp);  in rtl_hw_initialize()
5233 		rtl_hw_init_8125(tp);  in rtl_hw_initialize()
5240 static int rtl_jumbo_max(struct rtl8169_private *tp)  in rtl_jumbo_max()  argument
5243 	if (!tp->supports_gmii)  in rtl_jumbo_max()
5246 	switch (tp->mac_version) {  in rtl_jumbo_max()
5268 static int rtl_get_ether_clk(struct rtl8169_private *tp)  in rtl_get_ether_clk()  argument
5270 	struct device *d = tp_to_dev(tp);  in rtl_get_ether_clk()
5283 		tp->clk = clk;  in rtl_get_ether_clk()
5294 static void rtl_init_mac_address(struct rtl8169_private *tp)  in rtl_init_mac_address()  argument
5296 	struct net_device *dev = tp->dev;  in rtl_init_mac_address()
5300 	rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);  in rtl_init_mac_address()
5304 	rtl_read_mac_address(tp, mac_addr);  in rtl_init_mac_address()
5308 	rtl_read_mac_from_reg(tp, mac_addr, MAC0);  in rtl_init_mac_address()
5313 	dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");  in rtl_init_mac_address()
5315 	rtl_rar_set(tp, mac_addr);  in rtl_init_mac_address()
5320 	struct rtl8169_private *tp;  in rtl_init_one()  local
5326 	dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));  in rtl_init_one()
5332 	tp = netdev_priv(dev);  in rtl_init_one()
5333 	tp->dev = dev;  in rtl_init_one()
5334 	tp->pci_dev = pdev;  in rtl_init_one()
5335 	tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;  in rtl_init_one()
5336 	tp->eee_adv = -1;  in rtl_init_one()
5337 	tp->ocp_base = OCP_STD_PHY_BASE;  in rtl_init_one()
5340 	rc = rtl_get_ether_clk(tp);  in rtl_init_one()
5349 	tp->aspm_manageable = !rc;  in rtl_init_one()
5380 	tp->mmio_addr = pcim_iomap_table(pdev)[region];  in rtl_init_one()
5382 	xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;  in rtl_init_one()
5385 	chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);  in rtl_init_one()
5391 	tp->mac_version = chipset;  in rtl_init_one()
5393 	tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;  in rtl_init_one()
5395 	if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&  in rtl_init_one()
5399 	rtl_init_rxcfg(tp);  in rtl_init_one()
5401 	rtl8169_irq_mask_and_ack(tp);  in rtl_init_one()
5403 	rtl_hw_initialize(tp);  in rtl_init_one()
5405 	rtl_hw_reset(tp);  in rtl_init_one()
5407 	rc = rtl_alloc_irq(tp);  in rtl_init_one()
5413 	INIT_WORK(&tp->wk.work, rtl_task);  in rtl_init_one()
5414 	u64_stats_init(&tp->rx_stats.syncp);  in rtl_init_one()
5415 	u64_stats_init(&tp->tx_stats.syncp);  in rtl_init_one()
5417 	rtl_init_mac_address(tp);  in rtl_init_one()
5421 	netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);  in rtl_init_one()
5432 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)  in rtl_init_one()
5436 	if (rtl_chip_supports_csum_v2(tp))  in rtl_init_one()
5446 	if (rtl_chip_supports_csum_v2(tp)) {  in rtl_init_one()
5462 	jumbo_max = rtl_jumbo_max(tp);  in rtl_init_one()
5466 	rtl_set_irq_mask(tp);  in rtl_init_one()
5468 	tp->fw_name = rtl_chip_infos[chipset].fw_name;  in rtl_init_one()
5470 	tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),  in rtl_init_one()
5471 					    &tp->counters_phys_addr,  in rtl_init_one()
5473 	if (!tp->counters)  in rtl_init_one()
5476 	pci_set_drvdata(pdev, tp);  in rtl_init_one()
5478 	rc = r8169_mdio_register(tp);  in rtl_init_one()
5483 	rtl_pll_power_down(tp);  in rtl_init_one()
5495 			    jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?  in rtl_init_one()
5498 	if (r8168_check_dash(tp)) {  in rtl_init_one()
5500 		rtl8168_driver_start(tp);  in rtl_init_one()