Lines Matching refs:lane
657 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
663 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
672 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
677 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
683 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
688 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
690 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
693 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
698 serdes_rd(ctx, lane, reg, &val); in serdes_setbits()
700 serdes_wr(ctx, lane, reg, val); in serdes_setbits()
943 int lane; in xgene_phy_sata_cfg_lanes() local
945 for (lane = 0; lane < MAX_LANE; lane++) { in xgene_phy_sata_cfg_lanes()
946 serdes_wr(ctx, lane, RXTX_REG147, 0x6); in xgene_phy_sata_cfg_lanes()
949 serdes_rd(ctx, lane, RXTX_REG0, &val); in xgene_phy_sata_cfg_lanes()
953 serdes_wr(ctx, lane, RXTX_REG0, val); in xgene_phy_sata_cfg_lanes()
956 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
959 ctx->sata_param.txboostgain[lane * 3 + in xgene_phy_sata_cfg_lanes()
960 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
961 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
965 serdes_rd(ctx, lane, RXTX_REG2, &val); in xgene_phy_sata_cfg_lanes()
969 serdes_wr(ctx, lane, RXTX_REG2, val); in xgene_phy_sata_cfg_lanes()
972 serdes_rd(ctx, lane, RXTX_REG4, &val); in xgene_phy_sata_cfg_lanes()
974 serdes_wr(ctx, lane, RXTX_REG4, val); in xgene_phy_sata_cfg_lanes()
977 serdes_rd(ctx, lane, RXTX_REG1, &val); in xgene_phy_sata_cfg_lanes()
980 serdes_wr(ctx, lane, RXTX_REG1, val); in xgene_phy_sata_cfg_lanes()
984 serdes_rd(ctx, lane, RXTX_REG5, &val); in xgene_phy_sata_cfg_lanes()
986 ctx->sata_param.txprecursor_cn1[lane * 3 + in xgene_phy_sata_cfg_lanes()
987 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
989 ctx->sata_param.txpostcursor_cp1[lane * 3 + in xgene_phy_sata_cfg_lanes()
990 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
992 ctx->sata_param.txprecursor_cn2[lane * 3 + in xgene_phy_sata_cfg_lanes()
993 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
994 serdes_wr(ctx, lane, RXTX_REG5, val); in xgene_phy_sata_cfg_lanes()
997 serdes_rd(ctx, lane, RXTX_REG6, &val); in xgene_phy_sata_cfg_lanes()
999 ctx->sata_param.txamplitude[lane * 3 + in xgene_phy_sata_cfg_lanes()
1000 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1005 serdes_wr(ctx, lane, RXTX_REG6, val); in xgene_phy_sata_cfg_lanes()
1008 serdes_rd(ctx, lane, RXTX_REG7, &val); in xgene_phy_sata_cfg_lanes()
1011 serdes_wr(ctx, lane, RXTX_REG7, val); in xgene_phy_sata_cfg_lanes()
1014 serdes_rd(ctx, lane, RXTX_REG8, &val); in xgene_phy_sata_cfg_lanes()
1020 serdes_wr(ctx, lane, RXTX_REG8, val); in xgene_phy_sata_cfg_lanes()
1023 serdes_rd(ctx, lane, RXTX_REG11, &val); in xgene_phy_sata_cfg_lanes()
1025 serdes_wr(ctx, lane, RXTX_REG11, val); in xgene_phy_sata_cfg_lanes()
1028 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_sata_cfg_lanes()
1032 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_sata_cfg_lanes()
1035 serdes_rd(ctx, lane, RXTX_REG26, &val); in xgene_phy_sata_cfg_lanes()
1038 serdes_wr(ctx, lane, RXTX_REG26, val); in xgene_phy_sata_cfg_lanes()
1040 serdes_wr(ctx, lane, RXTX_REG28, 0x0); in xgene_phy_sata_cfg_lanes()
1043 serdes_wr(ctx, lane, RXTX_REG31, 0x0); in xgene_phy_sata_cfg_lanes()
1046 serdes_rd(ctx, lane, RXTX_REG61, &val); in xgene_phy_sata_cfg_lanes()
1050 serdes_wr(ctx, lane, RXTX_REG61, val); in xgene_phy_sata_cfg_lanes()
1052 serdes_rd(ctx, lane, RXTX_REG62, &val); in xgene_phy_sata_cfg_lanes()
1054 serdes_wr(ctx, lane, RXTX_REG62, val); in xgene_phy_sata_cfg_lanes()
1059 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1063 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1069 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1073 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1079 serdes_rd(ctx, lane, reg, &val); in xgene_phy_sata_cfg_lanes()
1083 serdes_wr(ctx, lane, reg, val); in xgene_phy_sata_cfg_lanes()
1086 serdes_rd(ctx, lane, RXTX_REG102, &val); in xgene_phy_sata_cfg_lanes()
1088 serdes_wr(ctx, lane, RXTX_REG102, val); in xgene_phy_sata_cfg_lanes()
1090 serdes_wr(ctx, lane, RXTX_REG114, 0xffe0); in xgene_phy_sata_cfg_lanes()
1092 serdes_rd(ctx, lane, RXTX_REG125, &val); in xgene_phy_sata_cfg_lanes()
1094 ctx->sata_param.txeyedirection[lane * 3 + in xgene_phy_sata_cfg_lanes()
1095 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1097 ctx->sata_param.txeyetuning[lane * 3 + in xgene_phy_sata_cfg_lanes()
1098 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1100 serdes_wr(ctx, lane, RXTX_REG125, val); in xgene_phy_sata_cfg_lanes()
1102 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_sata_cfg_lanes()
1104 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_sata_cfg_lanes()
1106 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_sata_cfg_lanes()
1108 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_sata_cfg_lanes()
1110 serdes_rd(ctx, lane, RXTX_REG145, &val); in xgene_phy_sata_cfg_lanes()
1120 serdes_wr(ctx, lane, RXTX_REG145, val); in xgene_phy_sata_cfg_lanes()
1128 serdes_wr(ctx, lane, reg, 0xFFFF); in xgene_phy_sata_cfg_lanes()
1342 static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_force_lat_summer_cal() argument
1370 serdes_setbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1377 serdes_clrbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1386 serdes_setbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1393 serdes_clrbits(ctx, lane, RXTX_REG127, in xgene_phy_force_lat_summer_cal()
1397 serdes_wr(ctx, lane, RXTX_REG28, 0x7); in xgene_phy_force_lat_summer_cal()
1398 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); in xgene_phy_force_lat_summer_cal()
1399 serdes_clrbits(ctx, lane, RXTX_REG4, in xgene_phy_force_lat_summer_cal()
1401 serdes_clrbits(ctx, lane, RXTX_REG7, in xgene_phy_force_lat_summer_cal()
1404 serdes_wr(ctx, lane, serdes_reg[i].reg, in xgene_phy_force_lat_summer_cal()
1408 static void xgene_phy_reset_rxd(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_reset_rxd() argument
1411 serdes_clrbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); in xgene_phy_reset_rxd()
1414 serdes_setbits(ctx, lane, RXTX_REG7, RXTX_REG7_RESETB_RXD_MASK); in xgene_phy_reset_rxd()
1422 static void xgene_phy_gen_avg_val(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_gen_avg_val() argument
1437 lane); in xgene_phy_gen_avg_val()
1440 serdes_setbits(ctx, lane, RXTX_REG12, in xgene_phy_gen_avg_val()
1443 serdes_wr(ctx, lane, RXTX_REG28, 0x0000); in xgene_phy_gen_avg_val()
1445 serdes_wr(ctx, lane, RXTX_REG31, 0x0000); in xgene_phy_gen_avg_val()
1456 xgene_phy_force_lat_summer_cal(ctx, lane); in xgene_phy_gen_avg_val()
1458 serdes_rd(ctx, lane, RXTX_REG21, &val); in xgene_phy_gen_avg_val()
1463 serdes_rd(ctx, lane, RXTX_REG22, &val); in xgene_phy_gen_avg_val()
1468 serdes_rd(ctx, lane, RXTX_REG23, &val); in xgene_phy_gen_avg_val()
1472 serdes_rd(ctx, lane, RXTX_REG24, &val); in xgene_phy_gen_avg_val()
1476 serdes_rd(ctx, lane, RXTX_REG121, &val); in xgene_phy_gen_avg_val()
1506 xgene_phy_reset_rxd(ctx, lane); in xgene_phy_gen_avg_val()
1510 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1515 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1517 serdes_rd(ctx, lane, RXTX_REG128, &val); in xgene_phy_gen_avg_val()
1522 serdes_wr(ctx, lane, RXTX_REG128, val); in xgene_phy_gen_avg_val()
1524 serdes_rd(ctx, lane, RXTX_REG129, &val); in xgene_phy_gen_avg_val()
1529 serdes_wr(ctx, lane, RXTX_REG129, val); in xgene_phy_gen_avg_val()
1531 serdes_rd(ctx, lane, RXTX_REG130, &val); in xgene_phy_gen_avg_val()
1536 serdes_wr(ctx, lane, RXTX_REG130, val); in xgene_phy_gen_avg_val()
1539 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1542 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1558 serdes_rd(ctx, lane, RXTX_REG14, &val); in xgene_phy_gen_avg_val()
1560 serdes_wr(ctx, lane, RXTX_REG14, val); in xgene_phy_gen_avg_val()
1563 serdes_rd(ctx, lane, RXTX_REG127, &val); in xgene_phy_gen_avg_val()
1566 serdes_wr(ctx, lane, RXTX_REG127, val); in xgene_phy_gen_avg_val()
1569 serdes_rd(ctx, lane, RXTX_REG12, &val); in xgene_phy_gen_avg_val()
1571 serdes_wr(ctx, lane, RXTX_REG12, val); in xgene_phy_gen_avg_val()
1573 serdes_wr(ctx, lane, RXTX_REG28, 0x0007); in xgene_phy_gen_avg_val()
1575 serdes_wr(ctx, lane, RXTX_REG31, 0x7e00); in xgene_phy_gen_avg_val()