Lines Matching +full:pdm +full:- +full:clk +full:- +full:map
1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/clk.h>
34 #include <dt-bindings/pinctrl/rockchip.h>
79 * @offset: if initialized to -1 it will be autocalculated, by specifying
112 * @offset: if initialized to -1 it will be autocalculated, by specifying
127 * @clk: clock of the gpio bank
151 struct clk *clk; member
179 { .offset = -1 }, \
180 { .offset = -1 }, \
181 { .offset = -1 }, \
182 { .offset = -1 }, \
192 { .type = iom0, .offset = -1 }, \
193 { .type = iom1, .offset = -1 }, \
194 { .type = iom2, .offset = -1 }, \
195 { .type = iom3, .offset = -1 }, \
205 { .offset = -1 }, \
206 { .offset = -1 }, \
207 { .offset = -1 }, \
208 { .offset = -1 }, \
211 { .drv_type = type0, .offset = -1 }, \
212 { .drv_type = type1, .offset = -1 }, \
213 { .drv_type = type2, .offset = -1 }, \
214 { .drv_type = type3, .offset = -1 }, \
226 { .offset = -1 }, \
227 { .offset = -1 }, \
228 { .offset = -1 }, \
229 { .offset = -1 }, \
232 { .drv_type = drv0, .offset = -1 }, \
233 { .drv_type = drv1, .offset = -1 }, \
234 { .drv_type = drv2, .offset = -1 }, \
235 { .drv_type = drv3, .offset = -1 }, \
252 { .type = iom0, .offset = -1 }, \
253 { .type = iom1, .offset = -1 }, \
254 { .type = iom2, .offset = -1 }, \
255 { .type = iom3, .offset = -1 }, \
276 { .type = iom0, .offset = -1 }, \
277 { .type = iom1, .offset = -1 }, \
278 { .type = iom2, .offset = -1 }, \
279 { .type = iom3, .offset = -1 }, \
418 for (i = 0; i < info->ngroups; i++) { in pinctrl_name_to_group()
419 if (!strcmp(info->groups[i].name, name)) in pinctrl_name_to_group()
420 return &info->groups[i]; in pinctrl_name_to_group()
433 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in pin_to_bank()
435 while (pin >= (b->pin_base + b->nr_pins)) in pin_to_bank()
445 struct rockchip_pin_bank *b = info->ctrl->pin_banks; in bank_num_to_bank()
448 for (i = 0; i < info->ctrl->nr_banks; i++, b++) { in bank_num_to_bank()
449 if (b->bank_num == num) in bank_num_to_bank()
453 return ERR_PTR(-EINVAL); in bank_num_to_bank()
464 return info->ngroups; in rockchip_get_groups_count()
472 return info->groups[selector].name; in rockchip_get_group_name()
481 if (selector >= info->ngroups) in rockchip_get_group_pins()
482 return -EINVAL; in rockchip_get_group_pins()
484 *pins = info->groups[selector].pins; in rockchip_get_group_pins()
485 *npins = info->groups[selector].npins; in rockchip_get_group_pins()
492 struct pinctrl_map **map, unsigned *num_maps) in rockchip_dt_node_to_map() argument
505 grp = pinctrl_name_to_group(info, np->name); in rockchip_dt_node_to_map()
507 dev_err(info->dev, "unable to find group for node %pOFn\n", in rockchip_dt_node_to_map()
509 return -EINVAL; in rockchip_dt_node_to_map()
512 map_num += grp->npins; in rockchip_dt_node_to_map()
516 return -ENOMEM; in rockchip_dt_node_to_map()
518 *map = new_map; in rockchip_dt_node_to_map()
521 /* create mux map */ in rockchip_dt_node_to_map()
525 return -EINVAL; in rockchip_dt_node_to_map()
528 new_map[0].data.mux.function = parent->name; in rockchip_dt_node_to_map()
529 new_map[0].data.mux.group = np->name; in rockchip_dt_node_to_map()
532 /* create config map */ in rockchip_dt_node_to_map()
534 for (i = 0; i < grp->npins; i++) { in rockchip_dt_node_to_map()
537 pin_get_name(pctldev, grp->pins[i]); in rockchip_dt_node_to_map()
538 new_map[i].data.configs.configs = grp->data[i].configs; in rockchip_dt_node_to_map()
539 new_map[i].data.configs.num_configs = grp->data[i].nconfigs; in rockchip_dt_node_to_map()
542 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", in rockchip_dt_node_to_map()
543 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in rockchip_dt_node_to_map()
549 struct pinctrl_map *map, unsigned num_maps) in rockchip_dt_free_map() argument
551 kfree(map); in rockchip_dt_free_map()
798 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_recalced_mux()
799 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_recalced_mux()
803 for (i = 0; i < ctrl->niomux_recalced; i++) { in rockchip_get_recalced_mux()
804 data = &ctrl->iomux_recalced[i]; in rockchip_get_recalced_mux()
805 if (data->num == bank->bank_num && in rockchip_get_recalced_mux()
806 data->pin == pin) in rockchip_get_recalced_mux()
810 if (i >= ctrl->niomux_recalced) in rockchip_get_recalced_mux()
813 *reg = data->reg; in rockchip_get_recalced_mux()
814 *mask = data->mask; in rockchip_get_recalced_mux()
815 *bit = data->bit; in rockchip_get_recalced_mux()
820 /* cif-d2m0 */
827 /* cif-d2m1 */
834 /* pdm-m0 */
841 /* pdm-m1 */
848 /* uart2-rxm0 */
855 /* uart2-rxm1 */
862 /* uart3-rxm0 */
869 /* uart3-rxm1 */
880 /* spi-0 */
887 /* spi-1 */
894 /* spi-2 */
901 /* i2s-0 */
908 /* i2s-1 */
915 /* emmc-0 */
922 /* emmc-1 */
933 /* non-iomuxed emmc/flash pins on flash-dqs */
941 /* non-iomuxed emmc/flash pins on emmc-clk */
953 /* pwm0-0 */
960 /* pwm0-1 */
967 /* pwm1-0 */
974 /* pwm1-1 */
981 /* pwm2-0 */
988 /* pwm2-1 */
995 /* pwm3-0 */
1002 /* pwm3-1 */
1009 /* sdio-0_d0 */
1016 /* sdio-1_d0 */
1023 /* spi-0_rx */
1030 /* spi-1_rx */
1037 /* emmc-0_cmd */
1044 /* emmc-1_cmd */
1051 /* uart2-0_rx */
1058 /* uart2-1_rx */
1065 /* uart1-0_rx */
1072 /* uart1-1_rx */
1143 /* i2s-8ch-1-sclktxm0 */
1150 /* i2s-8ch-1-sclkrxm0 */
1157 /* i2s-8ch-1-sclktxm1 */
1164 /* i2s-8ch-1-sclkrxm1 */
1171 /* pdm-clkm0 */
1178 /* pdm-clkm1 */
1185 /* pdm-clkm2 */
1192 /* pdm-clkm-m2 */
1301 /* gmac-m1_rxd0 */
1308 /* gmac-m1-optimized_rxd3 */
1415 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux_route()
1416 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_mux_route()
1420 for (i = 0; i < ctrl->niomux_routes; i++) { in rockchip_get_mux_route()
1421 data = &ctrl->iomux_routes[i]; in rockchip_get_mux_route()
1422 if ((data->bank_num == bank->bank_num) && in rockchip_get_mux_route()
1423 (data->pin == pin) && (data->func == mux)) in rockchip_get_mux_route()
1427 if (i >= ctrl->niomux_routes) in rockchip_get_mux_route()
1430 *loc = data->route_location; in rockchip_get_mux_route()
1431 *reg = data->route_offset; in rockchip_get_mux_route()
1432 *value = data->route_val; in rockchip_get_mux_route()
1439 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_mux()
1447 return -EINVAL; in rockchip_get_mux()
1449 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_get_mux()
1450 dev_err(info->dev, "pin %d is unrouted\n", pin); in rockchip_get_mux()
1451 return -EINVAL; in rockchip_get_mux()
1454 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_get_mux()
1457 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_get_mux()
1458 ? info->regmap_pmu : info->regmap_base; in rockchip_get_mux()
1461 mux_type = bank->iomux[iomux_num].type; in rockchip_get_mux()
1462 reg = bank->iomux[iomux_num].offset; in rockchip_get_mux()
1478 if (bank->recalced_mask & BIT(pin)) in rockchip_get_mux()
1491 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_verify_mux()
1495 return -EINVAL; in rockchip_verify_mux()
1497 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { in rockchip_verify_mux()
1498 dev_err(info->dev, "pin %d is unrouted\n", pin); in rockchip_verify_mux()
1499 return -EINVAL; in rockchip_verify_mux()
1502 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { in rockchip_verify_mux()
1504 dev_err(info->dev, in rockchip_verify_mux()
1506 return -ENOTSUPP; in rockchip_verify_mux()
1528 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_mux()
1539 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) in rockchip_set_mux()
1542 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", in rockchip_set_mux()
1543 bank->bank_num, pin, mux); in rockchip_set_mux()
1545 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) in rockchip_set_mux()
1546 ? info->regmap_pmu : info->regmap_base; in rockchip_set_mux()
1549 mux_type = bank->iomux[iomux_num].type; in rockchip_set_mux()
1550 reg = bank->iomux[iomux_num].offset; in rockchip_set_mux()
1566 if (bank->recalced_mask & BIT(pin)) in rockchip_set_mux()
1569 if (bank->route_mask & BIT(pin)) { in rockchip_set_mux()
1577 route_regmap = info->regmap_pmu; in rockchip_set_mux()
1580 route_regmap = info->regmap_base; in rockchip_set_mux()
1608 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_pull_reg_and_bit()
1611 if (bank->bank_num == 0) { in px30_calc_pull_reg_and_bit()
1612 *regmap = info->regmap_pmu; in px30_calc_pull_reg_and_bit()
1615 *regmap = info->regmap_base; in px30_calc_pull_reg_and_bit()
1619 *reg -= 0x10; in px30_calc_pull_reg_and_bit()
1620 *reg += bank->bank_num * PX30_PULL_BANK_STRIDE; in px30_calc_pull_reg_and_bit()
1638 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_drv_reg_and_bit()
1641 if (bank->bank_num == 0) { in px30_calc_drv_reg_and_bit()
1642 *regmap = info->regmap_pmu; in px30_calc_drv_reg_and_bit()
1645 *regmap = info->regmap_base; in px30_calc_drv_reg_and_bit()
1649 *reg -= 0x10; in px30_calc_drv_reg_and_bit()
1650 *reg += bank->bank_num * PX30_DRV_BANK_STRIDE; in px30_calc_drv_reg_and_bit()
1669 struct rockchip_pinctrl *info = bank->drvdata; in px30_calc_schmitt_reg_and_bit()
1672 if (bank->bank_num == 0) { in px30_calc_schmitt_reg_and_bit()
1673 *regmap = info->regmap_pmu; in px30_calc_schmitt_reg_and_bit()
1677 *regmap = info->regmap_base; in px30_calc_schmitt_reg_and_bit()
1680 *reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE; in px30_calc_schmitt_reg_and_bit()
1699 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_pull_reg_and_bit()
1702 if (bank->bank_num == 0) { in rv1108_calc_pull_reg_and_bit()
1703 *regmap = info->regmap_pmu; in rv1108_calc_pull_reg_and_bit()
1707 *regmap = info->regmap_base; in rv1108_calc_pull_reg_and_bit()
1709 *reg -= 0x10; in rv1108_calc_pull_reg_and_bit()
1710 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE; in rv1108_calc_pull_reg_and_bit()
1728 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_drv_reg_and_bit()
1731 if (bank->bank_num == 0) { in rv1108_calc_drv_reg_and_bit()
1732 *regmap = info->regmap_pmu; in rv1108_calc_drv_reg_and_bit()
1735 *regmap = info->regmap_base; in rv1108_calc_drv_reg_and_bit()
1739 *reg -= 0x10; in rv1108_calc_drv_reg_and_bit()
1740 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE; in rv1108_calc_drv_reg_and_bit()
1759 struct rockchip_pinctrl *info = bank->drvdata; in rv1108_calc_schmitt_reg_and_bit()
1762 if (bank->bank_num == 0) { in rv1108_calc_schmitt_reg_and_bit()
1763 *regmap = info->regmap_pmu; in rv1108_calc_schmitt_reg_and_bit()
1767 *regmap = info->regmap_base; in rv1108_calc_schmitt_reg_and_bit()
1770 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE; in rv1108_calc_schmitt_reg_and_bit()
1786 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_schmitt_reg_and_bit()
1788 *regmap = info->regmap_base; in rk3308_calc_schmitt_reg_and_bit()
1791 *reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE; in rk3308_calc_schmitt_reg_and_bit()
1806 struct rockchip_pinctrl *info = bank->drvdata; in rk2928_calc_pull_reg_and_bit()
1808 *regmap = info->regmap_base; in rk2928_calc_pull_reg_and_bit()
1810 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk2928_calc_pull_reg_and_bit()
1822 struct rockchip_pinctrl *info = bank->drvdata; in rk3128_calc_pull_reg_and_bit()
1824 *regmap = info->regmap_base; in rk3128_calc_pull_reg_and_bit()
1826 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; in rk3128_calc_pull_reg_and_bit()
1842 struct rockchip_pinctrl *info = bank->drvdata; in rk3188_calc_pull_reg_and_bit()
1845 if (bank->bank_num == 0 && pin_num < 12) { in rk3188_calc_pull_reg_and_bit()
1846 *regmap = info->regmap_pmu ? info->regmap_pmu in rk3188_calc_pull_reg_and_bit()
1847 : bank->regmap_pull; in rk3188_calc_pull_reg_and_bit()
1848 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; in rk3188_calc_pull_reg_and_bit()
1853 *regmap = info->regmap_pull ? info->regmap_pull in rk3188_calc_pull_reg_and_bit()
1854 : info->regmap_base; in rk3188_calc_pull_reg_and_bit()
1855 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; in rk3188_calc_pull_reg_and_bit()
1858 *reg -= 4; in rk3188_calc_pull_reg_and_bit()
1859 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3188_calc_pull_reg_and_bit()
1867 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); in rk3188_calc_pull_reg_and_bit()
1877 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_pull_reg_and_bit()
1880 if (bank->bank_num == 0) { in rk3288_calc_pull_reg_and_bit()
1881 *regmap = info->regmap_pmu; in rk3288_calc_pull_reg_and_bit()
1888 *regmap = info->regmap_base; in rk3288_calc_pull_reg_and_bit()
1892 *reg -= 0x10; in rk3288_calc_pull_reg_and_bit()
1893 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3288_calc_pull_reg_and_bit()
1911 struct rockchip_pinctrl *info = bank->drvdata; in rk3288_calc_drv_reg_and_bit()
1914 if (bank->bank_num == 0) { in rk3288_calc_drv_reg_and_bit()
1915 *regmap = info->regmap_pmu; in rk3288_calc_drv_reg_and_bit()
1922 *regmap = info->regmap_base; in rk3288_calc_drv_reg_and_bit()
1926 *reg -= 0x10; in rk3288_calc_drv_reg_and_bit()
1927 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3288_calc_drv_reg_and_bit()
1941 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_pull_reg_and_bit()
1943 *regmap = info->regmap_base; in rk3228_calc_pull_reg_and_bit()
1945 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3228_calc_pull_reg_and_bit()
1958 struct rockchip_pinctrl *info = bank->drvdata; in rk3228_calc_drv_reg_and_bit()
1960 *regmap = info->regmap_base; in rk3228_calc_drv_reg_and_bit()
1962 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3228_calc_drv_reg_and_bit()
1975 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_pull_reg_and_bit()
1977 *regmap = info->regmap_base; in rk3308_calc_pull_reg_and_bit()
1979 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3308_calc_pull_reg_and_bit()
1992 struct rockchip_pinctrl *info = bank->drvdata; in rk3308_calc_drv_reg_and_bit()
1994 *regmap = info->regmap_base; in rk3308_calc_drv_reg_and_bit()
1996 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3308_calc_drv_reg_and_bit()
2010 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_pull_reg_and_bit()
2013 if (bank->bank_num == 0) { in rk3368_calc_pull_reg_and_bit()
2014 *regmap = info->regmap_pmu; in rk3368_calc_pull_reg_and_bit()
2021 *regmap = info->regmap_base; in rk3368_calc_pull_reg_and_bit()
2025 *reg -= 0x10; in rk3368_calc_pull_reg_and_bit()
2026 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3368_calc_pull_reg_and_bit()
2041 struct rockchip_pinctrl *info = bank->drvdata; in rk3368_calc_drv_reg_and_bit()
2044 if (bank->bank_num == 0) { in rk3368_calc_drv_reg_and_bit()
2045 *regmap = info->regmap_pmu; in rk3368_calc_drv_reg_and_bit()
2052 *regmap = info->regmap_base; in rk3368_calc_drv_reg_and_bit()
2056 *reg -= 0x10; in rk3368_calc_drv_reg_and_bit()
2057 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE; in rk3368_calc_drv_reg_and_bit()
2073 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_pull_reg_and_bit()
2076 if ((bank->bank_num == 0) || (bank->bank_num == 1)) { in rk3399_calc_pull_reg_and_bit()
2077 *regmap = info->regmap_pmu; in rk3399_calc_pull_reg_and_bit()
2080 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
2086 *regmap = info->regmap_base; in rk3399_calc_pull_reg_and_bit()
2090 *reg -= 0x20; in rk3399_calc_pull_reg_and_bit()
2091 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; in rk3399_calc_pull_reg_and_bit()
2103 struct rockchip_pinctrl *info = bank->drvdata; in rk3399_calc_drv_reg_and_bit()
2107 if ((bank->bank_num == 0) || (bank->bank_num == 1)) in rk3399_calc_drv_reg_and_bit()
2108 *regmap = info->regmap_pmu; in rk3399_calc_drv_reg_and_bit()
2110 *regmap = info->regmap_base; in rk3399_calc_drv_reg_and_bit()
2112 *reg = bank->drv[drv_num].offset; in rk3399_calc_drv_reg_and_bit()
2113 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rk3399_calc_drv_reg_and_bit()
2114 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)) in rk3399_calc_drv_reg_and_bit()
2121 { 2, 4, 8, 12, -1, -1, -1, -1 },
2122 { 3, 6, 9, 12, -1, -1, -1, -1 },
2123 { 5, 10, 15, 20, -1, -1, -1, -1 },
2131 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_drive_perpin()
2132 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_drive_perpin()
2137 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_get_drive_perpin()
2139 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_drive_perpin()
2151 * drive-strength offset is special, as it is in rockchip_get_drive_perpin()
2175 bit -= 16; in rockchip_get_drive_perpin()
2178 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", in rockchip_get_drive_perpin()
2180 return -EINVAL; in rockchip_get_drive_perpin()
2190 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", in rockchip_get_drive_perpin()
2192 return -EINVAL; in rockchip_get_drive_perpin()
2200 data &= (1 << rmask_bits) - 1; in rockchip_get_drive_perpin()
2208 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_drive_perpin()
2209 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_drive_perpin()
2214 int drv_type = bank->drv[pin_num / 8].drv_type; in rockchip_set_drive_perpin()
2216 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n", in rockchip_set_drive_perpin()
2217 bank->bank_num, pin_num, strength); in rockchip_set_drive_perpin()
2219 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_drive_perpin()
2221 ret = -EINVAL; in rockchip_set_drive_perpin()
2233 dev_err(info->dev, "unsupported driver strength %d\n", in rockchip_set_drive_perpin()
2248 * drive-strength offset is special, as it is spread in rockchip_set_drive_perpin()
2270 bit -= 16; in rockchip_set_drive_perpin()
2273 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n", in rockchip_set_drive_perpin()
2275 return -EINVAL; in rockchip_set_drive_perpin()
2284 dev_err(info->dev, "unsupported pinctrl drive type: %d\n", in rockchip_set_drive_perpin()
2286 return -EINVAL; in rockchip_set_drive_perpin()
2290 data = ((1 << rmask_bits) - 1) << (bit + 16); in rockchip_set_drive_perpin()
2316 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_pull()
2317 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_pull()
2324 if (ctrl->type == RK3066B) in rockchip_get_pull()
2327 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_pull()
2333 switch (ctrl->type) { in rockchip_get_pull()
2346 pull_type = bank->pull_type[pin_num / 8]; in rockchip_get_pull()
2348 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; in rockchip_get_pull()
2352 dev_err(info->dev, "unsupported pinctrl type\n"); in rockchip_get_pull()
2353 return -EINVAL; in rockchip_get_pull()
2360 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_pull()
2361 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_pull()
2367 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", in rockchip_set_pull()
2368 bank->bank_num, pin_num, pull); in rockchip_set_pull()
2371 if (ctrl->type == RK3066B) in rockchip_set_pull()
2372 return pull ? -EINVAL : 0; in rockchip_set_pull()
2374 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_pull()
2376 switch (ctrl->type) { in rockchip_set_pull()
2391 pull_type = bank->pull_type[pin_num / 8]; in rockchip_set_pull()
2392 ret = -EINVAL; in rockchip_set_pull()
2402 dev_err(info->dev, "unsupported pull setting %d\n", in rockchip_set_pull()
2408 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); in rockchip_set_pull()
2415 dev_err(info->dev, "unsupported pinctrl type\n"); in rockchip_set_pull()
2416 return -EINVAL; in rockchip_set_pull()
2432 struct rockchip_pinctrl *info = bank->drvdata; in rk3328_calc_schmitt_reg_and_bit()
2434 *regmap = info->regmap_base; in rk3328_calc_schmitt_reg_and_bit()
2437 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE; in rk3328_calc_schmitt_reg_and_bit()
2446 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_get_schmitt()
2447 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_get_schmitt()
2453 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_get_schmitt()
2468 struct rockchip_pinctrl *info = bank->drvdata; in rockchip_set_schmitt()
2469 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_set_schmitt()
2475 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n", in rockchip_set_schmitt()
2476 bank->bank_num, pin_num, enable); in rockchip_set_schmitt()
2478 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit); in rockchip_set_schmitt()
2497 return info->nfunctions; in rockchip_pmx_get_funcs_count()
2505 return info->functions[selector].name; in rockchip_pmx_get_func_name()
2514 *groups = info->functions[selector].groups; in rockchip_pmx_get_groups()
2515 *num_groups = info->functions[selector].ngroups; in rockchip_pmx_get_groups()
2524 const unsigned int *pins = info->groups[group].pins; in rockchip_pmx_set()
2525 const struct rockchip_pin_config *data = info->groups[group].data; in rockchip_pmx_set()
2529 dev_dbg(info->dev, "enable function %s group %s\n", in rockchip_pmx_set()
2530 info->functions[selector].name, info->groups[group].name); in rockchip_pmx_set()
2536 for (cnt = 0; cnt < info->groups[group].npins; cnt++) { in rockchip_pmx_set()
2538 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, in rockchip_pmx_set()
2546 for (cnt--; cnt >= 0; cnt--) in rockchip_pmx_set()
2547 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); in rockchip_pmx_set()
2561 ret = clk_enable(bank->clk); in rockchip_gpio_get_direction()
2563 dev_err(bank->drvdata->dev, in rockchip_gpio_get_direction()
2564 "failed to enable clock for bank %s\n", bank->name); in rockchip_gpio_get_direction()
2567 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in rockchip_gpio_get_direction()
2568 clk_disable(bank->clk); in rockchip_gpio_get_direction()
2595 clk_enable(bank->clk); in _rockchip_pmx_gpio_set_direction()
2596 raw_spin_lock_irqsave(&bank->slock, flags); in _rockchip_pmx_gpio_set_direction()
2598 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
2604 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); in _rockchip_pmx_gpio_set_direction()
2606 raw_spin_unlock_irqrestore(&bank->slock, flags); in _rockchip_pmx_gpio_set_direction()
2607 clk_disable(bank->clk); in _rockchip_pmx_gpio_set_direction()
2620 chip = range->gc; in rockchip_pmx_gpio_set_direction()
2621 pin = offset - chip->base; in rockchip_pmx_gpio_set_direction()
2622 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", in rockchip_pmx_gpio_set_direction()
2623 offset, range->name, pin, input ? "input" : "output"); in rockchip_pmx_gpio_set_direction()
2625 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base, in rockchip_pmx_gpio_set_direction()
2644 switch (ctrl->type) { in rockchip_pinconf_pull_valid()
2684 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2693 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_set()
2694 return -ENOTSUPP; in rockchip_pinconf_set()
2697 return -EINVAL; in rockchip_pinconf_set()
2699 rc = rockchip_set_pull(bank, pin - bank->pin_base, in rockchip_pinconf_set()
2705 rockchip_gpio_set(&bank->gpio_chip, in rockchip_pinconf_set()
2706 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2707 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip, in rockchip_pinconf_set()
2708 pin - bank->pin_base, false); in rockchip_pinconf_set()
2713 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_set()
2714 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_set()
2715 return -ENOTSUPP; in rockchip_pinconf_set()
2718 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2723 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_set()
2724 return -ENOTSUPP; in rockchip_pinconf_set()
2727 pin - bank->pin_base, arg); in rockchip_pinconf_set()
2732 return -ENOTSUPP; in rockchip_pinconf_set()
2752 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2753 return -EINVAL; in rockchip_pinconf_get()
2761 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) in rockchip_pinconf_get()
2762 return -ENOTSUPP; in rockchip_pinconf_get()
2764 if (rockchip_get_pull(bank, pin - bank->pin_base) != param) in rockchip_pinconf_get()
2765 return -EINVAL; in rockchip_pinconf_get()
2770 rc = rockchip_get_mux(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2772 return -EINVAL; in rockchip_pinconf_get()
2774 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); in rockchip_pinconf_get()
2781 /* rk3288 is the first with per-pin drive-strength */ in rockchip_pinconf_get()
2782 if (!info->ctrl->drv_calc_reg) in rockchip_pinconf_get()
2783 return -ENOTSUPP; in rockchip_pinconf_get()
2785 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2792 if (!info->ctrl->schmitt_calc_reg) in rockchip_pinconf_get()
2793 return -ENOTSUPP; in rockchip_pinconf_get()
2795 rc = rockchip_get_schmitt(bank, pin - bank->pin_base); in rockchip_pinconf_get()
2802 return -ENOTSUPP; in rockchip_pinconf_get()
2818 { .compatible = "rockchip,gpio-bank" },
2819 { .compatible = "rockchip,rk3188-gpio-bank0" },
2832 info->nfunctions++; in rockchip_pinctrl_child_count()
2833 info->ngroups += of_get_child_count(child); in rockchip_pinctrl_child_count()
2849 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); in rockchip_pinctrl_parse_groups()
2852 grp->name = np->name; in rockchip_pinctrl_parse_groups()
2862 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); in rockchip_pinctrl_parse_groups()
2863 return -EINVAL; in rockchip_pinctrl_parse_groups()
2866 grp->npins = size / 4; in rockchip_pinctrl_parse_groups()
2868 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), in rockchip_pinctrl_parse_groups()
2870 grp->data = devm_kcalloc(info->dev, in rockchip_pinctrl_parse_groups()
2871 grp->npins, in rockchip_pinctrl_parse_groups()
2874 if (!grp->pins || !grp->data) in rockchip_pinctrl_parse_groups()
2875 return -ENOMEM; in rockchip_pinctrl_parse_groups()
2886 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
2887 grp->data[j].func = be32_to_cpu(*list++); in rockchip_pinctrl_parse_groups()
2891 return -EINVAL; in rockchip_pinctrl_parse_groups()
2895 &grp->data[j].configs, &grp->data[j].nconfigs); in rockchip_pinctrl_parse_groups()
2914 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); in rockchip_pinctrl_parse_functions()
2916 func = &info->functions[index]; in rockchip_pinctrl_parse_functions()
2919 func->name = np->name; in rockchip_pinctrl_parse_functions()
2920 func->ngroups = of_get_child_count(np); in rockchip_pinctrl_parse_functions()
2921 if (func->ngroups <= 0) in rockchip_pinctrl_parse_functions()
2924 func->groups = devm_kcalloc(info->dev, in rockchip_pinctrl_parse_functions()
2925 func->ngroups, sizeof(char *), GFP_KERNEL); in rockchip_pinctrl_parse_functions()
2926 if (!func->groups) in rockchip_pinctrl_parse_functions()
2927 return -ENOMEM; in rockchip_pinctrl_parse_functions()
2930 func->groups[i] = child->name; in rockchip_pinctrl_parse_functions()
2931 grp = &info->groups[grp_index++]; in rockchip_pinctrl_parse_functions()
2945 struct device *dev = &pdev->dev; in rockchip_pinctrl_parse_dt()
2946 struct device_node *np = dev->of_node; in rockchip_pinctrl_parse_dt()
2953 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); in rockchip_pinctrl_parse_dt()
2954 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); in rockchip_pinctrl_parse_dt()
2956 info->functions = devm_kcalloc(dev, in rockchip_pinctrl_parse_dt()
2957 info->nfunctions, in rockchip_pinctrl_parse_dt()
2960 if (!info->functions) in rockchip_pinctrl_parse_dt()
2961 return -ENOMEM; in rockchip_pinctrl_parse_dt()
2963 info->groups = devm_kcalloc(dev, in rockchip_pinctrl_parse_dt()
2964 info->ngroups, in rockchip_pinctrl_parse_dt()
2967 if (!info->groups) in rockchip_pinctrl_parse_dt()
2968 return -ENOMEM; in rockchip_pinctrl_parse_dt()
2978 dev_err(&pdev->dev, "failed to parse function\n"); in rockchip_pinctrl_parse_dt()
2990 struct pinctrl_desc *ctrldesc = &info->pctl; in rockchip_pinctrl_register()
2996 ctrldesc->name = "rockchip-pinctrl"; in rockchip_pinctrl_register()
2997 ctrldesc->owner = THIS_MODULE; in rockchip_pinctrl_register()
2998 ctrldesc->pctlops = &rockchip_pctrl_ops; in rockchip_pinctrl_register()
2999 ctrldesc->pmxops = &rockchip_pmx_ops; in rockchip_pinctrl_register()
3000 ctrldesc->confops = &rockchip_pinconf_ops; in rockchip_pinctrl_register()
3002 pindesc = devm_kcalloc(&pdev->dev, in rockchip_pinctrl_register()
3003 info->ctrl->nr_pins, sizeof(*pindesc), in rockchip_pinctrl_register()
3006 return -ENOMEM; in rockchip_pinctrl_register()
3008 ctrldesc->pins = pindesc; in rockchip_pinctrl_register()
3009 ctrldesc->npins = info->ctrl->nr_pins; in rockchip_pinctrl_register()
3012 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { in rockchip_pinctrl_register()
3013 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
3014 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { in rockchip_pinctrl_register()
3015 pdesc->number = k; in rockchip_pinctrl_register()
3016 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", in rockchip_pinctrl_register()
3017 pin_bank->name, pin); in rockchip_pinctrl_register()
3026 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info); in rockchip_pinctrl_register()
3027 if (IS_ERR(info->pctl_dev)) { in rockchip_pinctrl_register()
3028 dev_err(&pdev->dev, "could not register pinctrl driver\n"); in rockchip_pinctrl_register()
3029 return PTR_ERR(info->pctl_dev); in rockchip_pinctrl_register()
3032 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { in rockchip_pinctrl_register()
3033 pin_bank = &info->ctrl->pin_banks[bank]; in rockchip_pinctrl_register()
3034 pin_bank->grange.name = pin_bank->name; in rockchip_pinctrl_register()
3035 pin_bank->grange.id = bank; in rockchip_pinctrl_register()
3036 pin_bank->grange.pin_base = pin_bank->pin_base; in rockchip_pinctrl_register()
3037 pin_bank->grange.base = pin_bank->gpio_chip.base; in rockchip_pinctrl_register()
3038 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; in rockchip_pinctrl_register()
3039 pin_bank->grange.gc = &pin_bank->gpio_chip; in rockchip_pinctrl_register()
3040 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); in rockchip_pinctrl_register()
3053 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; in rockchip_gpio_set()
3057 clk_enable(bank->clk); in rockchip_gpio_set()
3058 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set()
3066 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set()
3067 clk_disable(bank->clk); in rockchip_gpio_set()
3079 clk_enable(bank->clk); in rockchip_gpio_get()
3080 data = readl(bank->reg_base + GPIO_EXT_PORT); in rockchip_gpio_get()
3081 clk_disable(bank->clk); in rockchip_gpio_get()
3094 return pinctrl_gpio_direction_input(gc->base + offset); in rockchip_gpio_direction_input()
3106 return pinctrl_gpio_direction_output(gc->base + offset); in rockchip_gpio_direction_output()
3113 void __iomem *reg = bank->reg_base + GPIO_DEBOUNCE; in rockchip_gpio_set_debounce()
3117 clk_enable(bank->clk); in rockchip_gpio_set_debounce()
3118 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_gpio_set_debounce()
3127 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_gpio_set_debounce()
3128 clk_disable(bank->clk); in rockchip_gpio_set_debounce()
3152 * still return -ENOTSUPP as before, to make sure the caller in rockchip_gpio_set_config()
3155 return -ENOTSUPP; in rockchip_gpio_set_config()
3157 return -ENOTSUPP; in rockchip_gpio_set_config()
3170 if (!bank->domain) in rockchip_gpio_to_irq()
3171 return -ENXIO; in rockchip_gpio_to_irq()
3173 clk_enable(bank->clk); in rockchip_gpio_to_irq()
3174 virq = irq_create_mapping(bank->domain, offset); in rockchip_gpio_to_irq()
3175 clk_disable(bank->clk); in rockchip_gpio_to_irq()
3177 return (virq) ? : -ENXIO; in rockchip_gpio_to_irq()
3203 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); in rockchip_irq_demux()
3207 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); in rockchip_irq_demux()
3214 virq = irq_find_mapping(bank->domain, irq); in rockchip_irq_demux()
3217 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); in rockchip_irq_demux()
3221 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); in rockchip_irq_demux()
3227 if (bank->toggle_edge_mode & BIT(irq)) { in rockchip_irq_demux()
3231 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); in rockchip_irq_demux()
3233 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_demux()
3235 polarity = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
3242 bank->reg_base + GPIO_INT_POLARITY); in rockchip_irq_demux()
3244 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_demux()
3247 data = readl_relaxed(bank->reg_base + in rockchip_irq_demux()
3261 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_set_type()
3262 u32 mask = BIT(d->hwirq); in rockchip_irq_set_type()
3270 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); in rockchip_irq_set_type()
3274 clk_enable(bank->clk); in rockchip_irq_set_type()
3275 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
3277 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); in rockchip_irq_set_type()
3279 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); in rockchip_irq_set_type()
3281 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3288 raw_spin_lock_irqsave(&bank->slock, flags); in rockchip_irq_set_type()
3291 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); in rockchip_irq_set_type()
3292 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); in rockchip_irq_set_type()
3296 bank->toggle_edge_mode |= mask; in rockchip_irq_set_type()
3303 data = readl(bank->reg_base + GPIO_EXT_PORT); in rockchip_irq_set_type()
3310 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3315 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3320 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3325 bank->toggle_edge_mode &= ~mask; in rockchip_irq_set_type()
3331 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3332 clk_disable(bank->clk); in rockchip_irq_set_type()
3333 return -EINVAL; in rockchip_irq_set_type()
3336 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); in rockchip_irq_set_type()
3337 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); in rockchip_irq_set_type()
3340 raw_spin_unlock_irqrestore(&bank->slock, flags); in rockchip_irq_set_type()
3341 clk_disable(bank->clk); in rockchip_irq_set_type()
3349 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_suspend()
3351 clk_enable(bank->clk); in rockchip_irq_suspend()
3352 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK); in rockchip_irq_suspend()
3353 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK); in rockchip_irq_suspend()
3354 clk_disable(bank->clk); in rockchip_irq_suspend()
3360 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_resume()
3362 clk_enable(bank->clk); in rockchip_irq_resume()
3363 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK); in rockchip_irq_resume()
3364 clk_disable(bank->clk); in rockchip_irq_resume()
3370 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_enable()
3372 clk_enable(bank->clk); in rockchip_irq_enable()
3379 struct rockchip_pin_bank *bank = gc->private; in rockchip_irq_disable()
3382 clk_disable(bank->clk); in rockchip_irq_disable()
3388 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_interrupts_register()
3389 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_interrupts_register()
3395 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_interrupts_register()
3396 if (!bank->valid) { in rockchip_interrupts_register()
3397 dev_warn(&pdev->dev, "bank %s is not valid\n", in rockchip_interrupts_register()
3398 bank->name); in rockchip_interrupts_register()
3402 ret = clk_enable(bank->clk); in rockchip_interrupts_register()
3404 dev_err(&pdev->dev, "failed to enable clock for bank %s\n", in rockchip_interrupts_register()
3405 bank->name); in rockchip_interrupts_register()
3409 bank->domain = irq_domain_add_linear(bank->of_node, 32, in rockchip_interrupts_register()
3411 if (!bank->domain) { in rockchip_interrupts_register()
3412 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", in rockchip_interrupts_register()
3413 bank->name); in rockchip_interrupts_register()
3414 clk_disable(bank->clk); in rockchip_interrupts_register()
3418 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, in rockchip_interrupts_register()
3422 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", in rockchip_interrupts_register()
3423 bank->name); in rockchip_interrupts_register()
3424 irq_domain_remove(bank->domain); in rockchip_interrupts_register()
3425 clk_disable(bank->clk); in rockchip_interrupts_register()
3429 gc = irq_get_domain_generic_chip(bank->domain, 0); in rockchip_interrupts_register()
3430 gc->reg_base = bank->reg_base; in rockchip_interrupts_register()
3431 gc->private = bank; in rockchip_interrupts_register()
3432 gc->chip_types[0].regs.mask = GPIO_INTMASK; in rockchip_interrupts_register()
3433 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; in rockchip_interrupts_register()
3434 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in rockchip_interrupts_register()
3435 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; in rockchip_interrupts_register()
3436 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; in rockchip_interrupts_register()
3437 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; in rockchip_interrupts_register()
3438 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; in rockchip_interrupts_register()
3439 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; in rockchip_interrupts_register()
3440 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; in rockchip_interrupts_register()
3441 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; in rockchip_interrupts_register()
3442 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; in rockchip_interrupts_register()
3443 gc->wake_enabled = IRQ_MSK(bank->nr_pins); in rockchip_interrupts_register()
3450 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK); in rockchip_interrupts_register()
3451 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN); in rockchip_interrupts_register()
3452 gc->mask_cache = 0xffffffff; in rockchip_interrupts_register()
3454 irq_set_chained_handler_and_data(bank->irq, in rockchip_interrupts_register()
3456 clk_disable(bank->clk); in rockchip_interrupts_register()
3465 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_gpiolib_register()
3466 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_gpiolib_register()
3471 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_gpiolib_register()
3472 if (!bank->valid) { in rockchip_gpiolib_register()
3473 dev_warn(&pdev->dev, "bank %s is not valid\n", in rockchip_gpiolib_register()
3474 bank->name); in rockchip_gpiolib_register()
3478 bank->gpio_chip = rockchip_gpiolib_chip; in rockchip_gpiolib_register()
3480 gc = &bank->gpio_chip; in rockchip_gpiolib_register()
3481 gc->base = bank->pin_base; in rockchip_gpiolib_register()
3482 gc->ngpio = bank->nr_pins; in rockchip_gpiolib_register()
3483 gc->parent = &pdev->dev; in rockchip_gpiolib_register()
3484 gc->of_node = bank->of_node; in rockchip_gpiolib_register()
3485 gc->label = bank->name; in rockchip_gpiolib_register()
3489 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", in rockchip_gpiolib_register()
3490 gc->label, ret); in rockchip_gpiolib_register()
3500 for (--i, --bank; i >= 0; --i, --bank) { in rockchip_gpiolib_register()
3501 if (!bank->valid) in rockchip_gpiolib_register()
3503 gpiochip_remove(&bank->gpio_chip); in rockchip_gpiolib_register()
3511 struct rockchip_pin_ctrl *ctrl = info->ctrl; in rockchip_gpiolib_unregister()
3512 struct rockchip_pin_bank *bank = ctrl->pin_banks; in rockchip_gpiolib_unregister()
3515 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_gpiolib_unregister()
3516 if (!bank->valid) in rockchip_gpiolib_unregister()
3518 gpiochip_remove(&bank->gpio_chip); in rockchip_gpiolib_unregister()
3530 if (of_address_to_resource(bank->of_node, 0, &res)) { in rockchip_get_bank_data()
3531 dev_err(info->dev, "cannot find IO resource for bank\n"); in rockchip_get_bank_data()
3532 return -ENOENT; in rockchip_get_bank_data()
3535 bank->reg_base = devm_ioremap_resource(info->dev, &res); in rockchip_get_bank_data()
3536 if (IS_ERR(bank->reg_base)) in rockchip_get_bank_data()
3537 return PTR_ERR(bank->reg_base); in rockchip_get_bank_data()
3540 * special case, where parts of the pull setting-registers are in rockchip_get_bank_data()
3543 if (of_device_is_compatible(bank->of_node, in rockchip_get_bank_data()
3544 "rockchip,rk3188-gpio-bank0")) { in rockchip_get_bank_data()
3547 node = of_parse_phandle(bank->of_node->parent, in rockchip_get_bank_data()
3550 if (of_address_to_resource(bank->of_node, 1, &res)) { in rockchip_get_bank_data()
3551 dev_err(info->dev, "cannot find IO resource for bank\n"); in rockchip_get_bank_data()
3552 return -ENOENT; in rockchip_get_bank_data()
3555 base = devm_ioremap_resource(info->dev, &res); in rockchip_get_bank_data()
3559 resource_size(&res) - 4; in rockchip_get_bank_data()
3561 "rockchip,rk3188-gpio-bank0-pull"; in rockchip_get_bank_data()
3562 bank->regmap_pull = devm_regmap_init_mmio(info->dev, in rockchip_get_bank_data()
3569 bank->irq = irq_of_parse_and_map(bank->of_node, 0); in rockchip_get_bank_data()
3571 bank->clk = of_clk_get(bank->of_node, 0); in rockchip_get_bank_data()
3572 if (IS_ERR(bank->clk)) in rockchip_get_bank_data()
3573 return PTR_ERR(bank->clk); in rockchip_get_bank_data()
3575 return clk_prepare(bank->clk); in rockchip_get_bank_data()
3586 struct device_node *node = pdev->dev.of_node; in rockchip_pinctrl_get_soc_data()
3593 ctrl = (struct rockchip_pin_ctrl *)match->data; in rockchip_pinctrl_get_soc_data()
3596 if (!of_find_property(np, "gpio-controller", NULL)) in rockchip_pinctrl_get_soc_data()
3599 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3600 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3601 if (!strcmp(bank->name, np->name)) { in rockchip_pinctrl_get_soc_data()
3602 bank->of_node = np; in rockchip_pinctrl_get_soc_data()
3605 bank->valid = true; in rockchip_pinctrl_get_soc_data()
3612 grf_offs = ctrl->grf_mux_offset; in rockchip_pinctrl_get_soc_data()
3613 pmu_offs = ctrl->pmu_mux_offset; in rockchip_pinctrl_get_soc_data()
3614 drv_pmu_offs = ctrl->pmu_drv_offset; in rockchip_pinctrl_get_soc_data()
3615 drv_grf_offs = ctrl->grf_drv_offset; in rockchip_pinctrl_get_soc_data()
3616 bank = ctrl->pin_banks; in rockchip_pinctrl_get_soc_data()
3617 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { in rockchip_pinctrl_get_soc_data()
3620 raw_spin_lock_init(&bank->slock); in rockchip_pinctrl_get_soc_data()
3621 bank->drvdata = d; in rockchip_pinctrl_get_soc_data()
3622 bank->pin_base = ctrl->nr_pins; in rockchip_pinctrl_get_soc_data()
3623 ctrl->nr_pins += bank->nr_pins; in rockchip_pinctrl_get_soc_data()
3627 struct rockchip_iomux *iom = &bank->iomux[j]; in rockchip_pinctrl_get_soc_data()
3628 struct rockchip_drv *drv = &bank->drv[j]; in rockchip_pinctrl_get_soc_data()
3631 if (bank_pins >= bank->nr_pins) in rockchip_pinctrl_get_soc_data()
3635 if (iom->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3636 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3637 pmu_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
3639 grf_offs = iom->offset; in rockchip_pinctrl_get_soc_data()
3641 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? in rockchip_pinctrl_get_soc_data()
3646 if (drv->offset >= 0) { in rockchip_pinctrl_get_soc_data()
3647 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3648 drv_pmu_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
3650 drv_grf_offs = drv->offset; in rockchip_pinctrl_get_soc_data()
3652 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ? in rockchip_pinctrl_get_soc_data()
3656 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n", in rockchip_pinctrl_get_soc_data()
3657 i, j, iom->offset, drv->offset); in rockchip_pinctrl_get_soc_data()
3663 inc = (iom->type & (IOMUX_WIDTH_4BIT | in rockchip_pinctrl_get_soc_data()
3666 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3673 * 3bit drive-strenth'es are spread over two registers. in rockchip_pinctrl_get_soc_data()
3675 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) || in rockchip_pinctrl_get_soc_data()
3676 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY)) in rockchip_pinctrl_get_soc_data()
3681 if (iom->type & IOMUX_SOURCE_PMU) in rockchip_pinctrl_get_soc_data()
3689 /* calculate the per-bank recalced_mask */ in rockchip_pinctrl_get_soc_data()
3690 for (j = 0; j < ctrl->niomux_recalced; j++) { in rockchip_pinctrl_get_soc_data()
3693 if (ctrl->iomux_recalced[j].num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3694 pin = ctrl->iomux_recalced[j].pin; in rockchip_pinctrl_get_soc_data()
3695 bank->recalced_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3699 /* calculate the per-bank route_mask */ in rockchip_pinctrl_get_soc_data()
3700 for (j = 0; j < ctrl->niomux_routes; j++) { in rockchip_pinctrl_get_soc_data()
3703 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) { in rockchip_pinctrl_get_soc_data()
3704 pin = ctrl->iomux_routes[j].pin; in rockchip_pinctrl_get_soc_data()
3705 bank->route_mask |= BIT(pin); in rockchip_pinctrl_get_soc_data()
3721 int ret = pinctrl_force_sleep(info->pctl_dev); in rockchip_pinctrl_suspend()
3730 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_suspend()
3731 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_suspend()
3734 pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_suspend()
3747 if (info->ctrl->type == RK3288) { in rockchip_pinctrl_resume()
3748 ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX, in rockchip_pinctrl_resume()
3755 return pinctrl_force_default(info->pctl_dev); in rockchip_pinctrl_resume()
3764 struct device *dev = &pdev->dev; in rockchip_pinctrl_probe()
3766 struct device_node *np = pdev->dev.of_node, *node; in rockchip_pinctrl_probe()
3771 if (!dev->of_node) { in rockchip_pinctrl_probe()
3773 return -ENODEV; in rockchip_pinctrl_probe()
3778 return -ENOMEM; in rockchip_pinctrl_probe()
3780 info->dev = dev; in rockchip_pinctrl_probe()
3785 return -EINVAL; in rockchip_pinctrl_probe()
3787 info->ctrl = ctrl; in rockchip_pinctrl_probe()
3791 info->regmap_base = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
3793 if (IS_ERR(info->regmap_base)) in rockchip_pinctrl_probe()
3794 return PTR_ERR(info->regmap_base); in rockchip_pinctrl_probe()
3797 base = devm_ioremap_resource(&pdev->dev, res); in rockchip_pinctrl_probe()
3801 rockchip_regmap_config.max_register = resource_size(res) - 4; in rockchip_pinctrl_probe()
3803 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, in rockchip_pinctrl_probe()
3806 /* to check for the old dt-bindings */ in rockchip_pinctrl_probe()
3807 info->reg_size = resource_size(res); in rockchip_pinctrl_probe()
3810 if (ctrl->type == RK3188 && info->reg_size < 0x200) { in rockchip_pinctrl_probe()
3812 base = devm_ioremap_resource(&pdev->dev, res); in rockchip_pinctrl_probe()
3817 resource_size(res) - 4; in rockchip_pinctrl_probe()
3818 rockchip_regmap_config.name = "rockchip,pinctrl-pull"; in rockchip_pinctrl_probe()
3819 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, in rockchip_pinctrl_probe()
3828 info->regmap_pmu = syscon_node_to_regmap(node); in rockchip_pinctrl_probe()
3830 if (IS_ERR(info->regmap_pmu)) in rockchip_pinctrl_probe()
3831 return PTR_ERR(info->regmap_pmu); in rockchip_pinctrl_probe()
3875 .label = "PX30-GPIO",
3899 .label = "RV1108-GPIO",
3920 .label = "RK2928-GPIO",
3935 .label = "RK3036-GPIO",
3953 .label = "RK3066a-GPIO",
3969 .label = "RK3066b-GPIO",
3984 .label = "RK3128-GPIO",
4004 .label = "RK3188-GPIO",
4022 .label = "RK3228-GPIO",
4066 .label = "RK3288-GPIO",
4102 .label = "RK3308-GPIO",
4131 .label = "RK3328-GPIO",
4157 .label = "RK3368-GPIO",
4177 -1,
4178 -1,
4221 .label = "RK3399-GPIO",
4234 { .compatible = "rockchip,px30-pinctrl",
4236 { .compatible = "rockchip,rv1108-pinctrl",
4238 { .compatible = "rockchip,rk2928-pinctrl",
4240 { .compatible = "rockchip,rk3036-pinctrl",
4242 { .compatible = "rockchip,rk3066a-pinctrl",
4244 { .compatible = "rockchip,rk3066b-pinctrl",
4246 { .compatible = "rockchip,rk3128-pinctrl",
4248 { .compatible = "rockchip,rk3188-pinctrl",
4250 { .compatible = "rockchip,rk3228-pinctrl",
4252 { .compatible = "rockchip,rk3288-pinctrl",
4254 { .compatible = "rockchip,rk3308-pinctrl",
4256 { .compatible = "rockchip,rk3328-pinctrl",
4258 { .compatible = "rockchip,rk3368-pinctrl",
4260 { .compatible = "rockchip,rk3399-pinctrl",
4268 .name = "rockchip-pinctrl",