Lines Matching +full:pin +full:- +full:settings
2 * Generic device tree based pinctrl driver for one register per pin
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
38 #define DRIVER_NAME "pinctrl-single"
42 * struct pcs_func_vals - mux function register offset and value pair
54 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
71 * struct pcs_conf_type - pinconf property name, pinconf param pair
81 * struct pcs_function - pinctrl function
87 * @conf: array of pin configurations
88 * @nconfs: number of pin configurations available
103 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
117 * struct pcs_data - wrapper for data needed by pinctrl framework
131 * struct pcs_soc_data - SoC specific settings
136 * @rearm: optional SoC specific wake-up rearm function
147 * struct pcs_device - pinctrl device instance
154 * @pctl: pin controller device
166 * @bits_per_pin: number of bits per pin
172 * @desc: pin controller descriptor
210 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
211 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
212 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
214 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
216 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
274 unsigned int pin) in pcs_pin_reg_offset_get() argument
276 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
278 if (pcs->bits_per_mux) { in pcs_pin_reg_offset_get()
281 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; in pcs_pin_reg_offset_get()
285 return pin * mux_bytes; in pcs_pin_reg_offset_get()
289 unsigned int pin) in pcs_pin_shift_reg_get() argument
291 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin; in pcs_pin_shift_reg_get()
296 unsigned pin) in pcs_pin_dbg_show() argument
305 offset = pcs_pin_reg_offset_get(pcs, pin); in pcs_pin_dbg_show()
306 val = pcs->read(pcs->base + offset); in pcs_pin_dbg_show()
308 if (pcs->bits_per_mux) in pcs_pin_dbg_show()
309 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin); in pcs_pin_dbg_show()
311 pa = pcs->res->start + offset; in pcs_pin_dbg_show()
322 devm_kfree(pcs->dev, map); in pcs_dt_free_map()
338 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin, in pcs_get_function() argument
342 struct pin_desc *pdesc = pin_desc_get(pctldev, pin); in pcs_get_function()
347 /* If pin is not described in DTS & enabled, mux_setting is NULL. */ in pcs_get_function()
348 setting = pdesc->mux_setting; in pcs_get_function()
350 return -ENOTSUPP; in pcs_get_function()
351 fselector = setting->func; in pcs_get_function()
353 *func = function->data; in pcs_get_function()
355 dev_err(pcs->dev, "%s could not find function%i\n", in pcs_get_function()
357 return -ENOTSUPP; in pcs_get_function()
372 if (!pcs->fmask) in pcs_set_mux()
375 func = function->data; in pcs_set_mux()
377 return -EINVAL; in pcs_set_mux()
379 dev_dbg(pcs->dev, "enabling %s function%i\n", in pcs_set_mux()
380 func->name, fselector); in pcs_set_mux()
382 for (i = 0; i < func->nvals; i++) { in pcs_set_mux()
387 vals = &func->vals[i]; in pcs_set_mux()
388 raw_spin_lock_irqsave(&pcs->lock, flags); in pcs_set_mux()
389 val = pcs->read(vals->reg); in pcs_set_mux()
391 if (pcs->bits_per_mux) in pcs_set_mux()
392 mask = vals->mask; in pcs_set_mux()
394 mask = pcs->fmask; in pcs_set_mux()
397 val |= (vals->val & mask); in pcs_set_mux()
398 pcs->write(val, vals->reg); in pcs_set_mux()
399 raw_spin_unlock_irqrestore(&pcs->lock, flags); in pcs_set_mux()
406 struct pinctrl_gpio_range *range, unsigned pin) in pcs_request_gpio() argument
414 if (!pcs->fmask) in pcs_request_gpio()
415 return -ENOTSUPP; in pcs_request_gpio()
417 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { in pcs_request_gpio()
421 if (pin >= frange->offset + frange->npins in pcs_request_gpio()
422 || pin < frange->offset) in pcs_request_gpio()
425 offset = pcs_pin_reg_offset_get(pcs, pin); in pcs_request_gpio()
427 if (pcs->bits_per_mux) { in pcs_request_gpio()
428 int pin_shift = pcs_pin_shift_reg_get(pcs, pin); in pcs_request_gpio()
430 data = pcs->read(pcs->base + offset); in pcs_request_gpio()
431 data &= ~(pcs->fmask << pin_shift); in pcs_request_gpio()
432 data |= frange->gpiofunc << pin_shift; in pcs_request_gpio()
433 pcs->write(data, pcs->base + offset); in pcs_request_gpio()
435 data = pcs->read(pcs->base + offset); in pcs_request_gpio()
436 data &= ~pcs->fmask; in pcs_request_gpio()
437 data |= frange->gpiofunc; in pcs_request_gpio()
438 pcs->write(data, pcs->base + offset); in pcs_request_gpio()
454 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin) in pcs_pinconf_clear_bias() argument
460 pcs_pinconf_set(pctldev, pin, &config, 1); in pcs_pinconf_clear_bias()
468 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin) in pcs_pinconf_bias_disable() argument
475 if (!pcs_pinconf_get(pctldev, pin, &config)) in pcs_pinconf_bias_disable()
484 unsigned pin, unsigned long *config) in pcs_pinconf_get() argument
491 ret = pcs_get_function(pctldev, pin, &func); in pcs_pinconf_get()
495 for (i = 0; i < func->nconfs; i++) { in pcs_pinconf_get()
498 if (pcs_pinconf_bias_disable(pctldev, pin)) { in pcs_pinconf_get()
502 return -ENOTSUPP; in pcs_pinconf_get()
504 } else if (param != func->conf[i].param) { in pcs_pinconf_get()
508 offset = pin * (pcs->width / BITS_PER_BYTE); in pcs_pinconf_get()
509 data = pcs->read(pcs->base + offset) & func->conf[i].mask; in pcs_pinconf_get()
510 switch (func->conf[i].param) { in pcs_pinconf_get()
515 if ((data != func->conf[i].enable) || in pcs_pinconf_get()
516 (data == func->conf[i].disable)) in pcs_pinconf_get()
517 return -ENOTSUPP; in pcs_pinconf_get()
522 for (j = 0; j < func->nconfs; j++) { in pcs_pinconf_get()
523 switch (func->conf[j].param) { in pcs_pinconf_get()
525 if (data != func->conf[j].enable) in pcs_pinconf_get()
526 return -ENOTSUPP; in pcs_pinconf_get()
543 return -ENOTSUPP; in pcs_pinconf_get()
547 unsigned pin, unsigned long *configs, in pcs_pinconf_set() argument
556 ret = pcs_get_function(pctldev, pin, &func); in pcs_pinconf_set()
561 for (i = 0; i < func->nconfs; i++) { in pcs_pinconf_set()
563 != func->conf[i].param) in pcs_pinconf_set()
566 offset = pin * (pcs->width / BITS_PER_BYTE); in pcs_pinconf_set()
567 data = pcs->read(pcs->base + offset); in pcs_pinconf_set()
569 switch (func->conf[i].param) { in pcs_pinconf_set()
575 shift = ffs(func->conf[i].mask) - 1; in pcs_pinconf_set()
576 data &= ~func->conf[i].mask; in pcs_pinconf_set()
577 data |= (arg << shift) & func->conf[i].mask; in pcs_pinconf_set()
581 pcs_pinconf_clear_bias(pctldev, pin); in pcs_pinconf_set()
586 pcs_pinconf_clear_bias(pctldev, pin); in pcs_pinconf_set()
589 data &= ~func->conf[i].mask; in pcs_pinconf_set()
591 data |= func->conf[i].enable; in pcs_pinconf_set()
593 data |= func->conf[i].disable; in pcs_pinconf_set()
596 return -ENOTSUPP; in pcs_pinconf_set()
598 pcs->write(data, pcs->base + offset); in pcs_pinconf_set()
602 if (i >= func->nconfs) in pcs_pinconf_set()
603 return -ENOTSUPP; in pcs_pinconf_set()
621 return -ENOTSUPP; in pcs_pinconf_group_get()
624 return -ENOTSUPP; in pcs_pinconf_group_get()
643 return -ENOTSUPP; in pcs_pinconf_group_set()
649 struct seq_file *s, unsigned pin) in pcs_pinconf_dbg_show() argument
677 * pcs_add_pin() - add a pin to the static per controller pin array
683 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_add_pin()
684 struct pinctrl_pin_desc *pin; in pcs_add_pin() local
687 i = pcs->pins.cur; in pcs_add_pin()
688 if (i >= pcs->desc.npins) { in pcs_add_pin()
689 dev_err(pcs->dev, "too many pins, max %i\n", in pcs_add_pin()
690 pcs->desc.npins); in pcs_add_pin()
691 return -ENOMEM; in pcs_add_pin()
694 if (pcs_soc->irq_enable_mask) { in pcs_add_pin()
697 val = pcs->read(pcs->base + offset); in pcs_add_pin()
698 if (val & pcs_soc->irq_enable_mask) { in pcs_add_pin()
699 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", in pcs_add_pin()
700 (unsigned long)pcs->res->start + offset, val); in pcs_add_pin()
701 val &= ~pcs_soc->irq_enable_mask; in pcs_add_pin()
702 pcs->write(val, pcs->base + offset); in pcs_add_pin()
706 pin = &pcs->pins.pa[i]; in pcs_add_pin()
707 pin->number = i; in pcs_add_pin()
708 pcs->pins.cur++; in pcs_add_pin()
714 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
727 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_allocate_pin_table()
729 if (pcs->bits_per_mux && pcs->fmask) { in pcs_allocate_pin_table()
730 pcs->bits_per_pin = fls(pcs->fmask); in pcs_allocate_pin_table()
731 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; in pcs_allocate_pin_table()
732 num_pins_in_register = pcs->width / pcs->bits_per_pin; in pcs_allocate_pin_table()
734 nr_pins = pcs->size / mux_bytes; in pcs_allocate_pin_table()
737 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); in pcs_allocate_pin_table()
738 pcs->pins.pa = devm_kcalloc(pcs->dev, in pcs_allocate_pin_table()
739 nr_pins, sizeof(*pcs->pins.pa), in pcs_allocate_pin_table()
741 if (!pcs->pins.pa) in pcs_allocate_pin_table()
742 return -ENOMEM; in pcs_allocate_pin_table()
744 pcs->desc.pins = pcs->pins.pa; in pcs_allocate_pin_table()
745 pcs->desc.npins = nr_pins; in pcs_allocate_pin_table()
747 for (i = 0; i < pcs->desc.npins; i++) { in pcs_allocate_pin_table()
754 dev_err(pcs->dev, "error adding pins: %i\n", res); in pcs_allocate_pin_table()
763 * pcs_add_function() - adds a new function to the function list
785 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); in pcs_add_function()
787 return -ENOMEM; in pcs_add_function()
789 function->vals = vals; in pcs_add_function()
790 function->nvals = nvals; in pcs_add_function()
792 selector = pinmux_generic_add_function(pcs->pctl, name, in pcs_add_function()
796 devm_kfree(pcs->dev, function); in pcs_add_function()
806 * pcs_get_pin_by_offset() - get a pin index based on the register offset
816 if (offset >= pcs->size) { in pcs_get_pin_by_offset()
817 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", in pcs_get_pin_by_offset()
818 offset, pcs->size); in pcs_get_pin_by_offset()
819 return -EINVAL; in pcs_get_pin_by_offset()
822 if (pcs->bits_per_mux) in pcs_get_pin_by_offset()
823 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; in pcs_get_pin_by_offset()
825 index = offset / (pcs->width / BITS_PER_BYTE); in pcs_get_pin_by_offset()
837 int ret = -EINVAL; in pcs_config_match()
850 (*conf)->param = param; in add_config()
851 (*conf)->val = value; in add_config()
852 (*conf)->enable = enable; in add_config()
853 (*conf)->disable = disable; in add_config()
854 (*conf)->mask = mask; in add_config()
868 struct pcs_conf_vals **conf, unsigned long **settings) in pcs_add_conf2() argument
878 shift = ffs(value[1]) - 1; in pcs_add_conf2()
881 add_setting(settings, param, value[0] >> shift); in pcs_add_conf2()
887 struct pcs_conf_vals **conf, unsigned long **settings) in pcs_add_conf4() argument
897 dev_err(pcs->dev, "mask field of the property can't be 0\n"); in pcs_add_conf4()
905 dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); in pcs_add_conf4()
907 add_setting(settings, param, ret); in pcs_add_conf4()
917 unsigned long *settings = NULL, *s = NULL; in pcs_parse_pinconf() local
920 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, in pcs_parse_pinconf()
921 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, in pcs_parse_pinconf()
922 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, in pcs_parse_pinconf()
923 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, }, in pcs_parse_pinconf()
926 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, in pcs_parse_pinconf()
927 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, in pcs_parse_pinconf()
928 { "pinctrl-single,input-schmitt-enable", in pcs_parse_pinconf()
934 return -ENOTSUPP; in pcs_parse_pinconf()
946 return -ENOTSUPP; in pcs_parse_pinconf()
948 func->conf = devm_kcalloc(pcs->dev, in pcs_parse_pinconf()
951 if (!func->conf) in pcs_parse_pinconf()
952 return -ENOMEM; in pcs_parse_pinconf()
953 func->nconfs = nconfs; in pcs_parse_pinconf()
954 conf = &(func->conf[0]); in pcs_parse_pinconf()
956 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long), in pcs_parse_pinconf()
958 if (!settings) in pcs_parse_pinconf()
959 return -ENOMEM; in pcs_parse_pinconf()
960 s = &settings[0]; in pcs_parse_pinconf()
968 m->type = PIN_MAP_TYPE_CONFIGS_GROUP; in pcs_parse_pinconf()
969 m->data.configs.group_or_pin = np->name; in pcs_parse_pinconf()
970 m->data.configs.configs = settings; in pcs_parse_pinconf()
971 m->data.configs.num_configs = nconfs; in pcs_parse_pinconf()
976 * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
985 * Also note that this driver tries to avoid understanding pin and function
989 * decipher the pin and function names using debugfs.
1000 const char *name = "pinctrl-single,pins"; in pcs_parse_one_pinctrl_entry()
1002 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; in pcs_parse_one_pinctrl_entry()
1007 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); in pcs_parse_one_pinctrl_entry()
1008 return -EINVAL; in pcs_parse_one_pinctrl_entry()
1011 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL); in pcs_parse_one_pinctrl_entry()
1013 return -ENOMEM; in pcs_parse_one_pinctrl_entry()
1015 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL); in pcs_parse_one_pinctrl_entry()
1022 int pin; in pcs_parse_one_pinctrl_entry() local
1029 dev_err(pcs->dev, "invalid args_count for spec: %i\n", in pcs_parse_one_pinctrl_entry()
1035 vals[found].reg = pcs->base + offset; in pcs_parse_one_pinctrl_entry()
1046 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n", in pcs_parse_one_pinctrl_entry()
1049 pin = pcs_get_pin_by_offset(pcs, offset); in pcs_parse_one_pinctrl_entry()
1050 if (pin < 0) { in pcs_parse_one_pinctrl_entry()
1051 dev_err(pcs->dev, in pcs_parse_one_pinctrl_entry()
1056 pins[found++] = pin; in pcs_parse_one_pinctrl_entry()
1059 pgnames[0] = np->name; in pcs_parse_one_pinctrl_entry()
1060 mutex_lock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1061 fsel = pcs_add_function(pcs, &function, np->name, vals, found, in pcs_parse_one_pinctrl_entry()
1068 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); in pcs_parse_one_pinctrl_entry()
1074 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in pcs_parse_one_pinctrl_entry()
1075 (*map)->data.mux.group = np->name; in pcs_parse_one_pinctrl_entry()
1076 (*map)->data.mux.function = np->name; in pcs_parse_one_pinctrl_entry()
1082 else if (res == -ENOTSUPP) in pcs_parse_one_pinctrl_entry()
1089 mutex_unlock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1094 pinctrl_generic_remove_group(pcs->pctl, gsel); in pcs_parse_one_pinctrl_entry()
1097 pinmux_generic_remove_function(pcs->pctl, fsel); in pcs_parse_one_pinctrl_entry()
1099 mutex_unlock(&pcs->mutex); in pcs_parse_one_pinctrl_entry()
1100 devm_kfree(pcs->dev, pins); in pcs_parse_one_pinctrl_entry()
1103 devm_kfree(pcs->dev, vals); in pcs_parse_one_pinctrl_entry()
1114 const char *name = "pinctrl-single,bits"; in pcs_parse_bits_in_pinctrl_entry()
1116 int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; in pcs_parse_bits_in_pinctrl_entry()
1122 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); in pcs_parse_bits_in_pinctrl_entry()
1123 return -EINVAL; in pcs_parse_bits_in_pinctrl_entry()
1126 npins_in_row = pcs->width / pcs->bits_per_pin; in pcs_parse_bits_in_pinctrl_entry()
1128 vals = devm_kzalloc(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1132 return -ENOMEM; in pcs_parse_bits_in_pinctrl_entry()
1134 pins = devm_kzalloc(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1145 int pin; in pcs_parse_bits_in_pinctrl_entry() local
1152 dev_err(pcs->dev, "invalid args_count for spec: %i\n", in pcs_parse_bits_in_pinctrl_entry()
1162 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n", in pcs_parse_bits_in_pinctrl_entry()
1168 pin_num_from_lsb = bit_pos / pcs->bits_per_pin; in pcs_parse_bits_in_pinctrl_entry()
1169 mask_pos = ((pcs->fmask) << bit_pos); in pcs_parse_bits_in_pinctrl_entry()
1174 dev_err(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1183 dev_warn(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1190 vals[found].reg = pcs->base + offset; in pcs_parse_bits_in_pinctrl_entry()
1193 pin = pcs_get_pin_by_offset(pcs, offset); in pcs_parse_bits_in_pinctrl_entry()
1194 if (pin < 0) { in pcs_parse_bits_in_pinctrl_entry()
1195 dev_err(pcs->dev, in pcs_parse_bits_in_pinctrl_entry()
1200 pins[found++] = pin + pin_num_from_lsb; in pcs_parse_bits_in_pinctrl_entry()
1204 pgnames[0] = np->name; in pcs_parse_bits_in_pinctrl_entry()
1205 mutex_lock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1206 fsel = pcs_add_function(pcs, &function, np->name, vals, found, in pcs_parse_bits_in_pinctrl_entry()
1213 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); in pcs_parse_bits_in_pinctrl_entry()
1219 (*map)->type = PIN_MAP_TYPE_MUX_GROUP; in pcs_parse_bits_in_pinctrl_entry()
1220 (*map)->data.mux.group = np->name; in pcs_parse_bits_in_pinctrl_entry()
1221 (*map)->data.mux.function = np->name; in pcs_parse_bits_in_pinctrl_entry()
1224 dev_err(pcs->dev, "pinconf not supported\n"); in pcs_parse_bits_in_pinctrl_entry()
1225 res = -ENOTSUPP; in pcs_parse_bits_in_pinctrl_entry()
1230 mutex_unlock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1235 pinctrl_generic_remove_group(pcs->pctl, gsel); in pcs_parse_bits_in_pinctrl_entry()
1238 pinmux_generic_remove_function(pcs->pctl, fsel); in pcs_parse_bits_in_pinctrl_entry()
1240 mutex_unlock(&pcs->mutex); in pcs_parse_bits_in_pinctrl_entry()
1241 devm_kfree(pcs->dev, pins); in pcs_parse_bits_in_pinctrl_entry()
1244 devm_kfree(pcs->dev, vals); in pcs_parse_bits_in_pinctrl_entry()
1249 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1266 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL); in pcs_dt_node_to_map()
1268 return -ENOMEM; in pcs_dt_node_to_map()
1272 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); in pcs_dt_node_to_map()
1274 ret = -ENOMEM; in pcs_dt_node_to_map()
1278 if (pcs->bits_per_mux) { in pcs_dt_node_to_map()
1282 dev_err(pcs->dev, "no pins entries for %pOFn\n", in pcs_dt_node_to_map()
1290 dev_err(pcs->dev, "no pins entries for %pOFn\n", in pcs_dt_node_to_map()
1299 devm_kfree(pcs->dev, pgnames); in pcs_dt_node_to_map()
1301 devm_kfree(pcs->dev, *map); in pcs_dt_node_to_map()
1307 * pcs_irq_free() - free interrupt
1312 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_irq_free()
1314 if (pcs_soc->irq < 0) in pcs_irq_free()
1317 if (pcs->domain) in pcs_irq_free()
1318 irq_domain_remove(pcs->domain); in pcs_irq_free()
1321 free_irq(pcs_soc->irq, pcs_soc); in pcs_irq_free()
1323 irq_set_chained_handler(pcs_soc->irq, NULL); in pcs_irq_free()
1327 * pcs_free_resources() - free memory used by this driver
1333 pinctrl_unregister(pcs->pctl); in pcs_free_resources()
1336 if (pcs->missing_nr_pinctrl_cells) in pcs_free_resources()
1337 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells); in pcs_free_resources()
1343 const char *propname = "pinctrl-single,gpio-range"; in pcs_add_gpio_func()
1344 const char *cellname = "#pinctrl-single,gpio-range-cells"; in pcs_add_gpio_func()
1357 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); in pcs_add_gpio_func()
1359 ret = -ENOMEM; in pcs_add_gpio_func()
1362 range->offset = gpiospec.args[0]; in pcs_add_gpio_func()
1363 range->npins = gpiospec.args[1]; in pcs_add_gpio_func()
1364 range->gpiofunc = gpiospec.args[2]; in pcs_add_gpio_func()
1365 mutex_lock(&pcs->mutex); in pcs_add_gpio_func()
1366 list_add_tail(&range->node, &pcs->gpiofuncs); in pcs_add_gpio_func()
1367 mutex_unlock(&pcs->mutex); in pcs_add_gpio_func()
1387 * pcs_irq_set() - enables or disables an interrupt
1388 * @pcs_soc: SoC specific settings
1393 * register that is typically used for wake-up events.
1403 list_for_each(pos, &pcs->irqs) { in pcs_irq_set()
1408 if (irq != pcswi->irq) in pcs_irq_set()
1411 soc_mask = pcs_soc->irq_enable_mask; in pcs_irq_set()
1412 raw_spin_lock(&pcs->lock); in pcs_irq_set()
1413 mask = pcs->read(pcswi->reg); in pcs_irq_set()
1418 pcs->write(mask, pcswi->reg); in pcs_irq_set()
1421 mask = pcs->read(pcswi->reg); in pcs_irq_set()
1422 raw_spin_unlock(&pcs->lock); in pcs_irq_set()
1425 if (pcs_soc->rearm) in pcs_irq_set()
1426 pcs_soc->rearm(); in pcs_irq_set()
1430 * pcs_irq_mask() - mask pinctrl interrupt
1437 pcs_irq_set(pcs_soc, d->irq, false); in pcs_irq_mask()
1441 * pcs_irq_unmask() - unmask pinctrl interrupt
1448 pcs_irq_set(pcs_soc, d->irq, true); in pcs_irq_unmask()
1452 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1454 * @state: wake-up state
1457 * For runtime PM, the wake-up events should be enabled by default.
1470 * pcs_irq_handle() - common interrupt handler
1471 * @pcs_soc: SoC specific settings
1474 * mux register. This interrupt is typically used for wake-up events.
1484 list_for_each(pos, &pcs->irqs) { in pcs_irq_handle()
1489 raw_spin_lock(&pcs->lock); in pcs_irq_handle()
1490 mask = pcs->read(pcswi->reg); in pcs_irq_handle()
1491 raw_spin_unlock(&pcs->lock); in pcs_irq_handle()
1492 if (mask & pcs_soc->irq_status_mask) { in pcs_irq_handle()
1493 generic_handle_irq(irq_find_mapping(pcs->domain, in pcs_irq_handle()
1494 pcswi->hwirq)); in pcs_irq_handle()
1503 * pcs_irq_handler() - handler for the shared interrupt case
1508 * pinctrl-single share a single interrupt like on omaps.
1518 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1522 * pinctrl-single instance.
1539 struct pcs_soc_data *pcs_soc = d->host_data; in pcs_irqdomain_map()
1544 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL); in pcs_irqdomain_map()
1546 return -ENOMEM; in pcs_irqdomain_map()
1548 pcswi->reg = pcs->base + hwirq; in pcs_irqdomain_map()
1549 pcswi->hwirq = hwirq; in pcs_irqdomain_map()
1550 pcswi->irq = irq; in pcs_irqdomain_map()
1552 mutex_lock(&pcs->mutex); in pcs_irqdomain_map()
1553 list_add_tail(&pcswi->node, &pcs->irqs); in pcs_irqdomain_map()
1554 mutex_unlock(&pcs->mutex); in pcs_irqdomain_map()
1557 irq_set_chip_and_handler(irq, &pcs->chip, in pcs_irqdomain_map()
1571 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1578 struct pcs_soc_data *pcs_soc = &pcs->socdata; in pcs_irq_init_chained_handler()
1582 if (!pcs_soc->irq_enable_mask || in pcs_irq_init_chained_handler()
1583 !pcs_soc->irq_status_mask) { in pcs_irq_init_chained_handler()
1584 pcs_soc->irq = -1; in pcs_irq_init_chained_handler()
1585 return -EINVAL; in pcs_irq_init_chained_handler()
1588 INIT_LIST_HEAD(&pcs->irqs); in pcs_irq_init_chained_handler()
1589 pcs->chip.name = name; in pcs_irq_init_chained_handler()
1590 pcs->chip.irq_ack = pcs_irq_mask; in pcs_irq_init_chained_handler()
1591 pcs->chip.irq_mask = pcs_irq_mask; in pcs_irq_init_chained_handler()
1592 pcs->chip.irq_unmask = pcs_irq_unmask; in pcs_irq_init_chained_handler()
1593 pcs->chip.irq_set_wake = pcs_irq_set_wake; in pcs_irq_init_chained_handler()
1598 res = request_irq(pcs_soc->irq, pcs_irq_handler, in pcs_irq_init_chained_handler()
1603 pcs_soc->irq = -1; in pcs_irq_init_chained_handler()
1607 irq_set_chained_handler_and_data(pcs_soc->irq, in pcs_irq_init_chained_handler()
1618 num_irqs = pcs->size; in pcs_irq_init_chained_handler()
1620 pcs->domain = irq_domain_add_simple(np, num_irqs, 0, in pcs_irq_init_chained_handler()
1623 if (!pcs->domain) { in pcs_irq_init_chained_handler()
1624 irq_set_chained_handler(pcs_soc->irq, NULL); in pcs_irq_init_chained_handler()
1625 return -EINVAL; in pcs_irq_init_chained_handler()
1639 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_save_context()
1641 if (!pcs->saved_vals) { in pcs_save_context()
1642 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC); in pcs_save_context()
1643 if (!pcs->saved_vals) in pcs_save_context()
1644 return -ENOMEM; in pcs_save_context()
1647 switch (pcs->width) { in pcs_save_context()
1649 regsl = pcs->saved_vals; in pcs_save_context()
1650 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1651 *regsl++ = pcs->read(pcs->base + i); in pcs_save_context()
1654 regsw = pcs->saved_vals; in pcs_save_context()
1655 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1656 *regsw++ = pcs->read(pcs->base + i); in pcs_save_context()
1659 regshw = pcs->saved_vals; in pcs_save_context()
1660 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_save_context()
1661 *regshw++ = pcs->read(pcs->base + i); in pcs_save_context()
1675 mux_bytes = pcs->width / BITS_PER_BYTE; in pcs_restore_context()
1677 switch (pcs->width) { in pcs_restore_context()
1679 regsl = pcs->saved_vals; in pcs_restore_context()
1680 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1681 pcs->write(*regsl++, pcs->base + i); in pcs_restore_context()
1684 regsw = pcs->saved_vals; in pcs_restore_context()
1685 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1686 pcs->write(*regsw++, pcs->base + i); in pcs_restore_context()
1689 regshw = pcs->saved_vals; in pcs_restore_context()
1690 for (i = 0; i < pcs->size; i += mux_bytes) in pcs_restore_context()
1691 pcs->write(*regshw++, pcs->base + i); in pcs_restore_context()
1703 return -EINVAL; in pinctrl_single_suspend()
1705 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) { in pinctrl_single_suspend()
1713 return pinctrl_force_sleep(pcs->pctl); in pinctrl_single_suspend()
1722 return -EINVAL; in pinctrl_single_resume()
1724 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) in pinctrl_single_resume()
1727 return pinctrl_force_default(pcs->pctl); in pinctrl_single_resume()
1732 * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1737 * Handle legacy binding with no #pinctrl-cells. This should be
1738 * always two pinctrl-single,bit-per-mux and one for others.
1746 const char *name = "#pinctrl-cells"; in pcs_quirk_missing_pinctrl_cells()
1754 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n", in pcs_quirk_missing_pinctrl_cells()
1757 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1759 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1761 p->length = sizeof(__be32); in pcs_quirk_missing_pinctrl_cells()
1762 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1763 if (!p->value) in pcs_quirk_missing_pinctrl_cells()
1764 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1765 *(__be32 *)p->value = cpu_to_be32(cells); in pcs_quirk_missing_pinctrl_cells()
1767 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL); in pcs_quirk_missing_pinctrl_cells()
1768 if (!p->name) in pcs_quirk_missing_pinctrl_cells()
1769 return -ENOMEM; in pcs_quirk_missing_pinctrl_cells()
1771 pcs->missing_nr_pinctrl_cells = p; in pcs_quirk_missing_pinctrl_cells()
1774 error = of_add_property(np, pcs->missing_nr_pinctrl_cells); in pcs_quirk_missing_pinctrl_cells()
1782 struct device_node *np = pdev->dev.of_node; in pcs_probe()
1789 soc = of_device_get_match_data(&pdev->dev); in pcs_probe()
1791 return -EINVAL; in pcs_probe()
1793 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); in pcs_probe()
1795 return -ENOMEM; in pcs_probe()
1797 pcs->dev = &pdev->dev; in pcs_probe()
1798 pcs->np = np; in pcs_probe()
1799 raw_spin_lock_init(&pcs->lock); in pcs_probe()
1800 mutex_init(&pcs->mutex); in pcs_probe()
1801 INIT_LIST_HEAD(&pcs->gpiofuncs); in pcs_probe()
1802 pcs->flags = soc->flags; in pcs_probe()
1803 memcpy(&pcs->socdata, soc, sizeof(*soc)); in pcs_probe()
1805 ret = of_property_read_u32(np, "pinctrl-single,register-width", in pcs_probe()
1806 &pcs->width); in pcs_probe()
1808 dev_err(pcs->dev, "register width not specified\n"); in pcs_probe()
1813 ret = of_property_read_u32(np, "pinctrl-single,function-mask", in pcs_probe()
1814 &pcs->fmask); in pcs_probe()
1816 pcs->fshift = __ffs(pcs->fmask); in pcs_probe()
1817 pcs->fmax = pcs->fmask >> pcs->fshift; in pcs_probe()
1820 pcs->fmask = 0; in pcs_probe()
1821 pcs->fshift = 0; in pcs_probe()
1822 pcs->fmax = 0; in pcs_probe()
1825 ret = of_property_read_u32(np, "pinctrl-single,function-off", in pcs_probe()
1826 &pcs->foff); in pcs_probe()
1828 pcs->foff = PCS_OFF_DISABLED; in pcs_probe()
1830 pcs->bits_per_mux = of_property_read_bool(np, in pcs_probe()
1831 "pinctrl-single,bit-per-mux"); in pcs_probe()
1833 pcs->bits_per_mux ? 2 : 1); in pcs_probe()
1835 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n"); in pcs_probe()
1842 dev_err(pcs->dev, "could not get resource\n"); in pcs_probe()
1843 return -ENODEV; in pcs_probe()
1846 pcs->res = devm_request_mem_region(pcs->dev, res->start, in pcs_probe()
1848 if (!pcs->res) { in pcs_probe()
1849 dev_err(pcs->dev, "could not get mem_region\n"); in pcs_probe()
1850 return -EBUSY; in pcs_probe()
1853 pcs->size = resource_size(pcs->res); in pcs_probe()
1854 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); in pcs_probe()
1855 if (!pcs->base) { in pcs_probe()
1856 dev_err(pcs->dev, "could not ioremap\n"); in pcs_probe()
1857 return -ENODEV; in pcs_probe()
1862 switch (pcs->width) { in pcs_probe()
1864 pcs->read = pcs_readb; in pcs_probe()
1865 pcs->write = pcs_writeb; in pcs_probe()
1868 pcs->read = pcs_readw; in pcs_probe()
1869 pcs->write = pcs_writew; in pcs_probe()
1872 pcs->read = pcs_readl; in pcs_probe()
1873 pcs->write = pcs_writel; in pcs_probe()
1879 pcs->desc.name = DRIVER_NAME; in pcs_probe()
1880 pcs->desc.pctlops = &pcs_pinctrl_ops; in pcs_probe()
1881 pcs->desc.pmxops = &pcs_pinmux_ops; in pcs_probe()
1883 pcs->desc.confops = &pcs_pinconf_ops; in pcs_probe()
1884 pcs->desc.owner = THIS_MODULE; in pcs_probe()
1890 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl); in pcs_probe()
1892 dev_err(pcs->dev, "could not register single pinctrl driver\n"); in pcs_probe()
1900 pcs->socdata.irq = irq_of_parse_and_map(np, 0); in pcs_probe()
1901 if (pcs->socdata.irq) in pcs_probe()
1902 pcs->flags |= PCS_FEAT_IRQ; in pcs_probe()
1905 pdata = dev_get_platdata(&pdev->dev); in pcs_probe()
1907 if (pdata->rearm) in pcs_probe()
1908 pcs->socdata.rearm = pdata->rearm; in pcs_probe()
1909 if (pdata->irq) { in pcs_probe()
1910 pcs->socdata.irq = pdata->irq; in pcs_probe()
1911 pcs->flags |= PCS_FEAT_IRQ; in pcs_probe()
1918 dev_warn(pcs->dev, "initialized with no interrupts\n"); in pcs_probe()
1921 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size); in pcs_probe()
1923 return pinctrl_enable(pcs->pctl); in pcs_probe()
1968 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1969 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1970 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1971 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1972 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1973 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1974 { .compatible = "pinconf-single", .data = &pinconf_single },
1995 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");