Lines Matching refs:mr
305 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_dump_regs() local
311 ms, mr, md); in mesh_dump_regs()
314 (mr->count_hi << 8) + mr->count_lo, mr->sequence, in mesh_dump_regs()
315 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count, in mesh_dump_regs()
316 mr->exception, mr->error, mr->intr_mask, mr->interrupt, in mesh_dump_regs()
317 mr->sync_params); in mesh_dump_regs()
318 while(in_8(&mr->fifo_count)) in mesh_dump_regs()
319 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo)); in mesh_dump_regs()
339 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr) in mesh_flush_io() argument
341 (void)in_8(&mr->mesh_id); in mesh_flush_io()
360 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_init() local
363 mesh_flush_io(mr); in mesh_init()
368 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_init()
369 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_init()
370 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_init()
371 mesh_flush_io(mr); in mesh_init()
373 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_init()
374 out_8(&mr->source_id, ms->host->this_id); in mesh_init()
375 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_init()
376 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
382 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_init()
383 mesh_flush_io(mr); in mesh_init()
385 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_init()
386 mesh_flush_io(mr); in mesh_init()
393 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */ in mesh_init()
394 out_8(&mr->sequence, SEQ_FLUSHFIFO); in mesh_init()
395 mesh_flush_io(mr); in mesh_init()
397 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
398 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_init()
407 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_start_cmd() local
446 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
447 out_8(&mr->interrupt, INT_CMDDONE); in mesh_start_cmd()
448 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_start_cmd()
449 mesh_flush_io(mr); in mesh_start_cmd()
452 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { in mesh_start_cmd()
458 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
459 mr->error, mr->fifo_count)); in mesh_start_cmd()
461 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0) in mesh_start_cmd()
463 if (in_8(&mr->interrupt) != 0) { in mesh_start_cmd()
465 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
466 mr->error, mr->fifo_count)); in mesh_start_cmd()
473 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { in mesh_start_cmd()
486 out_8(&mr->dest_id, mr->source_id); in mesh_start_cmd()
500 out_8(&mr->sequence, SEQ_DISRESEL); in mesh_start_cmd()
501 if (in_8(&mr->interrupt) != 0) { in mesh_start_cmd()
503 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
504 mr->error, mr->fifo_count)); in mesh_start_cmd()
509 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
510 mr->error, mr->fifo_count)); in mesh_start_cmd()
513 out_8(&mr->sequence, SEQ_ARBITRATE); in mesh_start_cmd()
516 if (in_8(&mr->interrupt) != 0) in mesh_start_cmd()
521 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
522 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) in mesh_start_cmd()
523 && (in_8(&mr->bus_status0) & BS0_IO)) { in mesh_start_cmd()
526 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
527 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_start_cmd()
528 mesh_flush_io(mr); in mesh_start_cmd()
530 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_start_cmd()
531 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_start_cmd()
532 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_start_cmd()
533 mesh_flush_io(mr); in mesh_start_cmd()
534 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t) in mesh_start_cmd()
537 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
539 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) in mesh_start_cmd()
540 && (in_8(&mr->bus_status0) & BS0_IO)) { in mesh_start_cmd()
641 volatile struct mesh_regs __iomem *mr = ms->mesh; in set_sdtr() local
651 out_8(&mr->sync_params, ASYNC_PARAMS); in set_sdtr()
674 out_8(&mr->sync_params, tp->sync_params); in set_sdtr()
682 volatile struct mesh_regs __iomem *mr = ms->mesh; in start_phase() local
688 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence)); in start_phase()
689 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in start_phase()
696 out_8(&mr->count_hi, 0); in start_phase()
697 out_8(&mr->count_lo, 1); in start_phase()
698 out_8(&mr->sequence, SEQ_MSGIN + seq); in start_phase()
724 out_8(&mr->count_hi, 0); in start_phase()
725 out_8(&mr->sequence, SEQ_FLUSHFIFO); in start_phase()
726 mesh_flush_io(mr); in start_phase()
732 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) { in start_phase()
733 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0); in start_phase()
734 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */ in start_phase()
735 mesh_flush_io(mr); in start_phase()
737 out_8(&mr->count_lo, 1); in start_phase()
738 out_8(&mr->sequence, SEQ_MSGOUT + seq); in start_phase()
739 out_8(&mr->bus_status0, 0); /* release explicit ATN */ in start_phase()
740 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0); in start_phase()
751 out_8(&mr->count_lo, ms->n_msgout - 1); in start_phase()
752 out_8(&mr->sequence, SEQ_MSGOUT + seq); in start_phase()
754 out_8(&mr->fifo, ms->msgout[i]); in start_phase()
765 out_8(&mr->dest_id, ms->conn_tgt); in start_phase()
766 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN); in start_phase()
769 out_8(&mr->sync_params, tp->sync_params); in start_phase()
770 out_8(&mr->count_hi, 0); in start_phase()
772 out_8(&mr->count_lo, cmd->cmd_len); in start_phase()
773 out_8(&mr->sequence, SEQ_COMMAND + seq); in start_phase()
775 out_8(&mr->fifo, cmd->cmnd[i]); in start_phase()
777 out_8(&mr->count_lo, 6); in start_phase()
778 out_8(&mr->sequence, SEQ_COMMAND + seq); in start_phase()
780 out_8(&mr->fifo, 0); in start_phase()
796 out_8(&mr->count_lo, nb); in start_phase()
797 out_8(&mr->count_hi, nb >> 8); in start_phase()
798 out_8(&mr->sequence, (tp->data_goes_out? in start_phase()
802 out_8(&mr->count_hi, 0); in start_phase()
803 out_8(&mr->count_lo, 1); in start_phase()
804 out_8(&mr->sequence, SEQ_STATUS + seq); in start_phase()
808 out_8(&mr->sequence, SEQ_ENBRESEL); in start_phase()
809 mesh_flush_io(mr); in start_phase()
812 MKWORD(mr->interrupt, mr->exception, mr->error, in start_phase()
813 mr->fifo_count)); in start_phase()
814 out_8(&mr->sequence, SEQ_BUSFREE); in start_phase()
826 volatile struct mesh_regs __iomem *mr = ms->mesh; in get_msgin() local
829 n = mr->fifo_count; in get_msgin()
834 ms->msgin[i++] = in_8(&mr->fifo); in get_msgin()
858 volatile struct mesh_regs __iomem *mr = ms->mesh; in reselected() local
904 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) { in reselected()
907 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in reselected()
908 mesh_flush_io(mr); in reselected()
910 out_8(&mr->sequence, SEQ_ENBRESEL); in reselected()
911 mesh_flush_io(mr); in reselected()
914 MKWORD(0, mr->error, mr->exception, mr->fifo_count)); in reselected()
916 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in reselected()
917 mesh_flush_io(mr); in reselected()
919 out_8(&mr->sequence, SEQ_ENBRESEL); in reselected()
920 mesh_flush_io(mr); in reselected()
922 out_8(&mr->sync_params, ASYNC_PARAMS); in reselected()
927 if (in_8(&mr->fifo_count) == 0) { in reselected()
934 b = in_8(&mr->fifo); in reselected()
936 } while (in_8(&mr->fifo_count)); in reselected()
952 out_8(&mr->sync_params, tp->sync_params); in reselected()
965 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception)); in reselected()
991 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_reset() local
1011 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in handle_reset()
1012 out_8(&mr->sequence, SEQ_FLUSHFIFO); in handle_reset()
1013 mesh_flush_io(mr); in handle_reset()
1015 out_8(&mr->sync_params, ASYNC_PARAMS); in handle_reset()
1016 out_8(&mr->sequence, SEQ_ENBRESEL); in handle_reset()
1034 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_error() local
1036 err = in_8(&mr->error); in handle_error()
1037 exc = in_8(&mr->exception); in handle_error()
1038 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in handle_error()
1040 MKWORD(err, exc, mr->fifo_count, mr->count_lo)); in handle_error()
1045 while ((in_8(&mr->bus_status1) & BS1_RST) != 0) in handle_error()
1066 out_8(&mr->interrupt, INT_CMDDONE); in handle_error()
1086 count = (mr->count_hi << 8) + mr->count_lo; in handle_error()
1091 out_8(&mr->sequence, mr->sequence); in handle_error()
1117 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) { in handle_error()
1130 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_exception() local
1132 exc = in_8(&mr->exception); in handle_exception()
1133 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE); in handle_exception()
1324 volatile struct mesh_regs __iomem *mr = ms->mesh; in halt_dma() local
1331 while (t > 0 && in_8(&mr->fifo_count) != 0 in halt_dma()
1338 nb = (mr->count_hi << 8) + mr->count_lo; in halt_dma()
1340 MKWORD(0, mr->fifo_count, 0, nb)); in halt_dma()
1342 nb += mr->fifo_count; in halt_dma()
1369 volatile struct mesh_regs __iomem *mr = ms->mesh; in phase_mismatch() local
1373 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count)); in phase_mismatch()
1374 phase = in_8(&mr->bus_status0) & BS0_PHASE; in phase_mismatch()
1377 out_8(&mr->count_lo, 1); in phase_mismatch()
1378 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); in phase_mismatch()
1379 mesh_flush_io(mr); in phase_mismatch()
1381 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); in phase_mismatch()
1394 if (mr->fifo_count) { in phase_mismatch()
1395 out_8(&mr->sequence, SEQ_FLUSHFIFO); in phase_mismatch()
1396 mesh_flush_io(mr); in phase_mismatch()
1448 volatile struct mesh_regs __iomem *mr = ms->mesh; in cmd_complete() local
1453 dlog(ms, "cmd_complete fc=%x", mr->fifo_count); in cmd_complete()
1467 out_8(&mr->count_lo, n - ms->n_msgin); in cmd_complete()
1468 out_8(&mr->sequence, SEQ_MSGIN + seq); in cmd_complete()
1477 out_8(&mr->sequence, SEQ_FLUSHFIFO); in cmd_complete()
1478 mesh_flush_io(mr); in cmd_complete()
1480 out_8(&mr->count_lo, 1); in cmd_complete()
1481 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg); in cmd_complete()
1496 out_8(&mr->count_lo, 1); in cmd_complete()
1497 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN); in cmd_complete()
1499 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0) in cmd_complete()
1502 MKWORD(mr->error, mr->exception, in cmd_complete()
1503 mr->fifo_count, mr->count_lo)); in cmd_complete()
1504 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) { in cmd_complete()
1508 if (in_8(&mr->interrupt) & INT_ERROR) { in cmd_complete()
1510 in_8(&mr->error)); in cmd_complete()
1514 if (in_8(&mr->exception) != EXC_PHASEMM) in cmd_complete()
1516 in_8(&mr->exception)); in cmd_complete()
1519 in_8(&mr->bus_status0)); in cmd_complete()
1523 if (in_8(&mr->bus_status0) & BS0_REQ) { in cmd_complete()
1524 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); in cmd_complete()
1525 mesh_flush_io(mr); in cmd_complete()
1527 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); in cmd_complete()
1530 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN); in cmd_complete()
1572 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) { in cmd_complete()
1596 out_8(&mr->sequence, 0); in cmd_complete()
1597 out_8(&mr->interrupt, in cmd_complete()
1603 cmd->SCp.Status = mr->fifo; in cmd_complete()
1662 volatile struct mesh_regs __iomem *mr = ms->mesh; in DEF_SCSI_QCMD() local
1668 "phase=%d msgphase=%d\n", mr->bus_status0, in DEF_SCSI_QCMD()
1669 mr->interrupt, mr->exception, mr->error, in DEF_SCSI_QCMD()
1672 while ((intr = in_8(&mr->interrupt)) != 0) { in DEF_SCSI_QCMD()
1674 MKWORD(intr, mr->error, mr->exception, mr->sequence)); in DEF_SCSI_QCMD()
1680 out_8(&mr->interrupt, INT_CMDDONE); in DEF_SCSI_QCMD()
1710 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_host_reset() local
1723 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_host_reset()
1724 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_host_reset()
1725 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_host_reset()
1726 mesh_flush_io(mr); in mesh_host_reset()
1728 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_host_reset()
1729 out_8(&mr->source_id, ms->host->this_id); in mesh_host_reset()
1730 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_host_reset()
1731 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_host_reset()
1734 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_host_reset()
1735 mesh_flush_io(mr); in mesh_host_reset()
1737 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_host_reset()
1821 volatile struct mesh_regs __iomem *mr; in mesh_shutdown() local
1826 mr = ms->mesh; in mesh_shutdown()
1827 out_8(&mr->intr_mask, 0); in mesh_shutdown()
1828 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_shutdown()
1829 out_8(&mr->bus_status1, BS1_RST); in mesh_shutdown()
1830 mesh_flush_io(mr); in mesh_shutdown()
1832 out_8(&mr->bus_status1, 0); in mesh_shutdown()