Lines Matching refs:controller
156 static inline bool spi_qup_is_flag_set(struct spi_qup *controller, u32 flag) in spi_qup_is_flag_set() argument
158 u32 opflag = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_is_flag_set()
172 static inline unsigned int spi_qup_len(struct spi_qup *controller) in spi_qup_len() argument
174 return controller->n_words * controller->w_size; in spi_qup_len()
177 static inline bool spi_qup_is_valid_state(struct spi_qup *controller) in spi_qup_is_valid_state() argument
179 u32 opstate = readl_relaxed(controller->base + QUP_STATE); in spi_qup_is_valid_state()
184 static int spi_qup_set_state(struct spi_qup *controller, u32 state) in spi_qup_set_state() argument
190 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
199 dev_dbg(controller->dev, "invalid state for %ld,us %d\n", in spi_qup_set_state()
202 cur_state = readl_relaxed(controller->base + QUP_STATE); in spi_qup_set_state()
209 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
210 writel_relaxed(QUP_STATE_CLEAR, controller->base + QUP_STATE); in spi_qup_set_state()
214 writel_relaxed(cur_state, controller->base + QUP_STATE); in spi_qup_set_state()
218 while (!spi_qup_is_valid_state(controller)) { in spi_qup_set_state()
229 static void spi_qup_read_from_fifo(struct spi_qup *controller, u32 num_words) in spi_qup_read_from_fifo() argument
231 u8 *rx_buf = controller->rx_buf; in spi_qup_read_from_fifo()
237 word = readl_relaxed(controller->base + QUP_INPUT_FIFO); in spi_qup_read_from_fifo()
239 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_read_from_fifo()
240 controller->rx_bytes, in spi_qup_read_from_fifo()
241 controller->w_size); in spi_qup_read_from_fifo()
244 controller->rx_bytes += num_bytes; in spi_qup_read_from_fifo()
248 for (i = 0; i < num_bytes; i++, controller->rx_bytes++) { in spi_qup_read_from_fifo()
256 shift *= (controller->w_size - i - 1); in spi_qup_read_from_fifo()
257 rx_buf[controller->rx_bytes] = word >> shift; in spi_qup_read_from_fifo()
262 static void spi_qup_read(struct spi_qup *controller, u32 *opflags) in spi_qup_read() argument
265 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_read()
267 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->rx_bytes, in spi_qup_read()
268 controller->w_size); in spi_qup_read()
269 words_per_block = controller->in_blk_sz >> 2; in spi_qup_read()
274 controller->base + QUP_OPERATIONAL); in spi_qup_read()
283 if (!spi_qup_is_flag_set(controller, in spi_qup_read()
291 spi_qup_read_from_fifo(controller, num_words); in spi_qup_read()
296 if (is_block_mode && !spi_qup_is_flag_set(controller, in spi_qup_read()
310 *opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_read()
313 controller->base + QUP_OPERATIONAL); in spi_qup_read()
317 static void spi_qup_write_to_fifo(struct spi_qup *controller, u32 num_words) in spi_qup_write_to_fifo() argument
319 const u8 *tx_buf = controller->tx_buf; in spi_qup_write_to_fifo()
326 num_bytes = min_t(int, spi_qup_len(controller) - in spi_qup_write_to_fifo()
327 controller->tx_bytes, in spi_qup_write_to_fifo()
328 controller->w_size); in spi_qup_write_to_fifo()
331 data = tx_buf[controller->tx_bytes + i]; in spi_qup_write_to_fifo()
335 controller->tx_bytes += num_bytes; in spi_qup_write_to_fifo()
337 writel_relaxed(word, controller->base + QUP_OUTPUT_FIFO); in spi_qup_write_to_fifo()
348 static void spi_qup_write(struct spi_qup *controller) in spi_qup_write() argument
350 bool is_block_mode = controller->mode == QUP_IO_M_MODE_BLOCK; in spi_qup_write()
353 remainder = DIV_ROUND_UP(spi_qup_len(controller) - controller->tx_bytes, in spi_qup_write()
354 controller->w_size); in spi_qup_write()
355 words_per_block = controller->out_blk_sz >> 2; in spi_qup_write()
360 controller->base + QUP_OPERATIONAL); in spi_qup_write()
370 if (spi_qup_is_flag_set(controller, in spi_qup_write()
377 spi_qup_write_to_fifo(controller, num_words); in spi_qup_write()
382 if (is_block_mode && !spi_qup_is_flag_set(controller, in spi_qup_write()
579 static bool spi_qup_data_pending(struct spi_qup *controller) in spi_qup_data_pending() argument
583 remainder_tx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
584 controller->tx_bytes, controller->w_size); in spi_qup_data_pending()
586 remainder_rx = DIV_ROUND_UP(spi_qup_len(controller) - in spi_qup_data_pending()
587 controller->rx_bytes, controller->w_size); in spi_qup_data_pending()
594 struct spi_qup *controller = dev_id; in spi_qup_qup_irq() local
599 qup_err = readl_relaxed(controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
600 spi_err = readl_relaxed(controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
601 opflags = readl_relaxed(controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
603 writel_relaxed(qup_err, controller->base + QUP_ERROR_FLAGS); in spi_qup_qup_irq()
604 writel_relaxed(spi_err, controller->base + SPI_ERROR_FLAGS); in spi_qup_qup_irq()
608 dev_warn(controller->dev, "OUTPUT_OVER_RUN\n"); in spi_qup_qup_irq()
610 dev_warn(controller->dev, "INPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
612 dev_warn(controller->dev, "OUTPUT_UNDER_RUN\n"); in spi_qup_qup_irq()
614 dev_warn(controller->dev, "INPUT_OVER_RUN\n"); in spi_qup_qup_irq()
621 dev_warn(controller->dev, "CLK_OVER_RUN\n"); in spi_qup_qup_irq()
623 dev_warn(controller->dev, "CLK_UNDER_RUN\n"); in spi_qup_qup_irq()
628 spin_lock_irqsave(&controller->lock, flags); in spi_qup_qup_irq()
629 if (!controller->error) in spi_qup_qup_irq()
630 controller->error = error; in spi_qup_qup_irq()
631 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_qup_irq()
633 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
634 writel_relaxed(opflags, controller->base + QUP_OPERATIONAL); in spi_qup_qup_irq()
637 spi_qup_read(controller, &opflags); in spi_qup_qup_irq()
640 spi_qup_write(controller); in spi_qup_qup_irq()
642 if (!spi_qup_data_pending(controller)) in spi_qup_qup_irq()
643 complete(&controller->done); in spi_qup_qup_irq()
647 complete(&controller->done); in spi_qup_qup_irq()
650 if (!spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_qup_irq()
651 if (spi_qup_data_pending(controller)) in spi_qup_qup_irq()
654 complete(&controller->done); in spi_qup_qup_irq()
663 struct spi_qup *controller = spi_master_get_devdata(spi->master); in spi_qup_io_prep() local
666 if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) { in spi_qup_io_prep()
667 dev_err(controller->dev, "too big size for loopback %d > %d\n", in spi_qup_io_prep()
668 xfer->len, controller->in_fifo_sz); in spi_qup_io_prep()
672 ret = clk_set_rate(controller->cclk, xfer->speed_hz); in spi_qup_io_prep()
674 dev_err(controller->dev, "fail to set frequency %d", in spi_qup_io_prep()
679 controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8); in spi_qup_io_prep()
680 controller->n_words = xfer->len / controller->w_size; in spi_qup_io_prep()
682 if (controller->n_words <= (controller->in_fifo_sz / sizeof(u32))) in spi_qup_io_prep()
683 controller->mode = QUP_IO_M_MODE_FIFO; in spi_qup_io_prep()
687 controller->mode = QUP_IO_M_MODE_BAM; in spi_qup_io_prep()
689 controller->mode = QUP_IO_M_MODE_BLOCK; in spi_qup_io_prep()
697 struct spi_qup *controller = spi_master_get_devdata(spi->master); in spi_qup_io_config() local
701 spin_lock_irqsave(&controller->lock, flags); in spi_qup_io_config()
702 controller->xfer = xfer; in spi_qup_io_config()
703 controller->error = 0; in spi_qup_io_config()
704 controller->rx_bytes = 0; in spi_qup_io_config()
705 controller->tx_bytes = 0; in spi_qup_io_config()
706 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_io_config()
709 if (spi_qup_set_state(controller, QUP_STATE_RESET)) { in spi_qup_io_config()
710 dev_err(controller->dev, "cannot set RESET state\n"); in spi_qup_io_config()
714 switch (controller->mode) { in spi_qup_io_config()
716 writel_relaxed(controller->n_words, in spi_qup_io_config()
717 controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
718 writel_relaxed(controller->n_words, in spi_qup_io_config()
719 controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
721 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
722 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
725 writel_relaxed(controller->n_words, in spi_qup_io_config()
726 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
727 writel_relaxed(controller->n_words, in spi_qup_io_config()
728 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
730 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
731 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
733 if (!controller->qup_v1) { in spi_qup_io_config()
736 input_cnt = controller->base + QUP_MX_INPUT_CNT; in spi_qup_io_config()
746 writel_relaxed(controller->n_words, input_cnt); in spi_qup_io_config()
748 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
752 reinit_completion(&controller->done); in spi_qup_io_config()
753 writel_relaxed(controller->n_words, in spi_qup_io_config()
754 controller->base + QUP_MX_INPUT_CNT); in spi_qup_io_config()
755 writel_relaxed(controller->n_words, in spi_qup_io_config()
756 controller->base + QUP_MX_OUTPUT_CNT); in spi_qup_io_config()
758 writel_relaxed(0, controller->base + QUP_MX_READ_CNT); in spi_qup_io_config()
759 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT); in spi_qup_io_config()
762 dev_err(controller->dev, "unknown mode = %d\n", in spi_qup_io_config()
763 controller->mode); in spi_qup_io_config()
767 iomode = readl_relaxed(controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
771 if (!spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
776 iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
777 iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT); in spi_qup_io_config()
779 writel_relaxed(iomode, controller->base + QUP_IO_M_MODES); in spi_qup_io_config()
781 control = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
788 writel_relaxed(control, controller->base + SPI_IO_CONTROL); in spi_qup_io_config()
790 config = readl_relaxed(controller->base + SPI_CONFIG); in spi_qup_io_config()
811 writel_relaxed(config, controller->base + SPI_CONFIG); in spi_qup_io_config()
813 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_io_config()
818 if (spi_qup_is_dma_xfer(controller->mode)) { in spi_qup_io_config()
825 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_io_config()
828 if (!controller->qup_v1) { in spi_qup_io_config()
836 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_io_config()
839 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK); in spi_qup_io_config()
849 struct spi_qup *controller = spi_master_get_devdata(master); in spi_qup_transfer_one() local
862 reinit_completion(&controller->done); in spi_qup_transfer_one()
864 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
865 controller->xfer = xfer; in spi_qup_transfer_one()
866 controller->error = 0; in spi_qup_transfer_one()
867 controller->rx_bytes = 0; in spi_qup_transfer_one()
868 controller->tx_bytes = 0; in spi_qup_transfer_one()
869 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
871 if (spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
876 spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_transfer_one()
877 spin_lock_irqsave(&controller->lock, flags); in spi_qup_transfer_one()
879 ret = controller->error; in spi_qup_transfer_one()
880 spin_unlock_irqrestore(&controller->lock, flags); in spi_qup_transfer_one()
882 if (ret && spi_qup_is_dma_xfer(controller->mode)) in spi_qup_transfer_one()
979 struct spi_qup *controller; in spi_qup_set_cs() local
983 controller = spi_master_get_devdata(spi->master); in spi_qup_set_cs()
984 spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
992 writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL); in spi_qup_set_cs()
999 struct spi_qup *controller; in spi_qup_probe() local
1073 controller = spi_master_get_devdata(master); in spi_qup_probe()
1075 controller->dev = dev; in spi_qup_probe()
1076 controller->base = base; in spi_qup_probe()
1077 controller->iclk = iclk; in spi_qup_probe()
1078 controller->cclk = cclk; in spi_qup_probe()
1079 controller->irq = irq; in spi_qup_probe()
1087 controller->qup_v1 = (uintptr_t)of_device_get_match_data(dev); in spi_qup_probe()
1089 if (!controller->qup_v1) in spi_qup_probe()
1092 spin_lock_init(&controller->lock); in spi_qup_probe()
1093 init_completion(&controller->done); in spi_qup_probe()
1099 controller->out_blk_sz = size * 16; in spi_qup_probe()
1101 controller->out_blk_sz = 4; in spi_qup_probe()
1105 controller->in_blk_sz = size * 16; in spi_qup_probe()
1107 controller->in_blk_sz = 4; in spi_qup_probe()
1110 controller->out_fifo_sz = controller->out_blk_sz * (2 << size); in spi_qup_probe()
1113 controller->in_fifo_sz = controller->in_blk_sz * (2 << size); in spi_qup_probe()
1116 controller->in_blk_sz, controller->in_fifo_sz, in spi_qup_probe()
1117 controller->out_blk_sz, controller->out_fifo_sz); in spi_qup_probe()
1121 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_probe()
1130 if (!controller->qup_v1) in spi_qup_probe()
1137 if (controller->qup_v1) in spi_qup_probe()
1146 IRQF_TRIGGER_HIGH, pdev->name, controller); in spi_qup_probe()
1176 struct spi_qup *controller = spi_master_get_devdata(master); in spi_qup_pm_suspend_runtime() local
1180 config = readl(controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1182 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_suspend_runtime()
1184 clk_disable_unprepare(controller->cclk); in spi_qup_pm_suspend_runtime()
1185 clk_disable_unprepare(controller->iclk); in spi_qup_pm_suspend_runtime()
1193 struct spi_qup *controller = spi_master_get_devdata(master); in spi_qup_pm_resume_runtime() local
1197 ret = clk_prepare_enable(controller->iclk); in spi_qup_pm_resume_runtime()
1201 ret = clk_prepare_enable(controller->cclk); in spi_qup_pm_resume_runtime()
1203 clk_disable_unprepare(controller->iclk); in spi_qup_pm_resume_runtime()
1208 config = readl_relaxed(controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1210 writel_relaxed(config, controller->base + QUP_CONFIG); in spi_qup_pm_resume_runtime()
1219 struct spi_qup *controller = spi_master_get_devdata(master); in spi_qup_suspend() local
1231 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_suspend()
1235 clk_disable_unprepare(controller->cclk); in spi_qup_suspend()
1236 clk_disable_unprepare(controller->iclk); in spi_qup_suspend()
1243 struct spi_qup *controller = spi_master_get_devdata(master); in spi_qup_resume() local
1246 ret = clk_prepare_enable(controller->iclk); in spi_qup_resume()
1250 ret = clk_prepare_enable(controller->cclk); in spi_qup_resume()
1252 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1256 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_resume()
1267 clk_disable_unprepare(controller->cclk); in spi_qup_resume()
1268 clk_disable_unprepare(controller->iclk); in spi_qup_resume()
1276 struct spi_qup *controller = spi_master_get_devdata(master); in spi_qup_remove() local
1283 ret = spi_qup_set_state(controller, QUP_STATE_RESET); in spi_qup_remove()
1289 clk_disable_unprepare(controller->cclk); in spi_qup_remove()
1290 clk_disable_unprepare(controller->iclk); in spi_qup_remove()