233 static void rp2_rmw(struct rp2_uart_port *up, int reg,  in rp2_rmw()  argument
236 	u32 tmp = readl(up->base + reg);  in rp2_rmw()
239 	writel(tmp, up->base + reg);  in rp2_rmw()
242 static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val)  in rp2_rmw_clr()  argument
244 	rp2_rmw(up, reg, val, 0);  in rp2_rmw_clr()
247 static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val)  in rp2_rmw_set()  argument
249 	rp2_rmw(up, reg, 0, val);  in rp2_rmw_set()
252 static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num,  in rp2_mask_ch_irq()  argument
257 	spin_lock_irqsave(&up->card->card_lock, flags);  in rp2_mask_ch_irq()
259 	irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK);  in rp2_mask_ch_irq()
264 	writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);  in rp2_mask_ch_irq()
266 	spin_unlock_irqrestore(&up->card->card_lock, flags);  in rp2_mask_ch_irq()
271 	struct rp2_uart_port *up = port_to_up(port);  in rp2_uart_tx_empty()  local
279 	spin_lock_irqsave(&up->port.lock, flags);  in rp2_uart_tx_empty()
280 	tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT);  in rp2_uart_tx_empty()
281 	spin_unlock_irqrestore(&up->port.lock, flags);  in rp2_uart_tx_empty()
288 	struct rp2_uart_port *up = port_to_up(port);  in rp2_uart_get_mctrl()  local
291 	status = readl(up->base + RP2_CHAN_STAT);  in rp2_uart_get_mctrl()
337 static void __rp2_uart_set_termios(struct rp2_uart_port *up,  in __rp2_uart_set_termios()  argument
343 	writew(baud_div - 1, up->base + RP2_BAUD);  in __rp2_uart_set_termios()
346 	rp2_rmw(up, RP2_UART_CTL,  in __rp2_uart_set_termios()
355 	rp2_rmw(up, RP2_TXRX_CTL,  in __rp2_uart_set_termios()
368 	       up->ucode + RP2_TX_SWFLOW);  in __rp2_uart_set_termios()
370 	       up->ucode + RP2_RX_SWFLOW);  in __rp2_uart_set_termios()
377 	struct rp2_uart_port *up = port_to_up(port);  in rp2_uart_set_termios()  local
392 	__rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div);  in rp2_uart_set_termios()
398 static void rp2_rx_chars(struct rp2_uart_port *up)  in rp2_rx_chars()  argument
400 	u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT);  in rp2_rx_chars()
401 	struct tty_port *port = &up->port.state->port;  in rp2_rx_chars()
404 		u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ;  in rp2_rx_chars()
408 			if (!uart_handle_sysrq_char(&up->port, ch))  in rp2_rx_chars()
409 				uart_insert_char(&up->port, byte, 0, ch,  in rp2_rx_chars()
420 			uart_insert_char(&up->port, byte,  in rp2_rx_chars()
423 		up->port.icount.rx++;  in rp2_rx_chars()
426 	spin_unlock(&up->port.lock);  in rp2_rx_chars()
428 	spin_lock(&up->port.lock);  in rp2_rx_chars()
431 static void rp2_tx_chars(struct rp2_uart_port *up)  in rp2_tx_chars()  argument
433 	u16 max_tx = FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT);  in rp2_tx_chars()
434 	struct circ_buf *xmit = &up->port.state->xmit;  in rp2_tx_chars()
436 	if (uart_tx_stopped(&up->port)) {  in rp2_tx_chars()
437 		rp2_uart_stop_tx(&up->port);  in rp2_tx_chars()
442 		if (up->port.x_char) {  in rp2_tx_chars()
443 			writeb(up->port.x_char, up->base + RP2_DATA_BYTE);  in rp2_tx_chars()
444 			up->port.x_char = 0;  in rp2_tx_chars()
445 			up->port.icount.tx++;  in rp2_tx_chars()
449 			rp2_uart_stop_tx(&up->port);  in rp2_tx_chars()
452 		writeb(xmit->buf[xmit->tail], up->base + RP2_DATA_BYTE);  in rp2_tx_chars()
454 		up->port.icount.tx++;  in rp2_tx_chars()
458 		uart_write_wakeup(&up->port);  in rp2_tx_chars()
461 static void rp2_ch_interrupt(struct rp2_uart_port *up)  in rp2_ch_interrupt()  argument
465 	spin_lock(&up->port.lock);  in rp2_ch_interrupt()
471 	status = readl(up->base + RP2_CHAN_STAT);  in rp2_ch_interrupt()
472 	writel(status, up->base + RP2_CHAN_STAT);  in rp2_ch_interrupt()
475 		rp2_rx_chars(up);  in rp2_ch_interrupt()
477 		rp2_tx_chars(up);  in rp2_ch_interrupt()
479 		wake_up_interruptible(&up->port.state->port.delta_msr_wait);  in rp2_ch_interrupt()
481 	spin_unlock(&up->port.lock);  in rp2_ch_interrupt()
510 static inline void rp2_flush_fifos(struct rp2_uart_port *up)  in rp2_flush_fifos()  argument
512 	rp2_rmw_set(up, RP2_UART_CTL,  in rp2_flush_fifos()
514 	readl(up->base + RP2_UART_CTL);  in rp2_flush_fifos()
516 	rp2_rmw_clr(up, RP2_UART_CTL,  in rp2_flush_fifos()
522 	struct rp2_uart_port *up = port_to_up(port);  in rp2_uart_startup()  local
524 	rp2_flush_fifos(up);  in rp2_uart_startup()
525 	rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m);  in rp2_uart_startup()
526 	rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m,  in rp2_uart_startup()
528 	rp2_rmw(up, RP2_CHAN_STAT, 0, 0);  in rp2_uart_startup()
529 	rp2_mask_ch_irq(up, up->idx, 1);  in rp2_uart_startup()
536 	struct rp2_uart_port *up = port_to_up(port);  in rp2_uart_shutdown()  local
542 	rp2_mask_ch_irq(up, up->idx, 0);  in rp2_uart_shutdown()
543 	rp2_rmw(up, RP2_CHAN_STAT, 0, 0);  in rp2_uart_shutdown()
629 static void rp2_init_port(struct rp2_uart_port *up, const struct firmware *fw)  in rp2_init_port()  argument
633 	writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);  in rp2_init_port()
634 	readl(up->base + RP2_UART_CTL);  in rp2_init_port()
637 	writel(0, up->base + RP2_TXRX_CTL);  in rp2_init_port()
638 	writel(0, up->base + RP2_UART_CTL);  in rp2_init_port()
639 	readl(up->base + RP2_UART_CTL);  in rp2_init_port()
642 	rp2_flush_fifos(up);  in rp2_init_port()
645 		writeb(fw->data[i], up->ucode + i);  in rp2_init_port()
647 	__rp2_uart_set_termios(up, CS8 | CREAD | CLOCAL, 0, DEFAULT_BAUD_DIV);  in rp2_init_port()
648 	rp2_uart_set_mctrl(&up->port, 0);  in rp2_init_port()
650 	writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO);  in rp2_init_port()
651 	rp2_rmw(up, RP2_UART_CTL, RP2_UART_CTL_MODE_m,  in rp2_init_port()
653 	rp2_rmw_set(up, RP2_TXRX_CTL,  in rp2_init_port()