Lines Matching full:layout
46 * format and data layout of the buffer, and should be the only way to describe
49 * Having multiple fourcc:modifier pairs which describe the same layout should
206 * then V), but the exact Linear layout is undefined.
353 * When adding a new token please document the layout with a code comment,
369 * In future cases where a generic layout is identified before merging with a
393 * Linear Layout
395 * Just plain linear layout. Note that this is different from no specifying any
405 * Intel X-tiling layout
407 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
408 * in row-major layout. Within the tile bytes are laid out row-major, with
412 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
415 * identify the layout in a simple way for i915-specific userspace, which
422 * Intel Y-tiling layout
424 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
425 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
430 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
433 * identify the layout in a simple way for i915-specific userspace, which
440 * Intel Yf-tiling layout
442 * This is a tiled layout using 4Kb tiles in row-major layout.
444 * are arranged in four groups (two wide, two high) with column-major layout.
516 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
517 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
538 * Vivante 4x4 tiling layout
540 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
541 * layout.
546 * Vivante 64x64 super-tiling layout
548 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
550 * major layout.
558 * Vivante 4x4 tiling layout for dual-pipe
560 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
562 * compared to the non-split tiled layout.
567 * Vivante 64x64 super-tiling layout for dual-pipe
569 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
571 * therefore halved compared to the non-split super-tiled layout.
578 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
585 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
588 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
605 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
622 * tables of all GPUs >= NV50. It affects the exact layout of bits
630 * since the modifier should define the layout of the associated
636 * kind and bit layout has changed at various points.
643 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
645 * page kind and block linear swizzles. This causes the layout of
649 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
650 * 1 = Desktop GPU and Tegra Xavier+ Layout
655 * 1 = ROP/3D, layout 1, exact compression format implied by Page
657 * 2 = ROP/3D, layout 2, exact compression format implied by Page
675 /* To grandfather in prior block linear format modifiers to the above layout,
691 * 16Bx2 Block Linear layout, used by Tegra K1 and later
747 * This is the primary layout that the V3D GPU can texture from (it
899 * AFBC sparse layout
920 * AFBC tiled layout
922 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
926 * When the tiled layout is used, the buffer size (in pixels) must be aligned
942 * Indicates that the buffer is allocated in a layout safe for front-buffer
959 * The buffer layout is the same as for AFBC buffers without USM set, this only
1005 * The first 8 bits of the mode defines the layout, then the following 8 bits
1006 * defines the options changing the layout.
1009 * combinations of layout and options.
1024 * Amlogic FBC Basic Layout
1026 * The basic layout is composed of:
1031 * This layout is transferrable between Amlogic SoCs supporting this modifier.
1036 * Amlogic FBC Scatter Memory layout
1039 * frames content to optimize memory access and layout.
1046 * Due to the nature of the layout, these buffers are not expected to
1055 /* Amlogic FBC Layout Options Bit Mask */
1064 * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1065 * the basic layout and 3200 bytes per 64x32 superblock combined with
1066 * the scatter layout.