Lines Matching refs:AddrSurfInfoIn
632 bool compressed, ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn, in gfx6_compute_level() argument
643 AddrSurfInfoIn->mipLevel = level; in gfx6_compute_level()
644 AddrSurfInfoIn->width = u_minify(config->info.width, level); in gfx6_compute_level()
645 AddrSurfInfoIn->height = u_minify(config->info.height, level); in gfx6_compute_level()
650 if (config->info.levels == 1 && AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED && in gfx6_compute_level()
651 AddrSurfInfoIn->bpp && util_is_power_of_two_or_zero(AddrSurfInfoIn->bpp)) { in gfx6_compute_level()
652 unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8); in gfx6_compute_level()
654 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment); in gfx6_compute_level()
659 if (AddrSurfInfoIn->bpp == 96) { in gfx6_compute_level()
661 assert(AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED); in gfx6_compute_level()
665 AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, 16); in gfx6_compute_level()
669 AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level); in gfx6_compute_level()
671 AddrSurfInfoIn->numSlices = 6; in gfx6_compute_level()
673 AddrSurfInfoIn->numSlices = config->info.array_size; in gfx6_compute_level()
679 AddrSurfInfoIn->basePitch = surf->u.legacy.zs.stencil_level[0].nblk_x; in gfx6_compute_level()
681 AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x; in gfx6_compute_level()
685 AddrSurfInfoIn->basePitch *= surf->blk_w; in gfx6_compute_level()
688 ret = AddrComputeSurfaceInfo(addrlib, AddrSurfInfoIn, AddrSurfInfoOut); in gfx6_compute_level()
721 if (AddrSurfInfoIn->flags.prt) { in gfx6_compute_level()
737 if (!AddrSurfInfoIn->flags.depth && !AddrSurfInfoIn->flags.stencil) in gfx6_compute_level()
741 if (AddrSurfInfoIn->flags.dccCompatible && (level == 0 || AddrDccOut->subLvlCompressible)) { in gfx6_compute_level()
817 if (!is_stencil && AddrSurfInfoIn->flags.depth && surf_level->mode == RADEON_SURF_MODE_2D && in gfx6_compute_level()
1026 ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0}; in gfx6_compute_surface() local
1036 AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT); in gfx6_compute_surface()
1057 AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED; in gfx6_compute_surface()
1061 AddrSurfInfoIn.tileMode = ADDR_TM_PRT_TILED_THIN1; in gfx6_compute_surface()
1063 AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1; in gfx6_compute_surface()
1067 AddrSurfInfoIn.tileMode = ADDR_TM_PRT_2D_TILED_THIN1; in gfx6_compute_surface()
1069 AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1; in gfx6_compute_surface()
1081 AddrSurfInfoIn.format = ADDR_FMT_BC1; in gfx6_compute_surface()
1084 AddrSurfInfoIn.format = ADDR_FMT_BC3; in gfx6_compute_surface()
1090 AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8; in gfx6_compute_surface()
1093 AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples); in gfx6_compute_surface()
1094 AddrSurfInfoIn.tileIndex = -1; in gfx6_compute_surface()
1097 AddrDccIn.numSamples = AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples); in gfx6_compute_surface()
1102 AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE; in gfx6_compute_surface()
1104 AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER; in gfx6_compute_surface()
1106 AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE; in gfx6_compute_surface()
1108 AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER); in gfx6_compute_surface()
1109 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0; in gfx6_compute_surface()
1110 AddrSurfInfoIn.flags.cube = config->is_cube; in gfx6_compute_surface()
1111 AddrSurfInfoIn.flags.display = get_display_flag(config, surf); in gfx6_compute_surface()
1112 AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1; in gfx6_compute_surface()
1113 AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0; in gfx6_compute_surface()
1114 AddrSurfInfoIn.flags.prt = (surf->flags & RADEON_SURF_PRT) != 0; in gfx6_compute_surface()
1119 AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible && in gfx6_compute_surface()
1120 !AddrSurfInfoIn.flags.fmask && config->info.samples <= 1 && in gfx6_compute_surface()
1129 AddrSurfInfoIn.flags.dccCompatible = in gfx6_compute_surface()
1135 AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0; in gfx6_compute_surface()
1136 AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER); in gfx6_compute_surface()
1157 if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil && in gfx6_compute_surface()
1162 AddrSurfInfoIn.flags.matchStencilTileCfg = 1; in gfx6_compute_surface()
1165 AddrSurfInfoIn.flags.noStencil = 1; in gfx6_compute_surface()
1171 AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 && surf->u.legacy.bankw && in gfx6_compute_surface()
1181 AddrSurfInfoIn.flags.opt4Space = 0; in gfx6_compute_surface()
1182 AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn; in gfx6_compute_surface()
1193 assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1); in gfx6_compute_surface()
1196 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) { in gfx6_compute_surface()
1198 AddrSurfInfoIn.tileIndex = 11; /* 16bpp */ in gfx6_compute_surface()
1200 AddrSurfInfoIn.tileIndex = 12; /* 32bpp */ in gfx6_compute_surface()
1203 AddrSurfInfoIn.tileIndex = 14; /* 8bpp */ in gfx6_compute_surface()
1205 AddrSurfInfoIn.tileIndex = 15; /* 16bpp */ in gfx6_compute_surface()
1207 AddrSurfInfoIn.tileIndex = 16; /* 32bpp */ in gfx6_compute_surface()
1209 AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */ in gfx6_compute_surface()
1213 if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) in gfx6_compute_surface()
1214 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */ in gfx6_compute_surface()
1216 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */ in gfx6_compute_surface()
1236 r = gfx6_compute_level(addrlib, config, surf, false, level, compressed, &AddrSurfInfoIn, in gfx6_compute_surface()
1246 AddrSurfInfoIn.flags.tcCompatible = 0; in gfx6_compute_surface()
1250 if (AddrSurfInfoIn.flags.matchStencilTileCfg) { in gfx6_compute_surface()
1251 AddrSurfInfoIn.flags.matchStencilTileCfg = 0; in gfx6_compute_surface()
1252 AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex; in gfx6_compute_surface()
1266 AddrSurfInfoIn.tileIndex = stencil_tile_idx; in gfx6_compute_surface()
1267 AddrSurfInfoIn.bpp = 8; in gfx6_compute_surface()
1268 AddrSurfInfoIn.flags.depth = 0; in gfx6_compute_surface()
1269 AddrSurfInfoIn.flags.stencil = 1; in gfx6_compute_surface()
1270 AddrSurfInfoIn.flags.tcCompatible = 0; in gfx6_compute_surface()
1275 r = gfx6_compute_level(addrlib, config, surf, true, level, compressed, &AddrSurfInfoIn, in gfx6_compute_surface()
1304 if (config->info.samples >= 2 && AddrSurfInfoIn.flags.color && info->has_graphics && in gfx6_compute_surface()
1316 fin.numSlices = AddrSurfInfoIn.numSlices; in gfx6_compute_surface()
1317 fin.numSamples = AddrSurfInfoIn.numSamples; in gfx6_compute_surface()
1318 fin.numFrags = AddrSurfInfoIn.numFrags; in gfx6_compute_surface()
2139 ADDR2_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0}; in gfx9_compute_surface() local
2142 AddrSurfInfoIn.size = sizeof(ADDR2_COMPUTE_SURFACE_INFO_INPUT); in gfx9_compute_surface()
2151 AddrSurfInfoIn.format = ADDR_FMT_BC1; in gfx9_compute_surface()
2154 AddrSurfInfoIn.format = ADDR_FMT_BC3; in gfx9_compute_surface()
2163 AddrSurfInfoIn.format = ADDR_FMT_8; in gfx9_compute_surface()
2167 AddrSurfInfoIn.format = ADDR_FMT_16; in gfx9_compute_surface()
2171 AddrSurfInfoIn.format = ADDR_FMT_32; in gfx9_compute_surface()
2175 AddrSurfInfoIn.format = ADDR_FMT_32_32; in gfx9_compute_surface()
2179 AddrSurfInfoIn.format = ADDR_FMT_32_32_32; in gfx9_compute_surface()
2183 AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32; in gfx9_compute_surface()
2188 AddrSurfInfoIn.bpp = surf->bpe * 8; in gfx9_compute_surface()
2192 AddrSurfInfoIn.flags.color = is_color_surface && !(surf->flags & RADEON_SURF_NO_RENDER_TARGET); in gfx9_compute_surface()
2193 AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0; in gfx9_compute_surface()
2194 AddrSurfInfoIn.flags.display = get_display_flag(config, surf); in gfx9_compute_surface()
2196 AddrSurfInfoIn.flags.texture = is_color_surface || surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE; in gfx9_compute_surface()
2197 AddrSurfInfoIn.flags.opt4space = 1; in gfx9_compute_surface()
2198 AddrSurfInfoIn.flags.prt = (surf->flags & RADEON_SURF_PRT) != 0; in gfx9_compute_surface()
2200 AddrSurfInfoIn.numMipLevels = config->info.levels; in gfx9_compute_surface()
2201 AddrSurfInfoIn.numSamples = MAX2(1, config->info.samples); in gfx9_compute_surface()
2202 AddrSurfInfoIn.numFrags = AddrSurfInfoIn.numSamples; in gfx9_compute_surface()
2205 AddrSurfInfoIn.numFrags = MAX2(1, config->info.storage_samples); in gfx9_compute_surface()
2211 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D; in gfx9_compute_surface()
2213 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D; in gfx9_compute_surface()
2215 AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D; in gfx9_compute_surface()
2217 AddrSurfInfoIn.width = config->info.width; in gfx9_compute_surface()
2218 AddrSurfInfoIn.height = config->info.height; in gfx9_compute_surface()
2221 AddrSurfInfoIn.numSlices = config->info.depth; in gfx9_compute_surface()
2223 AddrSurfInfoIn.numSlices = 6; in gfx9_compute_surface()
2225 AddrSurfInfoIn.numSlices = config->info.array_size; in gfx9_compute_surface()
2228 AddrSurfInfoIn.flags.metaPipeUnaligned = 0; in gfx9_compute_surface()
2229 AddrSurfInfoIn.flags.metaRbUnaligned = 0; in gfx9_compute_surface()
2232 ac_modifier_fill_dcc_params(surf->modifier, surf, &AddrSurfInfoIn); in gfx9_compute_surface()
2233 } else if (!AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.stencil) { in gfx9_compute_surface()
2248 if (AddrSurfInfoIn.flags.display) { in gfx9_compute_surface()
2257 AddrSurfInfoIn.flags.metaPipeUnaligned = 1; in gfx9_compute_surface()
2258 AddrSurfInfoIn.flags.metaRbUnaligned = 1; in gfx9_compute_surface()
2294 AddrSurfInfoIn.swizzleMode = ADDR_SW_LINEAR; in gfx9_compute_surface()
2301 AddrSurfInfoIn.swizzleMode = surf->u.gfx9.swizzle_mode; in gfx9_compute_surface()
2305 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false, in gfx9_compute_surface()
2306 &AddrSurfInfoIn.swizzleMode); in gfx9_compute_surface()
2321 AddrSurfInfoIn.swizzleMode = ac_modifier_gfx9_swizzle_mode(surf->modifier); in gfx9_compute_surface()
2324 surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType; in gfx9_compute_surface()
2333 if (AddrSurfInfoIn.flags.stencil) in gfx9_compute_surface()
2342 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn); in gfx9_compute_surface()
2349 AddrSurfInfoIn.flags.stencil = 1; in gfx9_compute_surface()
2350 AddrSurfInfoIn.bpp = 8; in gfx9_compute_surface()
2351 AddrSurfInfoIn.format = ADDR_FMT_8; in gfx9_compute_surface()
2353 if (!AddrSurfInfoIn.flags.depth) { in gfx9_compute_surface()
2354 r = gfx9_get_preferred_swizzle_mode(addrlib->handle, info, surf, &AddrSurfInfoIn, false, in gfx9_compute_surface()
2355 &AddrSurfInfoIn.swizzleMode); in gfx9_compute_surface()
2359 AddrSurfInfoIn.flags.depth = 0; in gfx9_compute_surface()
2361 r = gfx9_compute_miptree(addrlib, info, config, surf, compressed, &AddrSurfInfoIn); in gfx9_compute_surface()
2389 assert(!AddrSurfInfoIn.flags.display || surf->is_displayable); in gfx9_compute_surface()
2394 if (AddrSurfInfoIn.flags.color) in gfx9_compute_surface()
2396 if (AddrSurfInfoIn.flags.display && surf->modifier == DRM_FORMAT_MOD_INVALID) { in gfx9_compute_surface()
2403 AddrSurfInfoIn.flags.color && !surf->is_linear && in gfx9_compute_surface()
2412 AddrSurfInfoIn.flags.display && surf->bpe == 4) { in gfx9_compute_surface()
2417 if (!AddrSurfInfoIn.flags.display) in gfx9_compute_surface()