1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE 23 * 24 ***********************************************************************************************************************/ 25 26 /** 27 **************************************************************************************************** 28 * @file addrlib.h 29 * @brief Contains the Addr::Lib base class definition. 30 **************************************************************************************************** 31 */ 32 33 #ifndef __ADDR_LIB_H__ 34 #define __ADDR_LIB_H__ 35 36 #include "addrinterface.h" 37 #include "addrobject.h" 38 #include "addrelemlib.h" 39 40 #include "amdgpu_asic_addr.h" 41 42 #ifndef CIASICIDGFXENGINE_R600 43 #define CIASICIDGFXENGINE_R600 0x00000006 44 #endif 45 46 #ifndef CIASICIDGFXENGINE_R800 47 #define CIASICIDGFXENGINE_R800 0x00000008 48 #endif 49 50 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND 51 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A 52 #endif 53 54 #ifndef CIASICIDGFXENGINE_ARCTICISLAND 55 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D 56 #endif 57 58 namespace Addr 59 { 60 61 /** 62 **************************************************************************************************** 63 * @brief Neutral enums that define pipeinterleave 64 **************************************************************************************************** 65 */ 66 enum PipeInterleave 67 { 68 ADDR_PIPEINTERLEAVE_256B = 256, 69 ADDR_PIPEINTERLEAVE_512B = 512, 70 ADDR_PIPEINTERLEAVE_1KB = 1024, 71 ADDR_PIPEINTERLEAVE_2KB = 2048, 72 }; 73 74 /** 75 **************************************************************************************************** 76 * @brief Neutral enums that define DRAM row size 77 **************************************************************************************************** 78 */ 79 enum RowSize 80 { 81 ADDR_ROWSIZE_1KB = 1024, 82 ADDR_ROWSIZE_2KB = 2048, 83 ADDR_ROWSIZE_4KB = 4096, 84 ADDR_ROWSIZE_8KB = 8192, 85 }; 86 87 /** 88 **************************************************************************************************** 89 * @brief Neutral enums that define bank interleave 90 **************************************************************************************************** 91 */ 92 enum BankInterleave 93 { 94 ADDR_BANKINTERLEAVE_1 = 1, 95 ADDR_BANKINTERLEAVE_2 = 2, 96 ADDR_BANKINTERLEAVE_4 = 4, 97 ADDR_BANKINTERLEAVE_8 = 8, 98 }; 99 100 /** 101 **************************************************************************************************** 102 * @brief Neutral enums that define shader engine tile size 103 **************************************************************************************************** 104 */ 105 enum ShaderEngineTileSize 106 { 107 ADDR_SE_TILESIZE_16 = 16, 108 ADDR_SE_TILESIZE_32 = 32, 109 }; 110 111 /** 112 **************************************************************************************************** 113 * @brief Neutral enums that define bank swap size 114 **************************************************************************************************** 115 */ 116 enum BankSwapSize 117 { 118 ADDR_BANKSWAP_128B = 128, 119 ADDR_BANKSWAP_256B = 256, 120 ADDR_BANKSWAP_512B = 512, 121 ADDR_BANKSWAP_1KB = 1024, 122 }; 123 124 /** 125 **************************************************************************************************** 126 * @brief Enums that define max compressed fragments config 127 **************************************************************************************************** 128 */ 129 enum NumMaxCompressedFragmentsConfig 130 { 131 ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000, 132 ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001, 133 ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002, 134 ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003, 135 }; 136 137 /** 138 **************************************************************************************************** 139 * @brief Enums that define num pipes config 140 **************************************************************************************************** 141 */ 142 enum NumPipesConfig 143 { 144 ADDR_CONFIG_1_PIPE = 0x00000000, 145 ADDR_CONFIG_2_PIPE = 0x00000001, 146 ADDR_CONFIG_4_PIPE = 0x00000002, 147 ADDR_CONFIG_8_PIPE = 0x00000003, 148 ADDR_CONFIG_16_PIPE = 0x00000004, 149 ADDR_CONFIG_32_PIPE = 0x00000005, 150 ADDR_CONFIG_64_PIPE = 0x00000006, 151 }; 152 153 /** 154 **************************************************************************************************** 155 * @brief Enums that define num banks config 156 **************************************************************************************************** 157 */ 158 enum NumBanksConfig 159 { 160 ADDR_CONFIG_1_BANK = 0x00000000, 161 ADDR_CONFIG_2_BANK = 0x00000001, 162 ADDR_CONFIG_4_BANK = 0x00000002, 163 ADDR_CONFIG_8_BANK = 0x00000003, 164 ADDR_CONFIG_16_BANK = 0x00000004, 165 }; 166 167 /** 168 **************************************************************************************************** 169 * @brief Enums that define num rb per shader engine config 170 **************************************************************************************************** 171 */ 172 enum NumRbPerShaderEngineConfig 173 { 174 ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000, 175 ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001, 176 ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002, 177 }; 178 179 /** 180 **************************************************************************************************** 181 * @brief Enums that define num shader engines config 182 **************************************************************************************************** 183 */ 184 enum NumShaderEnginesConfig 185 { 186 ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, 187 ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, 188 ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002, 189 ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003, 190 }; 191 192 /** 193 **************************************************************************************************** 194 * @brief Enums that define pipe interleave size config 195 **************************************************************************************************** 196 */ 197 enum PipeInterleaveSizeConfig 198 { 199 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, 200 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, 201 ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002, 202 ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003, 203 }; 204 205 /** 206 **************************************************************************************************** 207 * @brief Enums that define row size config 208 **************************************************************************************************** 209 */ 210 enum RowSizeConfig 211 { 212 ADDR_CONFIG_1KB_ROW = 0x00000000, 213 ADDR_CONFIG_2KB_ROW = 0x00000001, 214 ADDR_CONFIG_4KB_ROW = 0x00000002, 215 }; 216 217 /** 218 **************************************************************************************************** 219 * @brief Enums that define bank interleave size config 220 **************************************************************************************************** 221 */ 222 enum BankInterleaveSizeConfig 223 { 224 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, 225 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, 226 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, 227 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, 228 }; 229 230 /** 231 **************************************************************************************************** 232 * @brief Enums that define engine tile size config 233 **************************************************************************************************** 234 */ 235 enum ShaderEngineTileSizeConfig 236 { 237 ADDR_CONFIG_SE_TILE_16 = 0x00000000, 238 ADDR_CONFIG_SE_TILE_32 = 0x00000001, 239 }; 240 241 /** 242 **************************************************************************************************** 243 * @brief This class contains asic independent address lib functionalities 244 **************************************************************************************************** 245 */ 246 class Lib : public Object 247 { 248 public: 249 virtual ~Lib(); 250 251 static ADDR_E_RETURNCODE Create( 252 const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut); 253 254 /// Pair of Create Destroy()255 VOID Destroy() 256 { 257 delete this; 258 } 259 260 static Lib* GetLib(ADDR_HANDLE hLib); 261 262 /// Returns AddrLib version (from compiled binary instead include file) GetVersion()263 UINT_32 GetVersion() 264 { 265 return m_version; 266 } 267 268 /// Returns asic chip family name defined by AddrLib GetChipFamily()269 ChipFamily GetChipFamily() 270 { 271 return m_chipFamily; 272 } 273 274 ADDR_E_RETURNCODE Flt32ToDepthPixel( 275 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn, 276 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const; 277 278 ADDR_E_RETURNCODE Flt32ToColorPixel( 279 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn, 280 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const; 281 282 BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const; 283 284 ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const; 285 286 ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const; 287 288 UINT_32 GetBpe(AddrFormat format) const; 289 290 protected: 291 Lib(); // Constructor is protected 292 Lib(const Client* pClient); 293 294 /// Pure virtual function to get max base alignments 295 virtual UINT_32 HwlComputeMaxBaseAlignments() const = 0; 296 297 /// Gets maximum alignements for metadata HwlComputeMaxMetaBaseAlignments()298 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const 299 { 300 ADDR_NOT_IMPLEMENTED(); 301 302 return 0; 303 } 304 ValidBaseAlignments(UINT_32 alignment)305 VOID ValidBaseAlignments(UINT_32 alignment) const 306 { 307 #if DEBUG 308 ADDR_ASSERT(alignment <= m_maxBaseAlign); 309 #endif 310 } 311 ValidMetaBaseAlignments(UINT_32 metaAlignment)312 VOID ValidMetaBaseAlignments(UINT_32 metaAlignment) const 313 { 314 #if DEBUG 315 ADDR_ASSERT(metaAlignment <= m_maxMetaBaseAlign); 316 #endif 317 } 318 319 // 320 // Initialization 321 // 322 /// Pure Virtual function for Hwl computing internal global parameters from h/w registers 323 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn) = 0; 324 325 /// Pure Virtual function for Hwl converting chip family 326 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0; 327 328 /// Get equation table pointer and number of equations HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)329 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 330 { 331 *ppEquationTable = NULL; 332 333 return 0; 334 } 335 336 // 337 // Misc helper 338 // 339 static UINT_32 Bits2Number(UINT_32 bitNum, ...); 340 GetNumFragments(UINT_32 numSamples,UINT_32 numFrags)341 static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags) 342 { 343 return (numFrags != 0) ? numFrags : Max(1u, numSamples); 344 } 345 346 /// Returns pointer of ElemLib GetElemLib()347 ElemLib* GetElemLib() const 348 { 349 return m_pElemLib; 350 } 351 352 /// Returns fillSizeFields flag GetFillSizeFieldsFlags()353 UINT_32 GetFillSizeFieldsFlags() const 354 { 355 return m_configFlags.fillSizeFields; 356 } 357 358 private: 359 // Disallow the copy constructor 360 Lib(const Lib& a); 361 362 // Disallow the assignment operator 363 Lib& operator=(const Lib& a); 364 365 VOID SetChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 366 367 VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels); 368 369 VOID SetMaxAlignments(); 370 371 protected: 372 ChipFamily m_chipFamily; ///< Chip family translated from the one in atiid.h 373 374 UINT_32 m_chipRevision; ///< Revision id from xxx_id.h 375 376 UINT_32 m_version; ///< Current version 377 378 // 379 // Global parameters 380 // 381 ConfigFlags m_configFlags; ///< Global configuration flags. Note this is setup by 382 /// AddrLib instead of Client except forceLinearAligned 383 384 UINT_32 m_pipes; ///< Number of pipes 385 UINT_32 m_banks; ///< Number of banks 386 /// For r800 this is MC_ARB_RAMCFG.NOOFBANK 387 /// Keep it here to do default parameter calculation 388 389 UINT_32 m_pipeInterleaveBytes; 390 ///< Specifies the size of contiguous address space 391 /// within each tiling pipe when making linear 392 /// accesses. (Formerly Group Size) 393 394 UINT_32 m_rowSize; ///< DRAM row size, in bytes 395 396 UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels 397 UINT_32 m_maxSamples; ///< Max numSamples 398 399 UINT_32 m_maxBaseAlign; ///< Max base alignment for data surface 400 UINT_32 m_maxMetaBaseAlign; ///< Max base alignment for metadata 401 402 private: 403 ElemLib* m_pElemLib; ///< Element Lib pointer 404 }; 405 406 Lib* SiHwlInit (const Client* pClient); 407 Lib* CiHwlInit (const Client* pClient); 408 Lib* Gfx9HwlInit (const Client* pClient); 409 Lib* Gfx10HwlInit(const Client* pClient); 410 Lib* Gfx11HwlInit(const Client* pClient); 411 } // Addr 412 413 #endif 414