1 /* 2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef I2S_CODEC_HI35XX_H 17 #define I2S_CODEC_HI35XX_H 18 19 #include "i2s_hi35xx.h" 20 #include "i2s_if.h" 21 #include "los_vm_zone.h" 22 23 24 #ifdef __cplusplus 25 #if __cplusplus 26 extern "C" { 27 #endif /* __cplusplus */ 28 #endif /* __cplusplus */ 29 30 #define AUDIO_ANA_CTRL_0 0x0014 31 #define DACL_POP_EN (0x1 << 18) 32 #define DACL_POP_EN_SHIFT 18 33 #define DACR_POP_EN (0x1 << 16) 34 #define DACR_POP_EN_SHIFT 16 35 #define MUTE_DACR (0x1 << 14) 36 #define MUTE_DACR_SHIFT 14 37 #define MUTE_DACL (0x1 << 13) 38 #define MUTE_DACL_SHIFT 13 39 #define PD_DACR (0x1 << 12) 40 #define PD_DACR_SHIFT 12 41 #define PD_DACL (0x1 << 11) 42 #define PD_DACL_SHIFT 11 43 #define PD_MICBIAS1 (0x1 << 5) 44 #define PD_MICBIAS1_SHIFT 5 45 #define PDB_CTCM_IBIAS (0x1 << 1) 46 #define PDB_CTCM_IBIAS_SHIFT 1 47 #define PD_VERF (0x1 << 1) 48 #define PD_VERF_SHIFT 1 49 50 #define AUDIO_ANA_CTRL_1 0x0018 51 #define RX_CTCM_PD (0x1 << 17) 52 #define RX_CTCM_PD_SHIFT 17 53 54 #define AUDIO_ANA_CTRL_2 0x001c 55 #define AUDIO_ANA_CTRL_2_RST (0x1 << 23) 56 #define AUDIO_ANA_CTRL_2_RST_SHIFT 23 57 #define AUDIO_ANA_CTRL_2_VREF_SEL (0x1f << 18) 58 #define AUDIO_ANA_CTRL_2_VREF_SEL_SHIFT 18 59 #define AUDIO_ANA_CTRL_2_ADCL_MODE_SEL (0x1 << 7) 60 #define AUDIO_ANA_CTRL_2_ADCL_MODE_SEL_SHIFT 7 61 #define AUDIO_ANA_CTRL_2_ADCR_MODE_SEL (0x1 << 6) 62 #define AUDIO_ANA_CTRL_2_ADCR_MODE_SEL_SHIFT 6 63 #define AUDIO_ANA_CTRL_2_LDO_PD_SEL (0x1 << 0) 64 #define AUDIO_ANA_CTRL_2_LDO_PD_SEL_SHIFT 0 65 66 #define AUDIO_ANA_CTRL_3 0x0020 67 #define PD_ADC_TUNE_09 (0x1 << 11) 68 #define PD_ADC_TUNE_09_SHIFT 11 69 #define POP_RAMPCLK_SEL (0x3 << 5) 70 #define POP_RAMPCLK_SEL_SHIFT 5 71 #define POP_RES_SEL (0x3 << 3) 72 #define POP_RES_SEL_SHIFT 3 73 #define DACL_POP_DIRECT (0x1 << 2) 74 #define DACL_POP_DIRECT_SHIFT 2 75 #define DACR_POP_DIRECT (0x1 << 0) 76 #define DACR_POP_DIRECT_SHIFT 0 77 78 #define AUDIO_ANA_CTRL_4 0x0024 79 #define ADC_TUNE_EN_09 (0x1 << 11) 80 #define ADC_TUNE_EN_09_SHIFT 11 81 #define ADC_TUNE_SEL_09 (0x1 << 10) 82 #define ADC_TUNE_SEL_09_SHIFT 10 83 84 #define AUDIO_ANA_CTRL_5 0x0028 85 86 #define AUDIO_CTRL_REG_1 0x0030 87 #define I2S1_FS_SEL (0x1f << 13) 88 #define I2S1_FS_SEL_SHIFT 13 89 #define I2S1_DATA_BITS (0x3 << 22) 90 #define I2S1_DATA_BITS_SHIFT 22 91 #define I2S2_DATA_BITS (0x3 << 20) 92 #define I2S2_DATA_BITS_SHIFT 20 93 94 #define I2S_DATA_BITS_16 0x00 95 #define I2S_DATA_BITS_18 0x01 96 #define I2S_DATA_BITS_20 0x10 97 #define I2S_DATA_BITS_24 0x11 98 99 100 #define I2S_FS_SEL_MCLK_1024FS 0x18 101 #define I2S_FS_SEL_MCLK_512FS 0x19 102 #define I2S_FS_SEL_MCLK_256FS 0x1a 103 #define I2S_FS_SEL_MCLK_128FS 0x1b 104 #define I2S_FS_SEL_MCLK_64FS 0x1c 105 106 #define AUDIO_DAC_REG_0 0x0034 107 #define AUDIO_DAC_RG_1 0x0038 108 #define AUDIO_ADC_REG_0 0x003c 109 110 #define REG_ACODEC_REG18 0x48 111 #define I2S_PAD_ENABLE (0x1 << 1) 112 #define I2S_PAD_ENABLE_SHIFT 1 113 #define AUDIO_ENABLE (0x1 << 0) 114 #define AUDIO_ENABLE_SHIFT 0 115 116 #define AUDIO_ANA_CTRL_0_INIT_VAL 0x040578E1 117 #define AUDIO_ANA_CTRL_1_INIT_VAL 0xFD220004 118 #define AUDIO_ANA_CTRL_2_INIT_VAL 0x4098001b 119 #define AUDIO_ANA_CTRL_3_INIT_VAL 0x8383fe00 120 #define AUDIO_ANA_CTRL_4_INIT_VAL 0x0000505C 121 #define AUDIO_ANA_CTRL_5_INIT_VAL 0x0 122 123 #define AUDIO_ANA_CTRL_0_RESET_VAL 0x4000002 124 #define AUDIO_ANA_CTRL_1_RESET_VAL 0xfd200004 125 #define AUDIO_ANA_CTRL_2_RESET_VAL 0x180018 126 #define AUDIO_ANA_CTRL_3_RESET_VAL 0x83830028 127 #define AUDIO_ANA_CTRL_4_RESET_VAL 0x5c5c 128 #define AUDIO_ANA_CTRL_5_RESET_VAL 0x130000 129 #define AUDIO_CTRL_REG_1_RESET_VAL 0xff035a00 130 #define AUDIO_DAC_REG_0_RESET_VAL 0x8000001 131 #define AUDIO_DAC_RG_1_RESET_VAL 0x6062424 132 #define AUDIO_ADC_REG_0_RESET_VAL 0x1e1ec001 133 134 135 #define CODEC_DEFAULT_MSLEEP 30 136 137 void GetI2sCodecInfo(const struct I2sConfigInfo *i2sCfg); 138 int32_t AudioCodecSetCfgI2slFsSel(uint16_t *pI2slFsSel, enum I2slFsSel i2slFsSel); 139 int32_t AudioCodecGetCfgI2slFsSel(uint16_t i2slFsSel, enum I2slFsSel *pEI2slFsSel); 140 void Hi35xxSetAudioCodec(struct I2sConfigInfo *i2sCfg, enum I2sSampleRate sampleRate, enum I2sWordWidth width); 141 void CodecInnerInit(const struct I2sConfigInfo *i2sCfg); 142 void CodecReset(const struct I2sConfigInfo *i2sCfg); 143 uint32_t CodecInit(const struct I2sConfigInfo *i2sCfg); 144 145 #ifdef __cplusplus 146 #if __cplusplus 147 } 148 #endif /* __cplusplus */ 149 #endif /* __cplusplus */ 150 #endif /* I2S_CODEC_HI35XX_H */ 151