1 /*
2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #include "i2s_codec_hi35xx.h"
17 #include "hdf_base.h"
18 #include "hdf_log.h"
19 #include "osal_io.h"
20 #include "osal_time.h"
21
22 #define HDF_LOG_TAG i2s_codec_hi35xx
GetI2sCodecInfo(const struct I2sConfigInfo * i2sCfg)23 void GetI2sCodecInfo(const struct I2sConfigInfo *i2sCfg)
24 {
25 uint32_t value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_0);
26 I2S_PRINT_LOG_ERR("%s: AUDIO_ANA_CTRL_0[0x%x][0x%08x]", __func__, AUDIO_ANA_CTRL_0, value);
27 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_1);
28 I2S_PRINT_LOG_DBG("%s: AUDIO_ANA_CTRL_1[0x%x][0x%08x]", __func__, AUDIO_ANA_CTRL_1, value);
29 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_2);
30 I2S_PRINT_LOG_DBG("%s: AUDIO_ANA_CTRL_2[0x%x][0x%08x]", __func__, AUDIO_ANA_CTRL_2, value);
31 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_3);
32 I2S_PRINT_LOG_DBG("%s: AUDIO_ANA_CTRL_3[0x%x][0x%08x]", __func__, AUDIO_ANA_CTRL_3, value);
33 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_4);
34 I2S_PRINT_LOG_DBG("%s: AUDIO_ANA_CTRL_4[0x%x][0x%08x]", __func__, AUDIO_ANA_CTRL_4, value);
35 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_5);
36 I2S_PRINT_LOG_DBG("%s: AUDIO_ANA_CTRL_5[0x%x][0x%08x]", __func__, AUDIO_ANA_CTRL_5, value);
37
38 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_CTRL_REG_1);
39 I2S_PRINT_LOG_DBG("%s: AUDIO_CTRL_REG_1[0x%x][0x%08x]", __func__, AUDIO_CTRL_REG_1, value);
40
41 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_DAC_REG_0);
42 I2S_PRINT_LOG_DBG("%s: AUDIO_DAC_REG_0[0x%x][0x%08x]", __func__, AUDIO_DAC_REG_0, value);
43 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_DAC_RG_1);
44 I2S_PRINT_LOG_DBG("%s: AUDIO_DAC_RG_1[0x%x][0x%08x]", __func__, AUDIO_DAC_RG_1, value);
45 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ADC_REG_0);
46 I2S_PRINT_LOG_DBG("%s: AUDIO_ADC_REG_0[0x%x][0x%08x]", __func__, AUDIO_ADC_REG_0, value);
47
48 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + REG_ACODEC_REG18);
49 I2S_PRINT_LOG_DBG("%s: REG_ACODEC_REG18[0x%x][0x%08x]", __func__, REG_ACODEC_REG18, value);
50 }
51
AudioCodecAdcModeSelShift(enum I2sSampleRate sampleRate)52 uint16_t AudioCodecAdcModeSelShift(enum I2sSampleRate sampleRate)
53 {
54 switch (sampleRate) {
55 case I2S_SAMPLE_RATE_8K:
56 case I2S_SAMPLE_RATE_16K:
57 case I2S_SAMPLE_RATE_32K:
58 return ACODEC_ADC_MODESEL_4096;
59 case I2S_SAMPLE_RATE_48K:
60 case I2S_SAMPLE_RATE_96K:
61 case I2S_SAMPLE_RATE_192K:
62 return ACODEC_ADC_MODESEL_6144;
63 default:
64 {
65 I2S_PRINT_LOG_ERR("%s: unsupported sampleRate [%d]", __func__, sampleRate);
66 return HDF_ERR_INVALID_PARAM;
67 }
68 }
69 return HDF_SUCCESS;
70 }
71
AudioCodecI2s1DataBits(enum I2sWordWidth width)72 uint16_t AudioCodecI2s1DataBits(enum I2sWordWidth width)
73 {
74 switch (width) {
75 case I2S_WORDWIDTH_16BIT:
76 return I2S_DATA_BITS_16;
77 case I2S_WORDWIDTH_18BIT:
78 return I2S_DATA_BITS_18;
79 case I2S_WORDWIDTH_20BIT:
80 return I2S_DATA_BITS_20;
81 case I2S_WORDWIDTH_24BIT:
82 return I2S_DATA_BITS_24;
83 default:
84 {
85 I2S_PRINT_LOG_ERR("%s: unsupported width [%d]", __func__, width);
86 return HDF_ERR_INVALID_PARAM;
87 }
88 }
89 return HDF_SUCCESS;
90 }
91
AudioCodecSetCfgI2slFsSel(uint16_t * pI2slFsSel,enum I2slFsSel i2slFsSel)92 int32_t AudioCodecSetCfgI2slFsSel(uint16_t *pI2slFsSel, enum I2slFsSel i2slFsSel)
93 {
94 if (pI2slFsSel == NULL) {
95 I2S_PRINT_LOG_ERR("%s: pI2slFsSel NULL", __func__);
96 return HDF_ERR_INVALID_PARAM;
97 }
98
99 switch (i2slFsSel) {
100 case I2SL_FS_SEL_1024_FS:
101 *pI2slFsSel = I2S_FS_SEL_MCLK_1024FS;
102 break;
103 case I2SL_FS_SEL_512_FS:
104 *pI2slFsSel = I2S_FS_SEL_MCLK_512FS;
105 break;
106 case I2SL_FS_SEL_256_FS:
107 *pI2slFsSel = I2S_FS_SEL_MCLK_256FS;
108 break;
109 case I2SL_FS_SEL_128_FS:
110 *pI2slFsSel = I2S_FS_SEL_MCLK_128FS;
111 break;
112 case I2SL_FS_SEL_64_FS:
113 *pI2slFsSel = I2S_FS_SEL_MCLK_64FS;
114 break;
115 default:
116 {
117 I2S_PRINT_LOG_ERR("%s: error i2slFsSel [%d]", __func__, i2slFsSel);
118 return HDF_ERR_INVALID_PARAM;
119 }
120 }
121
122 I2S_PRINT_LOG_DBG("%s: *pI2slFsSel [%x]", __func__, *pI2slFsSel);
123 return HDF_SUCCESS;
124 }
125
AudioCodecGetCfgI2slFsSel(uint16_t i2slFsSel,enum I2slFsSel * pEI2slFsSel)126 int32_t AudioCodecGetCfgI2slFsSel(uint16_t i2slFsSel, enum I2slFsSel *pEI2slFsSel)
127 {
128 if (pEI2slFsSel == NULL) {
129 I2S_PRINT_LOG_ERR("%s: pEI2slFsSel NULL", __func__);
130 return HDF_ERR_INVALID_PARAM;
131 }
132
133 switch (i2slFsSel) {
134 case I2S_FS_SEL_MCLK_1024FS:
135 *pEI2slFsSel = I2SL_FS_SEL_1024_FS;
136 break;
137 case I2S_FS_SEL_MCLK_512FS:
138 *pEI2slFsSel = I2SL_FS_SEL_512_FS;
139 break;
140 case I2S_FS_SEL_MCLK_256FS:
141 *pEI2slFsSel = I2SL_FS_SEL_256_FS;
142 break;
143 case I2S_FS_SEL_MCLK_128FS:
144 *pEI2slFsSel = I2SL_FS_SEL_128_FS;
145 break;
146 case I2S_FS_SEL_MCLK_64FS:
147 *pEI2slFsSel = I2SL_FS_SEL_64_FS;
148 break;
149 default:
150 {
151 I2S_PRINT_LOG_ERR("%s: error i2slFsSel [%d]", __func__, i2slFsSel);
152 return HDF_ERR_INVALID_PARAM;
153 }
154 }
155
156 I2S_PRINT_LOG_DBG("%s: *pEI2slFsSel [%x]", __func__, *pEI2slFsSel);
157 return HDF_SUCCESS;
158 }
159
AudioCodecSetI2slFsSel(const struct I2sConfigInfo * i2sCfg,enum I2sSampleRate sampleRate)160 void AudioCodecSetI2slFsSel(const struct I2sConfigInfo *i2sCfg, enum I2sSampleRate sampleRate)
161 {
162 if (i2sCfg == NULL) {
163 I2S_PRINT_LOG_ERR("%s:i2sCfg null", __func__);
164 return;
165 }
166
167 uint32_t value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_CTRL_REG_1);
168 value &= ~I2S1_FS_SEL;
169 value |= (i2sCfg->i2slFsSel << I2S1_FS_SEL_SHIFT);
170 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_CTRL_REG_1);
171
172 uint16_t tmp = AudioCodecAdcModeSelShift(sampleRate);
173 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_2);
174 value &= ~AUDIO_ANA_CTRL_2_ADCL_MODE_SEL;
175 value |= (tmp << AUDIO_ANA_CTRL_2_ADCL_MODE_SEL_SHIFT);
176 value &= ~AUDIO_ANA_CTRL_2_ADCR_MODE_SEL;
177 value |= (tmp << AUDIO_ANA_CTRL_2_ADCR_MODE_SEL_SHIFT);
178 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_2);
179
180 /* rctune */
181 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_4);
182 value &= ~ADC_TUNE_EN_09;
183 value |= (0x0 << ADC_TUNE_EN_09_SHIFT);
184 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_4);
185
186 OsalUDelay(30); /* wait 30 us. */
187
188 value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_ANA_CTRL_4);
189 value &= ~ADC_TUNE_EN_09;
190 value |= (0x1 << ADC_TUNE_EN_09_SHIFT);
191 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_4);
192 }
193
AudioCodecSetWidth(const struct I2sConfigInfo * i2sCfg,enum I2sWordWidth width)194 void AudioCodecSetWidth(const struct I2sConfigInfo *i2sCfg, enum I2sWordWidth width)
195 {
196 if (i2sCfg == NULL) {
197 I2S_PRINT_LOG_ERR("%s:i2sCfg null", __func__);
198 return;
199 }
200
201 uint16_t tmp = AudioCodecI2s1DataBits(width);
202 uint32_t value = Hi35xxI2sRegRead(i2sCfg->codecAddr + AUDIO_CTRL_REG_1);
203 value &= ~I2S1_DATA_BITS;
204 value |= (tmp << I2S1_DATA_BITS_SHIFT);
205 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_CTRL_REG_1);
206 }
207
AudioCodecSetAiaoChl(const struct I2sConfigInfo * i2sCfg)208 void AudioCodecSetAiaoChl(const struct I2sConfigInfo *i2sCfg)
209 {
210 if (i2sCfg == NULL) {
211 I2S_PRINT_LOG_ERR("%s:i2sCfg null", __func__);
212 return;
213 }
214
215 uint32_t value = Hi35xxI2sRegRead(i2sCfg->codecAddr + REG_ACODEC_REG18);
216 uint16_t tmp;
217 if (i2sCfg->writeChannel == I2S_WRITE_CHANNEL_AUDIO) {
218 value &= ~I2S_PAD_ENABLE;
219 tmp = 0x0;
220 value |= (tmp << I2S_PAD_ENABLE_SHIFT);
221 value &= ~AUDIO_ENABLE;
222 tmp = 0x1;
223 value |= (tmp << AUDIO_ENABLE_SHIFT);
224 } else { // output
225 value &= ~I2S_PAD_ENABLE;
226 tmp = 0x1;
227 value |= (tmp << I2S_PAD_ENABLE_SHIFT);
228 value &= ~AUDIO_ENABLE;
229 tmp = 0x0;
230 value |= (tmp << AUDIO_ENABLE_SHIFT);
231 }
232
233 // audio enable value is 0x9
234 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + REG_ACODEC_REG18);
235 }
236
Hi35xxSetAudioCodec(struct I2sConfigInfo * i2sCfg,enum I2sSampleRate sampleRate,enum I2sWordWidth width)237 void Hi35xxSetAudioCodec(struct I2sConfigInfo *i2sCfg, enum I2sSampleRate sampleRate, enum I2sWordWidth width)
238 {
239 if (i2sCfg == NULL) {
240 I2S_PRINT_LOG_ERR("%s:i2sCfg null", __func__);
241 return;
242 }
243
244 I2S_PRINT_LOG_DBG("%s: i2slFsSel[0x%x] sampleRate[0x%d] writeChannel[%d]", __func__,
245 i2sCfg->i2slFsSel, sampleRate, i2sCfg->writeChannel);
246 i2sCfg->sampleRate = sampleRate;
247 i2sCfg->width = width;
248 AudioCodecSetI2slFsSel(i2sCfg, sampleRate);
249 AudioCodecSetWidth(i2sCfg, width);
250 AudioCodecSetAiaoChl(i2sCfg);
251 }
252
CodecAnaCtrl0Init(const struct I2sConfigInfo * i2sCfg)253 void CodecAnaCtrl0Init(const struct I2sConfigInfo *i2sCfg)
254 {
255 uint32_t value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_0);
256 value &= ~PD_DACL;
257 value |= (0x0 << PD_DACL_SHIFT);
258 value &= ~PD_DACR;
259 value |= (0x0 << PD_DACR_SHIFT);
260 value &= ~MUTE_DACL;
261 value |= (0x0 << MUTE_DACL_SHIFT);
262 value &= ~MUTE_DACR;
263 value |= (0x0 << MUTE_DACR_SHIFT);
264 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_0);
265
266 value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_0);
267 value &= ~DACR_POP_EN;
268 value |= (0x0 << DACR_POP_EN_SHIFT);
269 value &= ~DACL_POP_EN;
270 value |= (0x0 << DACL_POP_EN_SHIFT);
271 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_0);
272 }
273
274
CodecInnerInit(const struct I2sConfigInfo * i2sCfg)275 void CodecInnerInit(const struct I2sConfigInfo *i2sCfg)
276 {
277 if (i2sCfg == NULL) {
278 I2S_PRINT_LOG_ERR("%s:i2sCfg null", __func__);
279 return;
280 }
281
282 uint32_t value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_2);
283 value &= ~AUDIO_ANA_CTRL_2_RST;
284 value |= (0x0 << AUDIO_ANA_CTRL_2_RST_SHIFT);
285 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_2);
286
287 value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_3);
288 value &= ~POP_RAMPCLK_SEL;
289 value |= (0x1 << POP_RAMPCLK_SEL_SHIFT);
290 value &= ~POP_RES_SEL;
291 value |= (0x1 << POP_RES_SEL_SHIFT);
292 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_3);
293
294 value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_2);
295 value &= ~AUDIO_ANA_CTRL_2_VREF_SEL;
296 value |= (0x0 << AUDIO_ANA_CTRL_2_VREF_SEL_SHIFT);
297 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_2);
298
299 value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_0);
300 value &= ~PDB_CTCM_IBIAS;
301 value |= (0x1 << PDB_CTCM_IBIAS_SHIFT);
302 value &= ~PD_MICBIAS1;
303 value |= (0x1 << PD_MICBIAS1_SHIFT);
304 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_0);
305
306 value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_1);
307 value &= ~RX_CTCM_PD;
308 value |= (0x0 << RX_CTCM_PD_SHIFT);
309 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_1);
310
311 value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_2);
312 value &= ~AUDIO_ANA_CTRL_2_LDO_PD_SEL;
313 value |= (0x0 << AUDIO_ANA_CTRL_2_LDO_PD_SEL_SHIFT);
314 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_2);
315
316 value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_0);
317 value &= ~PD_VERF;
318 value |= (0x0 << PD_VERF_SHIFT);
319 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_0);
320
321 value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_3);
322 value &= ~DACL_POP_DIRECT;
323 value |= (0x1 << DACL_POP_DIRECT_SHIFT);
324 value &= ~DACR_POP_DIRECT;
325 value |= (0x1 << DACR_POP_DIRECT_SHIFT);
326 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_3);
327
328 OsalMSleep(CODEC_DEFAULT_MSLEEP);
329
330 CodecAnaCtrl0Init(i2sCfg);
331 }
332
CodecReset(const struct I2sConfigInfo * i2sCfg)333 void CodecReset(const struct I2sConfigInfo *i2sCfg)
334 {
335 if (i2sCfg == NULL) {
336 I2S_PRINT_LOG_ERR("%s:i2sCfg null", __func__);
337 return;
338 }
339
340 Hi35xxI2sRegWrite(AUDIO_ANA_CTRL_0_RESET_VAL, i2sCfg->codecAddr + AUDIO_ANA_CTRL_0);
341 Hi35xxI2sRegWrite(AUDIO_ANA_CTRL_1_RESET_VAL, i2sCfg->codecAddr + AUDIO_ANA_CTRL_1);
342 Hi35xxI2sRegWrite(AUDIO_ANA_CTRL_2_RESET_VAL, i2sCfg->codecAddr + AUDIO_ANA_CTRL_2);
343
344 Hi35xxI2sRegWrite(AUDIO_ANA_CTRL_3_RESET_VAL, i2sCfg->codecAddr + AUDIO_ANA_CTRL_3);
345 Hi35xxI2sRegWrite(AUDIO_ANA_CTRL_4_RESET_VAL, i2sCfg->codecAddr + AUDIO_ANA_CTRL_4);
346
347 Hi35xxI2sRegWrite(AUDIO_ANA_CTRL_5_RESET_VAL, i2sCfg->codecAddr + AUDIO_ANA_CTRL_5);
348
349 Hi35xxI2sRegWrite(AUDIO_CTRL_REG_1_RESET_VAL, i2sCfg->codecAddr + AUDIO_CTRL_REG_1);
350 Hi35xxI2sRegWrite(AUDIO_DAC_REG_0_RESET_VAL, i2sCfg->codecAddr + AUDIO_DAC_REG_0);
351 Hi35xxI2sRegWrite(AUDIO_DAC_RG_1_RESET_VAL, i2sCfg->codecAddr + AUDIO_DAC_RG_1);
352 Hi35xxI2sRegWrite(AUDIO_ADC_REG_0_RESET_VAL, i2sCfg->codecAddr + AUDIO_ADC_REG_0);
353 }
354
CodecInit(const struct I2sConfigInfo * i2sCfg)355 uint32_t CodecInit(const struct I2sConfigInfo *i2sCfg)
356 {
357 if (i2sCfg == NULL) {
358 I2S_PRINT_LOG_ERR("%s: i2sCfg is null", __func__);
359 return HDF_FAILURE;
360 }
361
362 // init
363 Hi35xxI2sRegWrite(AUDIO_ANA_CTRL_0_INIT_VAL, i2sCfg->codecAddr + AUDIO_ANA_CTRL_0);
364 Hi35xxI2sRegWrite(AUDIO_ANA_CTRL_1_INIT_VAL, i2sCfg->codecAddr + AUDIO_ANA_CTRL_1);
365 Hi35xxI2sRegWrite(AUDIO_ANA_CTRL_2_INIT_VAL, i2sCfg->codecAddr + AUDIO_ANA_CTRL_2);
366
367 Hi35xxI2sRegWrite(AUDIO_ANA_CTRL_3_INIT_VAL, i2sCfg->codecAddr + AUDIO_ANA_CTRL_3);
368 Hi35xxI2sRegWrite(AUDIO_ANA_CTRL_4_INIT_VAL, i2sCfg->codecAddr + AUDIO_ANA_CTRL_4);
369 Hi35xxI2sRegWrite(AUDIO_ANA_CTRL_5_INIT_VAL, i2sCfg->codecAddr + AUDIO_ANA_CTRL_5);
370
371 CodecInnerInit(i2sCfg);
372
373 uint32_t value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_2);
374 value &= ~AUDIO_ANA_CTRL_2_LDO_PD_SEL;
375 value |= (0x0 << AUDIO_ANA_CTRL_2_LDO_PD_SEL_SHIFT);
376 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_2);
377
378 value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_3);
379 value &= ~PD_ADC_TUNE_09;
380 value |= (0x0 << PD_ADC_TUNE_09_SHIFT);
381 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_3);
382
383 value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_4);
384 value &= ~ADC_TUNE_SEL_09;
385 value |= (0x1 << ADC_TUNE_SEL_09_SHIFT);
386
387 value = Hi35xxI2sRegRead(i2sCfg->regBase + AUDIO_ANA_CTRL_4);
388 value &= ~ADC_TUNE_EN_09;
389 value |= (0x1 << ADC_TUNE_EN_09_SHIFT);
390 Hi35xxI2sRegWrite(value, i2sCfg->codecAddr + AUDIO_ANA_CTRL_4);
391
392 CodecReset(i2sCfg);
393 return HDF_SUCCESS;
394 }
395