1 // SPDX-License-Identifier: (GPL-2.0+ or MIT) 2 /* 3 * Copyright (C) 2020 frank@allwinnertech.com 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_SUN50IW12_H_ 7 #define _DT_BINDINGS_CLK_SUN50IW12_H_ 8 9 #define CLK_OSC12M 0 10 #define CLK_PLL_CPUX 1 11 #define CLK_PLL_DDR0 2 12 #define CLK_PLL_PERIPH0 3 13 #define CLK_PLL_PERIPH0_2X 4 14 #define CLK_PLL_PERIPH1 5 15 #define CLK_PLL_PERIPH1_2X 6 16 #define CLK_PLL_GPU 7 17 #define CLK_PLL_VIDEO0 8 18 #define CLK_PLL_VIDEO0_4X 9 19 #define CLK_PLL_VIDEO1 10 20 #define CLK_PLL_VIDEO1_4X 11 21 #define CLK_PLL_VIDEO2 12 22 #define CLK_PLL_VIDEO2_4X 13 23 #define CLK_PLL_VE 14 24 #define CLK_PLL_ADC 15 25 #define CLK_PLL_VIDEO3 16 26 #define CLK_PLL_VIDEO3_4X 17 27 #define CLK_PLL_AUDIO 18 28 #define CLK_CPUX 19 29 #define CLK_AXI 20 30 #define CLK_CPUX_APB 21 31 #define CLK_AHB 22 32 #define CLK_APB0 23 33 #define CLK_APB1 24 34 #define CLK_MBUS 25 35 #define CLK_MIPS 26 36 #define CLK_BUS_MIPS 27 37 #define CLK_GPU 28 38 #define CLK_BUS_GPU 29 39 #define CLK_CE 30 40 #define CLK_BUS_CE 31 41 #define CLK_VE_CORE 32 42 #define CLK_BUS_VE 33 43 #define CLK_BUS_AV1 34 44 #define CLK_BUS_VE3 35 45 #define CLK_BUS_DMA 36 46 #define CLK_MSGBOX 37 47 #define CLK_SPINLOCK 38 48 #define CLK_TIMER0 39 49 #define CLK_TIMER1 40 50 #define CLK_TIMER2 41 51 #define CLK_TIMER3 42 52 #define CLK_TIMER4 43 53 #define CLK_TIMER5 44 54 #define CLK_BUS_TIMER0 45 55 #define CLK_BUS_DBG 46 56 #define CLK_BUS_PWM 47 57 #define CLK_BUS_IOMMU 48 58 #define CLK_DRAM 49 59 #define CLK_MBUS_DMA 50 60 #define CLK_MBUS_VE3 51 61 #define CLK_MBUS_CE 52 62 #define CLK_MBUS_AV1 53 63 #define CLK_MBUS_NAND 54 64 #define CLK_BUS_DRAM 55 65 #define CLK_NAND0 56 66 #define CLK_NAND1 57 67 #define CLK_BUS_NAND 58 68 #define CLK_MMC0 59 69 #define CLK_MMC1 60 70 #define CLK_MMC2 61 71 #define CLK_BUS_MMC0 62 72 #define CLK_BUS_MMC1 63 73 #define CLK_BUS_MMC2 64 74 #define CLK_BUS_UART0 65 75 #define CLK_BUS_UART1 66 76 #define CLK_BUS_UART2 67 77 #define CLK_BUS_UART3 68 78 #define CLK_BUS_I2C0 69 79 #define CLK_BUS_I2C1 70 80 #define CLK_BUS_I2C2 71 81 #define CLK_BUS_I2C3 72 82 #define CLK_SPI0 73 83 #define CLK_SPI1 74 84 #define CLK_BUS_SPI0 75 85 #define CLK_BUS_SPI1 76 86 #define CLK_EMAC_25M 77 87 #define CLK_BUS_EMAC 78 88 #define CLK_BUS_GPADC 79 89 #define CLK_BUS_THS 80 90 #define CLK_I2S0 81 91 #define CLK_I2S1 82 92 #define CLK_I2S2 83 93 #define CLK_BUS_I2S0 84 94 #define CLK_BUS_I2S1 85 95 #define CLK_BUS_I2S2 86 96 #define CLK_SPDIF0_RX 87 97 #define CLK_SPDIF0_TX 88 98 #define CLK_SPDIF1_RX 89 99 #define CLK_SPDIF1_TX 90 100 #define CLK_BUS_SPDIF0 91 101 #define CLK_BUS_SPDIF1 92 102 #define CLK_AUDIO_HUB 93 103 #define CLK_AUDIO_CODEC_DAC 94 104 #define CLK_AUDIO_CODEC_ADC 95 105 #define CLK_BUS_AUDIO_CODEC 96 106 #define CLK_USB_OHCI0 97 107 #define CLK_USB_OHCI1 98 108 #define CLK_USB_OHCI2 99 109 #define CLK_BUS_OHCI0 100 110 #define CLK_BUS_OHCI1 101 111 #define CLK_BUS_OHCI2 102 112 #define CLK_BUS_EHCI0 103 113 #define CLK_BUS_EHCI1 104 114 #define CLK_BUS_EHCI2 105 115 #define CLK_BUS_OTG 106 116 #define CLK_BUS_LRADC 107 117 #define CLK_ADC 108 118 #define CLK_DTMB_120M 109 119 #define CLK_TVFE_1296M 110 120 #define CLK_I2H 111 121 #define CLK_CIP_TSX 112 122 #define CLK_CIP_MCX 113 123 #define CLK_CIP_TSP 114 124 #define CLK_TSA_TSP 115 125 #define CLK_CIP27 116 126 #define CLK_CIP_MTS0 117 127 #define CLK_AUDIO_CPU 118 128 #define CLK_AUDIO_UMAC 119 129 #define CLK_AUDIO_IHB 120 130 #define CLK_TSA432 121 131 #define CLK_MPG0 122 132 #define CLK_MPG1 123 133 #define CLK_BUS_DEMOD 124 134 #define CLK_TCD3 125 135 #define CLK_VINCAP_DMA 126 136 #define CLK_BUS_HDMI_AUDIO 127 137 #define CLK_BUS_CAP_300M 128 138 #define CLK_HDMI_AUDIO 129 139 #define CLK_BUS_TVCAP 130 140 #define CLK_DEINT 131 141 #define CLK_SVP_DTL 132 142 #define CLK_AFBD 133 143 #define CLK_BUS_DISP 134 144 145 #endif /* _DT_BINDINGS_CLK_SUN50IW12_H_ */ 146