1 // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 /* SPI commands (actual on-wire commands not SPI controller bitmasks) 18 Suitable for use with spi_flash_hal_common_command static function. 19 */ 20 #define CMD_RDID 0x9F 21 #define CMD_WRSR 0x01 22 #define SR_WIP (1<<0) /* Status register write-in-progress bit */ 23 #define SR_WREN (1<<1) /* Status register write enable bit */ 24 #define CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ 25 #define CMD_WREN 0x06 26 #define CMD_WRDI 0x04 27 #define CMD_RDSR 0x05 28 #define CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ 29 #define CMD_RDSCUR 0x2B /* on specific(MXIC) board, read security register */ 30 #define CMD_RDFR 0x48 /* on specific(ISSI) board, read function register */ 31 32 #define CMD_FASTRD_QIO 0xEB 33 #define CMD_FASTRD_QIO_4B 0xEC 34 #define CMD_FASTRD_QUAD 0x6B 35 #define CMD_FASTRD_QUAD_4B 0x6C 36 #define CMD_FASTRD_DIO 0xBB 37 #define CMD_FASTRD_DIO_4B 0xBC 38 #define CMD_FASTRD_DUAL 0x3B 39 #define CMD_FASTRD_DUAL_4B 0x3C 40 #define CMD_FASTRD 0x0B 41 #define CMD_FASTRD_4B 0x0C 42 #define CMD_READ 0x03 /* Speed limited */ 43 #define CMD_READ_4B 0x13 /* Speed limited */ 44 45 #define CMD_CHIP_ERASE 0xC7 46 #define CMD_SECTOR_ERASE 0x20 47 #define CMD_SECTOR_ERASE_4B 0x21 48 #define CMD_LARGE_BLOCK_ERASE 0xD8 /* 64KB block erase command */ 49 #define CMD_LARGE_BLOCK_ERASE_4B 0xDC /* 64KB block erase command */ 50 #define CMD_PROGRAM_PAGE 0x02 51 #define CMD_PROGRAM_PAGE_4B 0x12 52 #define CMD_SUSPEND 0x75 53 #define CMD_RESUME 0x7A 54 55 #define CMD_RST_EN 0x66 56 #define CMD_RST_DEV 0x99 57 58 #define SPI_FLASH_DIO_ADDR_BITLEN 24 59 #define SPI_FLASH_DIO_DUMMY_BITLEN 4 60 #define SPI_FLASH_QIO_ADDR_BITLEN 24 61 #define SPI_FLASH_QIO_DUMMY_BITLEN 6 62 #define SPI_FLASH_QOUT_ADDR_BITLEN 24 63 #define SPI_FLASH_QOUT_DUMMY_BITLEN 8 64 #define SPI_FLASH_DOUT_ADDR_BITLEN 24 65 #define SPI_FLASH_DOUT_DUMMY_BITLEN 8 66 #define SPI_FLASH_FASTRD_ADDR_BITLEN 24 67 #define SPI_FLASH_FASTRD_DUMMY_BITLEN 8 68 #define SPI_FLASH_SLOWRD_ADDR_BITLEN 24 69 #define SPI_FLASH_SLOWRD_DUMMY_BITLEN 0 70