1 /* 2 * Copyright (c) 2021 Chipsea Technologies (Shenzhen) Corp., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 /** 16 **************************************************************************************** 17 * 18 * @file chip.h 19 * 20 **************************************************************************************** 21 */ 22 23 #ifndef _CHIP_H_ 24 #define _CHIP_H_ 25 26 /* 27 * ========================================================================== 28 * ---------- Interrupt Number Definition ----------------------------------- 29 * ========================================================================== 30 */ 31 32 typedef enum IRQn 33 { 34 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ 35 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 36 MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */ 37 BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */ 38 UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */ 39 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */ 40 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */ 41 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */ 42 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */ 43 44 /****** Chip Specific Interrupt Numbers **********************************************************/ 45 BTAON_IRQn = 0, /*!< BT AON Interrupt */ 46 WCNAON_IRQn = 1, /*!< WCN AON Interrupt */ 47 WGEN_IRQn = 2, /*!< WiFi gen Interrupt */ 48 WPROTTRIG_IRQn = 3, /*!< WiFi prottrigger Interrupt */ 49 WTXTRIG_IRQn = 4, /*!< WiFi txtrigger Interrupt */ 50 WRXTRIG_IRQn = 5, /*!< WiFi rxtrigger Interrupt */ 51 WTXRXMISC_IRQn = 6, /*!< WiFi txrxmisc Interrupt */ 52 WTXRXTIM_IRQn = 7, /*!< WiFi txrtimer Interrupt */ 53 WPHY_IRQn = 8, /*!< WiFi PHY Interrupt */ 54 BLE_IRQn = 9, /*!< BLE Interrupt */ 55 BT_IRQn = 10, /*!< BT Interrupt */ 56 BTDM_IRQn = 11, /*!< BTDM Interrupt */ 57 FREQ_IRQn = 12, /*!< FREQ Interrupt */ 58 DMACOMB_IRQn = 13, /*!< DMA Comb Interrupt */ 59 SDIO_IRQn = 14, /*!< SDIO Interrupt */ 60 USBDMA_IRQn = 15, /*!< USB DMA Interrupt */ 61 UART0_IRQn = 16, /*!< UART Interrupt */ 62 UART1_IRQn = 17, /*!< UART Interrupt */ 63 UART2_IRQn = 18, /*!< UART Interrupt */ 64 MCU2WCN0_IRQn = 19, /*!< MCU2WCN Interrupt */ 65 MCU2WCN1_IRQn = 20, /*!< MCU2WCN Interrupt */ 66 WCN2MCU0_IRQn = 21, /*!< WCN2MCU Interrupt */ 67 WCN2MCU1_IRQn = 22, /*!< WCN2MCU Interrupt */ 68 MCU2WCN0_G1_IRQn = 23, /*!< MCU2WCN Interrupt */ 69 MCU2WCN1_G1_IRQn = 24, /*!< MCU2WCN Interrupt */ 70 WCN2MCU0_G1_IRQn = 25, /*!< WCN2MCU Interrupt */ 71 WCN2MCU1_G1_IRQn = 26, /*!< WCN2MCU Interrupt */ 72 TIMER20_IRQn = 27, /*!< Timer Interrupt */ 73 TIMER21_IRQn = 28, /*!< Timer Interrupt */ 74 TIMER22_IRQn = 29, /*!< Timer Interrupt */ 75 WDT3_IRQn = 30, /*!< Camera Interrupt */ 76 ASDMA_COMMON_IRQn = 31, /*!< ASDMA Common Interrupt */ 77 ASDMA_GE_SW_IRQn = 32, /*!< ASDMA Generic SW Interrupt */ 78 ASDMA_AUDIO_IRQn = 33, /*!< ASDMA Audio Channel Interrupt */ 79 ASDMA_GE_HW_IRQn = 34, /*!< ASDMA Generic HW Interrupt */ 80 ASDMA_DMAC_IRQn = 35, /*!< ASDMA Dmac Interrupt */ 81 AUD_PROC_IRQn = 36, /*!< Audio Process Interrupt */ 82 DMA00_IRQn = 37, /*!< DMA Interrupt */ 83 DMA01_IRQn = 38, /*!< DMA Interrupt */ 84 DMA02_IRQn = 39, /*!< DMA Interrupt */ 85 DMA03_IRQn = 40, /*!< DMA Interrupt */ 86 DMA04_IRQn = 41, /*!< DMA Interrupt */ 87 DMA05_IRQn = 42, /*!< DMA Interrupt */ 88 DMA06_IRQn = 43, /*!< DMA Interrupt */ 89 DMA07_IRQn = 44, /*!< DMA Interrupt */ 90 DMA08_IRQn = 45, /*!< DMA Interrupt */ 91 DMA09_IRQn = 46, /*!< DMA Interrupt */ 92 DMA10_IRQn = 47, /*!< DMA Interrupt */ 93 DMA11_IRQn = 48, /*!< DMA Interrupt */ 94 DMA12_IRQn = 49, /*!< DMA Interrupt */ 95 DMA13_IRQn = 50, /*!< DMA Interrupt */ 96 MCU2WCN2_IRQn = 51, /*!< MCU2WCN Interrupt */ 97 MCU2WCN3_IRQn = 52, /*!< MCU2WCN Interrupt */ 98 WCN2MCU2_IRQn = 53, /*!< WCN2MCU Interrupt */ 99 WCN2MCU3_IRQn = 54, /*!< WCN2MCU Interrupt */ 100 MCU2WCN2_G1_IRQn = 55, /*!< MCU2WCN Interrupt */ 101 MCU2WCN3_G1_IRQn = 56, /*!< MCU2WCN Interrupt */ 102 WCN2MCU2_G1_IRQn = 57, /*!< WCN2MCU Interrupt */ 103 WCN2MCU3_G1_IRQn = 58, /*!< WCN2MCU Interrupt */ 104 TIMER00_IRQn = 59, /*!< Timer Interrupt */ 105 TIMER01_IRQn = 60, /*!< Timer Interrupt */ 106 TIMER02_IRQn = 61, /*!< Timer Interrupt */ 107 TIMER10_IRQn = 62, /*!< Timer Interrupt */ 108 TIMER11_IRQn = 63, /*!< Timer Interrupt */ 109 TIMER12_IRQn = 64, /*!< Timer Interrupt */ 110 GPIO_IRQn = 65, /*!< GPIO Interrupt */ 111 WDT0_IRQn = 66, /*!< WDT Interrupt */ 112 WDT1_IRQn = 67, /*!< WDT Interrupt */ 113 WDT2_IRQn = 68, /*!< WDT Interrupt */ 114 SPI_IRQn = 69, /*!< SPI Interrupt */ 115 TRNG_IRQn = 70, /*!< TRNG Interrupt */ 116 I2CM_IRQn = 71, /*!< I2C Master Interrupt */ 117 I2CS_IRQn = 72, /*!< I2C Slave Interrupt */ 118 CACHE0_IRQn = 73, /*!< Cache Interrupt */ 119 CACHE1_IRQn = 74, /*!< Cache Interrupt */ 120 PSRAM_IRQn = 75, /*!< PSRAM Interrupt */ 121 SDMMC_IRQn = 76, /*!< SDMMC Interrupt */ 122 PSIM_IRQn = 77, /*!< PSI Master Interrupt */ 123 PWRCTRL_IRQn = 78, /*!< Power Control Interrupt */ 124 PMIC_IRQn = 79, /*!< PMIC Interrupt */ 125 NVIC_USER_IRQ_NUMBER /*!< User Interrupt Number */ 126 } IRQn_Type; 127 128 129 /* 130 * ========================================================================== 131 * ----------- Processor and Core Peripheral Section ------------------------ 132 * ========================================================================== 133 */ 134 135 /* Configuration of the Cortex-M4 Processor and Core Peripherals */ 136 #define __MPU_PRESENT 1 /*!< MPU present or not */ 137 #define __FPU_PRESENT 1 /*!< FPU present or not */ 138 #define __NVIC_PRIO_BITS 6 /*!< Number of Bits used for Priority Levels */ 139 #define __NVIC_PRIO_LOWEST 0x3F /*!< The lowest NVIC priority */ 140 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 141 142 143 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ 144 145 146 /******************************************************************************/ 147 /* Peripheral memory map */ 148 /******************************************************************************/ 149 /* Base addresses */ 150 #define CS_ROM_BASE (0x00000000UL) 151 #define CS_PMIC_RAM_BASE (0x01000000UL) 152 #define CS_FLASH_MEM_BASE (0x04000000UL) 153 #define CS_PSRAM_MEM_BASE (0x06000000UL) 154 #define CS_CACHE0_MEM_BASE (0x08000000UL) 155 #define CS_CACHE1_MEM_BASE (0x0C000000UL) 156 #define CS_AHB0_BASE (0x40000000UL) 157 #define CS_APB0_BASE (0x40100000UL) 158 #define CS_AHB2_BASE (0x40200000UL) 159 #define CS_WLANREG_BASE (0x40300000UL) 160 #define CS_AHB1_BASE (0x40500000UL) 161 #define CS_APB1_BASE (CS_AHB1_BASE) 162 #define CS_BTREG_BASE (0x40600000UL) 163 #define CS_PMIC_REG_BASE (0x50000000UL) 164 165 /* AHB0 peripherals */ 166 #define CS_CACHE0_BASE (CS_AHB0_BASE + 0x00000) 167 #define CS_CACHE1_BASE (CS_AHB0_BASE + 0x20000) 168 #define CS_CPUP_TRAP_BASE (CS_AHB0_BASE + 0x40000) 169 #define CS_UART0_BASE (CS_AHB0_BASE + 0x41000) 170 #define CS_UART1_BASE (CS_AHB0_BASE + 0x42000) 171 #define CS_UART2_BASE (CS_AHB0_BASE + 0x43000) 172 #define CS_IPCAPP_BASE (CS_AHB0_BASE + 0x44000) 173 #define CS_IPCEMB_BASE (CS_AHB0_BASE + 0x44100) 174 #define CS_ASDMA_BASE (CS_AHB0_BASE + 0x50000) 175 #define CS_AUDPROC_BASE (CS_AHB0_BASE + 0x61000) 176 #define CS_DMA_BASE (CS_AHB0_BASE + 0x70000) 177 #define CS_DMA_CE_MEM_BASE (CS_AHB0_BASE + 0x73000) 178 #define CS_CPUSB_TRAP_BASE (CS_AHB0_BASE + 0x80000) 179 #define CS_CPUSW_TRAP_BASE (CS_AHB0_BASE + 0x81000) 180 #define CS_SDMMC_BASE (CS_AHB0_BASE + 0x82000) 181 182 /* APB0 peripherals */ 183 #define CS_CPUSYSCTRL_BASE (CS_APB0_BASE + 0x00000) 184 #define CS_PWM_BASE (CS_APB0_BASE + 0x01000) 185 #define CS_I2CM0_BASE (CS_APB0_BASE + 0x02000) 186 #define CS_WDT0_BASE (CS_APB0_BASE + 0x03000) 187 #define CS_WDT1_BASE (CS_APB0_BASE + 0x04000) 188 #define CS_SPI0_BASE (CS_APB0_BASE + 0x05000) 189 #define CS_TIM0_BASE (CS_APB0_BASE + 0x06000) 190 #define CS_TIM1_BASE (CS_APB0_BASE + 0x07000) 191 #define CS_SPINLOCK_BASE (CS_APB0_BASE + 0x08000) 192 #define CS_TRNG_BASE (CS_APB0_BASE + 0x09000) 193 #define CS_WDT2_BASE (CS_APB0_BASE + 0x0A000) 194 #define CS_WDT3_BASE (CS_APB0_BASE + 0x0C000) 195 #define CS_PMON_BASE (CS_APB0_BASE + 0x0D000) 196 #define CS_ANAR0_BASE (CS_APB0_BASE + 0x0E000) 197 198 /* APB1 peripherals */ 199 #define CS_AONSYSCTRL_BASE (CS_APB1_BASE + 0x00000) 200 #define CS_TIM2_BASE (CS_APB1_BASE + 0x01000) 201 #define CS_WDT4_BASE (CS_APB1_BASE + 0x02000) 202 #define CS_IOMUX_BASE (CS_APB1_BASE + 0x03000) 203 #define CS_GPIO_BASE (CS_APB1_BASE + 0x04000) 204 #define CS_PSIM_BASE (CS_APB1_BASE + 0x05000) 205 #define CS_PWRCTRL_BASE (CS_APB1_BASE + 0x06000) 206 #define CS_ANAR1_BASE (CS_APB1_BASE + 0x08000) 207 208 /* AHB1 peripherals */ 209 #define CS_I2CS_BASE (CS_AHB1_BASE + 0x18000) 210 #define CS_WCNAON_BASE (CS_AHB1_BASE + 0x80000) 211 212 /* AHB2 peripherals */ 213 #define CS_USB_BASE (CS_AHB2_BASE + 0x00000) 214 #define CS_SDIO_BASE (CS_AHB2_BASE + 0x40000) 215 #define CS_PSRAMR_BASE (CS_AHB2_BASE + 0x41000) 216 #define CS_UHSPSRAMR_BASE (CS_AHB2_BASE + 0x41800) 217 218 #endif // _CHIP_H_ 219