1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone helper functions and enum definitions for 10 // the X86 target useful for the compiler back-end and the MC libraries. 11 // As such, it deliberately does not include references to LLVM core 12 // code gen types, passes, etc.. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 17 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 18 19 #include "X86MCTargetDesc.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/Support/DataTypes.h" 22 #include "llvm/Support/ErrorHandling.h" 23 24 namespace llvm { 25 26 namespace X86 { 27 // Enums for memory operand decoding. Each memory operand is represented with 28 // a 5 operand sequence in the form: 29 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 30 // These enums help decode this. 31 enum { 32 AddrBaseReg = 0, 33 AddrScaleAmt = 1, 34 AddrIndexReg = 2, 35 AddrDisp = 3, 36 37 /// AddrSegmentReg - The operand # of the segment in the memory operand. 38 AddrSegmentReg = 4, 39 40 /// AddrNumOperands - Total number of operands in a memory reference. 41 AddrNumOperands = 5 42 }; 43 44 /// AVX512 static rounding constants. These need to match the values in 45 /// avx512fintrin.h. 46 enum STATIC_ROUNDING { 47 TO_NEAREST_INT = 0, 48 TO_NEG_INF = 1, 49 TO_POS_INF = 2, 50 TO_ZERO = 3, 51 CUR_DIRECTION = 4, 52 NO_EXC = 8 53 }; 54 55 /// The constants to describe instr prefixes if there are 56 enum IPREFIXES { 57 IP_NO_PREFIX = 0, 58 IP_HAS_OP_SIZE = 1, 59 IP_HAS_AD_SIZE = 2, 60 IP_HAS_REPEAT_NE = 4, 61 IP_HAS_REPEAT = 8, 62 IP_HAS_LOCK = 16, 63 IP_HAS_NOTRACK = 32, 64 IP_USE_VEX3 = 64, 65 }; 66 67 enum OperandType : unsigned { 68 /// AVX512 embedded rounding control. This should only have values 0-3. 69 OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET, 70 OPERAND_COND_CODE, 71 }; 72 73 // X86 specific condition code. These correspond to X86_*_COND in 74 // X86InstrInfo.td. They must be kept in synch. 75 enum CondCode { 76 COND_O = 0, 77 COND_NO = 1, 78 COND_B = 2, 79 COND_AE = 3, 80 COND_E = 4, 81 COND_NE = 5, 82 COND_BE = 6, 83 COND_A = 7, 84 COND_S = 8, 85 COND_NS = 9, 86 COND_P = 10, 87 COND_NP = 11, 88 COND_L = 12, 89 COND_GE = 13, 90 COND_LE = 14, 91 COND_G = 15, 92 LAST_VALID_COND = COND_G, 93 94 // Artificial condition codes. These are used by AnalyzeBranch 95 // to indicate a block terminated with two conditional branches that together 96 // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE, 97 // which can't be represented on x86 with a single condition. These 98 // are never used in MachineInstrs and are inverses of one another. 99 COND_NE_OR_P, 100 COND_E_AND_NP, 101 102 COND_INVALID 103 }; 104 105 // The classification for the first instruction in macro fusion. 106 enum class FirstMacroFusionInstKind { 107 // TEST 108 Test, 109 // CMP 110 Cmp, 111 // AND 112 And, 113 // ADD, SUB 114 AddSub, 115 // INC, DEC 116 IncDec, 117 // Not valid as a first macro fusion instruction 118 Invalid 119 }; 120 121 enum class SecondMacroFusionInstKind { 122 // JA, JB and variants. 123 AB, 124 // JE, JL, JG and variants. 125 ELG, 126 // JS, JP, JO and variants 127 SPO, 128 // Not a fusible jump. 129 Invalid, 130 }; 131 132 /// \returns the type of the first instruction in macro-fusion. 133 inline FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)134 classifyFirstOpcodeInMacroFusion(unsigned Opcode) { 135 switch (Opcode) { 136 default: 137 return FirstMacroFusionInstKind::Invalid; 138 // TEST 139 case X86::TEST16i16: 140 case X86::TEST16mr: 141 case X86::TEST16ri: 142 case X86::TEST16rr: 143 case X86::TEST32i32: 144 case X86::TEST32mr: 145 case X86::TEST32ri: 146 case X86::TEST32rr: 147 case X86::TEST64i32: 148 case X86::TEST64mr: 149 case X86::TEST64ri32: 150 case X86::TEST64rr: 151 case X86::TEST8i8: 152 case X86::TEST8mr: 153 case X86::TEST8ri: 154 case X86::TEST8rr: 155 return FirstMacroFusionInstKind::Test; 156 case X86::AND16i16: 157 case X86::AND16ri: 158 case X86::AND16ri8: 159 case X86::AND16rm: 160 case X86::AND16rr: 161 case X86::AND16rr_REV: 162 case X86::AND32i32: 163 case X86::AND32ri: 164 case X86::AND32ri8: 165 case X86::AND32rm: 166 case X86::AND32rr: 167 case X86::AND32rr_REV: 168 case X86::AND64i32: 169 case X86::AND64ri32: 170 case X86::AND64ri8: 171 case X86::AND64rm: 172 case X86::AND64rr: 173 case X86::AND64rr_REV: 174 case X86::AND8i8: 175 case X86::AND8ri: 176 case X86::AND8ri8: 177 case X86::AND8rm: 178 case X86::AND8rr: 179 case X86::AND8rr_REV: 180 return FirstMacroFusionInstKind::And; 181 // CMP 182 case X86::CMP16i16: 183 case X86::CMP16mr: 184 case X86::CMP16ri: 185 case X86::CMP16ri8: 186 case X86::CMP16rm: 187 case X86::CMP16rr: 188 case X86::CMP16rr_REV: 189 case X86::CMP32i32: 190 case X86::CMP32mr: 191 case X86::CMP32ri: 192 case X86::CMP32ri8: 193 case X86::CMP32rm: 194 case X86::CMP32rr: 195 case X86::CMP32rr_REV: 196 case X86::CMP64i32: 197 case X86::CMP64mr: 198 case X86::CMP64ri32: 199 case X86::CMP64ri8: 200 case X86::CMP64rm: 201 case X86::CMP64rr: 202 case X86::CMP64rr_REV: 203 case X86::CMP8i8: 204 case X86::CMP8mr: 205 case X86::CMP8ri: 206 case X86::CMP8ri8: 207 case X86::CMP8rm: 208 case X86::CMP8rr: 209 case X86::CMP8rr_REV: 210 return FirstMacroFusionInstKind::Cmp; 211 // ADD 212 case X86::ADD16i16: 213 case X86::ADD16ri: 214 case X86::ADD16ri8: 215 case X86::ADD16rm: 216 case X86::ADD16rr: 217 case X86::ADD16rr_REV: 218 case X86::ADD32i32: 219 case X86::ADD32ri: 220 case X86::ADD32ri8: 221 case X86::ADD32rm: 222 case X86::ADD32rr: 223 case X86::ADD32rr_REV: 224 case X86::ADD64i32: 225 case X86::ADD64ri32: 226 case X86::ADD64ri8: 227 case X86::ADD64rm: 228 case X86::ADD64rr: 229 case X86::ADD64rr_REV: 230 case X86::ADD8i8: 231 case X86::ADD8ri: 232 case X86::ADD8ri8: 233 case X86::ADD8rm: 234 case X86::ADD8rr: 235 case X86::ADD8rr_REV: 236 // SUB 237 case X86::SUB16i16: 238 case X86::SUB16ri: 239 case X86::SUB16ri8: 240 case X86::SUB16rm: 241 case X86::SUB16rr: 242 case X86::SUB16rr_REV: 243 case X86::SUB32i32: 244 case X86::SUB32ri: 245 case X86::SUB32ri8: 246 case X86::SUB32rm: 247 case X86::SUB32rr: 248 case X86::SUB32rr_REV: 249 case X86::SUB64i32: 250 case X86::SUB64ri32: 251 case X86::SUB64ri8: 252 case X86::SUB64rm: 253 case X86::SUB64rr: 254 case X86::SUB64rr_REV: 255 case X86::SUB8i8: 256 case X86::SUB8ri: 257 case X86::SUB8ri8: 258 case X86::SUB8rm: 259 case X86::SUB8rr: 260 case X86::SUB8rr_REV: 261 return FirstMacroFusionInstKind::AddSub; 262 // INC 263 case X86::INC16r: 264 case X86::INC16r_alt: 265 case X86::INC32r: 266 case X86::INC32r_alt: 267 case X86::INC64r: 268 case X86::INC8r: 269 // DEC 270 case X86::DEC16r: 271 case X86::DEC16r_alt: 272 case X86::DEC32r: 273 case X86::DEC32r_alt: 274 case X86::DEC64r: 275 case X86::DEC8r: 276 return FirstMacroFusionInstKind::IncDec; 277 } 278 } 279 280 /// \returns the type of the second instruction in macro-fusion. 281 inline SecondMacroFusionInstKind classifySecondCondCodeInMacroFusion(X86::CondCode CC)282 classifySecondCondCodeInMacroFusion(X86::CondCode CC) { 283 if (CC == X86::COND_INVALID) 284 return SecondMacroFusionInstKind::Invalid; 285 286 switch (CC) { 287 default: 288 return SecondMacroFusionInstKind::Invalid; 289 // JE,JZ 290 case X86::COND_E: 291 // JNE,JNZ 292 case X86::COND_NE: 293 // JL,JNGE 294 case X86::COND_L: 295 // JLE,JNG 296 case X86::COND_LE: 297 // JG,JNLE 298 case X86::COND_G: 299 // JGE,JNL 300 case X86::COND_GE: 301 return SecondMacroFusionInstKind::ELG; 302 // JB,JC 303 case X86::COND_B: 304 // JNA,JBE 305 case X86::COND_BE: 306 // JA,JNBE 307 case X86::COND_A: 308 // JAE,JNC,JNB 309 case X86::COND_AE: 310 return SecondMacroFusionInstKind::AB; 311 // JS 312 case X86::COND_S: 313 // JNS 314 case X86::COND_NS: 315 // JP,JPE 316 case X86::COND_P: 317 // JNP,JPO 318 case X86::COND_NP: 319 // JO 320 case X86::COND_O: 321 // JNO 322 case X86::COND_NO: 323 return SecondMacroFusionInstKind::SPO; 324 } 325 } 326 327 /// \param FirstKind kind of the first instruction in macro fusion. 328 /// \param SecondKind kind of the second instruction in macro fusion. 329 /// 330 /// \returns true if the two instruction can be macro fused. isMacroFused(FirstMacroFusionInstKind FirstKind,SecondMacroFusionInstKind SecondKind)331 inline bool isMacroFused(FirstMacroFusionInstKind FirstKind, 332 SecondMacroFusionInstKind SecondKind) { 333 switch (FirstKind) { 334 case X86::FirstMacroFusionInstKind::Test: 335 case X86::FirstMacroFusionInstKind::And: 336 return true; 337 case X86::FirstMacroFusionInstKind::Cmp: 338 case X86::FirstMacroFusionInstKind::AddSub: 339 return SecondKind == X86::SecondMacroFusionInstKind::AB || 340 SecondKind == X86::SecondMacroFusionInstKind::ELG; 341 case X86::FirstMacroFusionInstKind::IncDec: 342 return SecondKind == X86::SecondMacroFusionInstKind::ELG; 343 case X86::FirstMacroFusionInstKind::Invalid: 344 return false; 345 } 346 llvm_unreachable("unknown fusion type"); 347 } 348 349 /// Defines the possible values of the branch boundary alignment mask. 350 enum AlignBranchBoundaryKind : uint8_t { 351 AlignBranchNone = 0, 352 AlignBranchFused = 1U << 0, 353 AlignBranchJcc = 1U << 1, 354 AlignBranchJmp = 1U << 2, 355 AlignBranchCall = 1U << 3, 356 AlignBranchRet = 1U << 4, 357 AlignBranchIndirect = 1U << 5 358 }; 359 } // end namespace X86; 360 361 /// X86II - This namespace holds all of the target specific flags that 362 /// instruction info tracks. 363 /// 364 namespace X86II { 365 /// Target Operand Flag enum. 366 enum TOF { 367 //===------------------------------------------------------------------===// 368 // X86 Specific MachineOperand flags. 369 370 MO_NO_FLAG, 371 372 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 373 /// relocation of: 374 /// SYMBOL_LABEL + [. - PICBASELABEL] 375 MO_GOT_ABSOLUTE_ADDRESS, 376 377 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 378 /// immediate should get the value of the symbol minus the PIC base label: 379 /// SYMBOL_LABEL - PICBASELABEL 380 MO_PIC_BASE_OFFSET, 381 382 /// MO_GOT - On a symbol operand this indicates that the immediate is the 383 /// offset to the GOT entry for the symbol name from the base of the GOT. 384 /// 385 /// See the X86-64 ELF ABI supplement for more details. 386 /// SYMBOL_LABEL @GOT 387 MO_GOT, 388 389 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 390 /// the offset to the location of the symbol name from the base of the GOT. 391 /// 392 /// See the X86-64 ELF ABI supplement for more details. 393 /// SYMBOL_LABEL @GOTOFF 394 MO_GOTOFF, 395 396 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 397 /// offset to the GOT entry for the symbol name from the current code 398 /// location. 399 /// 400 /// See the X86-64 ELF ABI supplement for more details. 401 /// SYMBOL_LABEL @GOTPCREL 402 MO_GOTPCREL, 403 404 /// MO_PLT - On a symbol operand this indicates that the immediate is 405 /// offset to the PLT entry of symbol name from the current code location. 406 /// 407 /// See the X86-64 ELF ABI supplement for more details. 408 /// SYMBOL_LABEL @PLT 409 MO_PLT, 410 411 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 412 /// the offset of the GOT entry with the TLS index structure that contains 413 /// the module number and variable offset for the symbol. Used in the 414 /// general dynamic TLS access model. 415 /// 416 /// See 'ELF Handling for Thread-Local Storage' for more details. 417 /// SYMBOL_LABEL @TLSGD 418 MO_TLSGD, 419 420 /// MO_TLSLD - On a symbol operand this indicates that the immediate is 421 /// the offset of the GOT entry with the TLS index for the module that 422 /// contains the symbol. When this index is passed to a call to 423 /// __tls_get_addr, the function will return the base address of the TLS 424 /// block for the symbol. Used in the x86-64 local dynamic TLS access model. 425 /// 426 /// See 'ELF Handling for Thread-Local Storage' for more details. 427 /// SYMBOL_LABEL @TLSLD 428 MO_TLSLD, 429 430 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is 431 /// the offset of the GOT entry with the TLS index for the module that 432 /// contains the symbol. When this index is passed to a call to 433 /// ___tls_get_addr, the function will return the base address of the TLS 434 /// block for the symbol. Used in the IA32 local dynamic TLS access model. 435 /// 436 /// See 'ELF Handling for Thread-Local Storage' for more details. 437 /// SYMBOL_LABEL @TLSLDM 438 MO_TLSLDM, 439 440 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 441 /// the offset of the GOT entry with the thread-pointer offset for the 442 /// symbol. Used in the x86-64 initial exec TLS access model. 443 /// 444 /// See 'ELF Handling for Thread-Local Storage' for more details. 445 /// SYMBOL_LABEL @GOTTPOFF 446 MO_GOTTPOFF, 447 448 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 449 /// the absolute address of the GOT entry with the negative thread-pointer 450 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access 451 /// model. 452 /// 453 /// See 'ELF Handling for Thread-Local Storage' for more details. 454 /// SYMBOL_LABEL @INDNTPOFF 455 MO_INDNTPOFF, 456 457 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 458 /// the thread-pointer offset for the symbol. Used in the x86-64 local 459 /// exec TLS access model. 460 /// 461 /// See 'ELF Handling for Thread-Local Storage' for more details. 462 /// SYMBOL_LABEL @TPOFF 463 MO_TPOFF, 464 465 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is 466 /// the offset of the GOT entry with the TLS offset of the symbol. Used 467 /// in the local dynamic TLS access model. 468 /// 469 /// See 'ELF Handling for Thread-Local Storage' for more details. 470 /// SYMBOL_LABEL @DTPOFF 471 MO_DTPOFF, 472 473 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 474 /// the negative thread-pointer offset for the symbol. Used in the IA32 475 /// local exec TLS access model. 476 /// 477 /// See 'ELF Handling for Thread-Local Storage' for more details. 478 /// SYMBOL_LABEL @NTPOFF 479 MO_NTPOFF, 480 481 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is 482 /// the offset of the GOT entry with the negative thread-pointer offset for 483 /// the symbol. Used in the PIC IA32 initial exec TLS access model. 484 /// 485 /// See 'ELF Handling for Thread-Local Storage' for more details. 486 /// SYMBOL_LABEL @GOTNTPOFF 487 MO_GOTNTPOFF, 488 489 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 490 /// reference is actually to the "__imp_FOO" symbol. This is used for 491 /// dllimport linkage on windows. 492 MO_DLLIMPORT, 493 494 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 495 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 496 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 497 MO_DARWIN_NONLAZY, 498 499 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 500 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 501 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 502 MO_DARWIN_NONLAZY_PIC_BASE, 503 504 /// MO_TLVP - On a symbol operand this indicates that the immediate is 505 /// some TLS offset. 506 /// 507 /// This is the TLS offset for the Darwin TLS mechanism. 508 MO_TLVP, 509 510 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 511 /// is some TLS offset from the picbase. 512 /// 513 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 514 MO_TLVP_PIC_BASE, 515 516 /// MO_SECREL - On a symbol operand this indicates that the immediate is 517 /// the offset from beginning of section. 518 /// 519 /// This is the TLS offset for the COFF/Windows TLS mechanism. 520 MO_SECREL, 521 522 /// MO_ABS8 - On a symbol operand this indicates that the symbol is known 523 /// to be an absolute symbol in range [0,128), so we can use the @ABS8 524 /// symbol modifier. 525 MO_ABS8, 526 527 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the 528 /// reference is actually to the ".refptr.FOO" symbol. This is used for 529 /// stub symbols on windows. 530 MO_COFFSTUB, 531 }; 532 533 enum : uint64_t { 534 //===------------------------------------------------------------------===// 535 // Instruction encodings. These are the standard/most common forms for X86 536 // instructions. 537 // 538 539 // PseudoFrm - This represents an instruction that is a pseudo instruction 540 // or one that has not been implemented yet. It is illegal to code generate 541 // it, but tolerated for intermediate implementation stages. 542 Pseudo = 0, 543 544 /// Raw - This form is for instructions that don't have any operands, so 545 /// they are just a fixed opcode value, like 'leave'. 546 RawFrm = 1, 547 548 /// AddRegFrm - This form is used for instructions like 'push r32' that have 549 /// their one register operand added to their opcode. 550 AddRegFrm = 2, 551 552 /// RawFrmMemOffs - This form is for instructions that store an absolute 553 /// memory offset as an immediate with a possible segment override. 554 RawFrmMemOffs = 3, 555 556 /// RawFrmSrc - This form is for instructions that use the source index 557 /// register SI/ESI/RSI with a possible segment override. 558 RawFrmSrc = 4, 559 560 /// RawFrmDst - This form is for instructions that use the destination index 561 /// register DI/EDI/RDI. 562 RawFrmDst = 5, 563 564 /// RawFrmDstSrc - This form is for instructions that use the source index 565 /// register SI/ESI/RSI with a possible segment override, and also the 566 /// destination index register DI/EDI/RDI. 567 RawFrmDstSrc = 6, 568 569 /// RawFrmImm8 - This is used for the ENTER instruction, which has two 570 /// immediates, the first of which is a 16-bit immediate (specified by 571 /// the imm encoding) and the second is a 8-bit fixed value. 572 RawFrmImm8 = 7, 573 574 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 575 /// immediates, the first of which is a 16 or 32-bit immediate (specified by 576 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 577 /// manual, this operand is described as pntr16:32 and pntr16:16 578 RawFrmImm16 = 8, 579 580 /// AddCCFrm - This form is used for Jcc that encode the condition code 581 /// in the lower 4 bits of the opcode. 582 AddCCFrm = 9, 583 584 /// MRM[0-7][rm] - These forms are used to represent instructions that use 585 /// a Mod/RM byte, and use the middle field to hold extended opcode 586 /// information. In the intel manual these are represented as /0, /1, ... 587 /// 588 589 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 590 /// to specify a destination, which in this case is memory. 591 /// 592 MRMDestMem = 32, 593 594 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 595 /// to specify a source, which in this case is memory. 596 /// 597 MRMSrcMem = 33, 598 599 /// MRMSrcMem4VOp3 - This form is used for instructions that encode 600 /// operand 3 with VEX.VVVV and load from memory. 601 /// 602 MRMSrcMem4VOp3 = 34, 603 604 /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM 605 /// byte to specify the fourth source, which in this case is memory. 606 /// 607 MRMSrcMemOp4 = 35, 608 609 /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM 610 /// byte to specify the operands and also encodes a condition code. 611 /// 612 MRMSrcMemCC = 36, 613 614 /// MRMXm - This form is used for instructions that use the Mod/RM byte 615 /// to specify a memory source, but doesn't use the middle field. And has 616 /// a condition code. 617 /// 618 MRMXmCC = 38, 619 620 /// MRMXm - This form is used for instructions that use the Mod/RM byte 621 /// to specify a memory source, but doesn't use the middle field. 622 /// 623 MRMXm = 39, 624 625 // Next, instructions that operate on a memory r/m operand... 626 MRM0m = 40, MRM1m = 41, MRM2m = 42, MRM3m = 43, // Format /0 /1 /2 /3 627 MRM4m = 44, MRM5m = 45, MRM6m = 46, MRM7m = 47, // Format /4 /5 /6 /7 628 629 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 630 /// to specify a destination, which in this case is a register. 631 /// 632 MRMDestReg = 48, 633 634 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 635 /// to specify a source, which in this case is a register. 636 /// 637 MRMSrcReg = 49, 638 639 /// MRMSrcReg4VOp3 - This form is used for instructions that encode 640 /// operand 3 with VEX.VVVV and do not load from memory. 641 /// 642 MRMSrcReg4VOp3 = 50, 643 644 /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM 645 /// byte to specify the fourth source, which in this case is a register. 646 /// 647 MRMSrcRegOp4 = 51, 648 649 /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM 650 /// byte to specify the operands and also encodes a condition code 651 /// 652 MRMSrcRegCC = 52, 653 654 /// MRMXCCr - This form is used for instructions that use the Mod/RM byte 655 /// to specify a register source, but doesn't use the middle field. And has 656 /// a condition code. 657 /// 658 MRMXrCC = 54, 659 660 /// MRMXr - This form is used for instructions that use the Mod/RM byte 661 /// to specify a register source, but doesn't use the middle field. 662 /// 663 MRMXr = 55, 664 665 // Instructions that operate on a register r/m operand... 666 MRM0r = 56, MRM1r = 57, MRM2r = 58, MRM3r = 59, // Format /0 /1 /2 /3 667 MRM4r = 60, MRM5r = 61, MRM6r = 62, MRM7r = 63, // Format /4 /5 /6 /7 668 669 /// MRM_XX - A mod/rm byte of exactly 0xXX. 670 MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67, 671 MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71, 672 MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75, 673 MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79, 674 MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83, 675 MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87, 676 MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91, 677 MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95, 678 MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99, 679 MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103, 680 MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107, 681 MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111, 682 MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115, 683 MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119, 684 MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123, 685 MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127, 686 687 FormMask = 127, 688 689 //===------------------------------------------------------------------===// 690 // Actual flags... 691 692 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix. 693 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in 694 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66 695 // prefix in 16-bit mode. 696 OpSizeShift = 7, 697 OpSizeMask = 0x3 << OpSizeShift, 698 699 OpSizeFixed = 0 << OpSizeShift, 700 OpSize16 = 1 << OpSizeShift, 701 OpSize32 = 2 << OpSizeShift, 702 703 // AsSize - AdSizeX implies this instruction determines its need of 0x67 704 // prefix from a normal ModRM memory operand. The other types indicate that 705 // an operand is encoded with a specific width and a prefix is needed if 706 // it differs from the current mode. 707 AdSizeShift = OpSizeShift + 2, 708 AdSizeMask = 0x3 << AdSizeShift, 709 710 AdSizeX = 0 << AdSizeShift, 711 AdSize16 = 1 << AdSizeShift, 712 AdSize32 = 2 << AdSizeShift, 713 AdSize64 = 3 << AdSizeShift, 714 715 //===------------------------------------------------------------------===// 716 // OpPrefix - There are several prefix bytes that are used as opcode 717 // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is 718 // no prefix. 719 // 720 OpPrefixShift = AdSizeShift + 2, 721 OpPrefixMask = 0x3 << OpPrefixShift, 722 723 // PD - Prefix code for packed double precision vector floating point 724 // operations performed in the SSE registers. 725 PD = 1 << OpPrefixShift, 726 727 // XS, XD - These prefix codes are for single and double precision scalar 728 // floating point operations performed in the SSE registers. 729 XS = 2 << OpPrefixShift, XD = 3 << OpPrefixShift, 730 731 //===------------------------------------------------------------------===// 732 // OpMap - This field determines which opcode map this instruction 733 // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc. 734 // 735 OpMapShift = OpPrefixShift + 2, 736 OpMapMask = 0x7 << OpMapShift, 737 738 // OB - OneByte - Set if this instruction has a one byte opcode. 739 OB = 0 << OpMapShift, 740 741 // TB - TwoByte - Set if this instruction has a two byte opcode, which 742 // starts with a 0x0F byte before the real opcode. 743 TB = 1 << OpMapShift, 744 745 // T8, TA - Prefix after the 0x0F prefix. 746 T8 = 2 << OpMapShift, TA = 3 << OpMapShift, 747 748 // XOP8 - Prefix to include use of imm byte. 749 XOP8 = 4 << OpMapShift, 750 751 // XOP9 - Prefix to exclude use of imm byte. 752 XOP9 = 5 << OpMapShift, 753 754 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. 755 XOPA = 6 << OpMapShift, 756 757 /// ThreeDNow - This indicates that the instruction uses the 758 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents 759 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction 760 /// storing a classifier in the imm8 field. To simplify our implementation, 761 /// we handle this by storeing the classifier in the opcode field and using 762 /// this flag to indicate that the encoder should do the wacky 3DNow! thing. 763 ThreeDNow = 7 << OpMapShift, 764 765 //===------------------------------------------------------------------===// 766 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 767 // They are used to specify GPRs and SSE registers, 64-bit operand size, 768 // etc. We only cares about REX.W and REX.R bits and only the former is 769 // statically determined. 770 // 771 REXShift = OpMapShift + 3, 772 REX_W = 1 << REXShift, 773 774 //===------------------------------------------------------------------===// 775 // This three-bit field describes the size of an immediate operand. Zero is 776 // unused so that we can tell if we forgot to set a value. 777 ImmShift = REXShift + 1, 778 ImmMask = 15 << ImmShift, 779 Imm8 = 1 << ImmShift, 780 Imm8PCRel = 2 << ImmShift, 781 Imm8Reg = 3 << ImmShift, 782 Imm16 = 4 << ImmShift, 783 Imm16PCRel = 5 << ImmShift, 784 Imm32 = 6 << ImmShift, 785 Imm32PCRel = 7 << ImmShift, 786 Imm32S = 8 << ImmShift, 787 Imm64 = 9 << ImmShift, 788 789 //===------------------------------------------------------------------===// 790 // FP Instruction Classification... Zero is non-fp instruction. 791 792 // FPTypeMask - Mask for all of the FP types... 793 FPTypeShift = ImmShift + 4, 794 FPTypeMask = 7 << FPTypeShift, 795 796 // NotFP - The default, set for instructions that do not use FP registers. 797 NotFP = 0 << FPTypeShift, 798 799 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 800 ZeroArgFP = 1 << FPTypeShift, 801 802 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 803 OneArgFP = 2 << FPTypeShift, 804 805 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 806 // result back to ST(0). For example, fcos, fsqrt, etc. 807 // 808 OneArgFPRW = 3 << FPTypeShift, 809 810 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 811 // explicit argument, storing the result to either ST(0) or the implicit 812 // argument. For example: fadd, fsub, fmul, etc... 813 TwoArgFP = 4 << FPTypeShift, 814 815 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 816 // explicit argument, but have no destination. Example: fucom, fucomi, ... 817 CompareFP = 5 << FPTypeShift, 818 819 // CondMovFP - "2 operand" floating point conditional move instructions. 820 CondMovFP = 6 << FPTypeShift, 821 822 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 823 SpecialFP = 7 << FPTypeShift, 824 825 // Lock prefix 826 LOCKShift = FPTypeShift + 3, 827 LOCK = 1 << LOCKShift, 828 829 // REP prefix 830 REPShift = LOCKShift + 1, 831 REP = 1 << REPShift, 832 833 // Execution domain for SSE instructions. 834 // 0 means normal, non-SSE instruction. 835 SSEDomainShift = REPShift + 1, 836 837 // Encoding 838 EncodingShift = SSEDomainShift + 2, 839 EncodingMask = 0x3 << EncodingShift, 840 841 // VEX - encoding using 0xC4/0xC5 842 VEX = 1 << EncodingShift, 843 844 /// XOP - Opcode prefix used by XOP instructions. 845 XOP = 2 << EncodingShift, 846 847 // VEX_EVEX - Specifies that this instruction use EVEX form which provides 848 // syntax support up to 32 512-bit register operands and up to 7 16-bit 849 // mask operands as well as source operand data swizzling/memory operand 850 // conversion, eviction hint, and rounding mode. 851 EVEX = 3 << EncodingShift, 852 853 // Opcode 854 OpcodeShift = EncodingShift + 2, 855 856 /// VEX_W - Has a opcode specific functionality, but is used in the same 857 /// way as REX_W is for regular SSE instructions. 858 VEX_WShift = OpcodeShift + 8, 859 VEX_W = 1ULL << VEX_WShift, 860 861 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 862 /// address instructions in SSE are represented as 3 address ones in AVX 863 /// and the additional register is encoded in VEX_VVVV prefix. 864 VEX_4VShift = VEX_WShift + 1, 865 VEX_4V = 1ULL << VEX_4VShift, 866 867 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 868 /// instruction uses 256-bit wide registers. This is usually auto detected 869 /// if a VR256 register is used, but some AVX instructions also have this 870 /// field marked when using a f256 memory references. 871 VEX_LShift = VEX_4VShift + 1, 872 VEX_L = 1ULL << VEX_LShift, 873 874 // EVEX_K - Set if this instruction requires masking 875 EVEX_KShift = VEX_LShift + 1, 876 EVEX_K = 1ULL << EVEX_KShift, 877 878 // EVEX_Z - Set if this instruction has EVEX.Z field set. 879 EVEX_ZShift = EVEX_KShift + 1, 880 EVEX_Z = 1ULL << EVEX_ZShift, 881 882 // EVEX_L2 - Set if this instruction has EVEX.L' field set. 883 EVEX_L2Shift = EVEX_ZShift + 1, 884 EVEX_L2 = 1ULL << EVEX_L2Shift, 885 886 // EVEX_B - Set if this instruction has EVEX.B field set. 887 EVEX_BShift = EVEX_L2Shift + 1, 888 EVEX_B = 1ULL << EVEX_BShift, 889 890 // The scaling factor for the AVX512's 8-bit compressed displacement. 891 CD8_Scale_Shift = EVEX_BShift + 1, 892 CD8_Scale_Mask = 127ULL << CD8_Scale_Shift, 893 894 /// Explicitly specified rounding control 895 EVEX_RCShift = CD8_Scale_Shift + 7, 896 EVEX_RC = 1ULL << EVEX_RCShift, 897 898 // NOTRACK prefix 899 NoTrackShift = EVEX_RCShift + 1, 900 NOTRACK = 1ULL << NoTrackShift 901 }; 902 903 /// \returns the "base" X86 opcode for the specified machine 904 /// instruction. getBaseOpcodeFor(uint64_t TSFlags)905 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { 906 return TSFlags >> X86II::OpcodeShift; 907 } 908 hasImm(uint64_t TSFlags)909 inline bool hasImm(uint64_t TSFlags) { 910 return (TSFlags & X86II::ImmMask) != 0; 911 } 912 913 /// Decode the "size of immediate" field from the TSFlags field of the 914 /// specified instruction. getSizeOfImm(uint64_t TSFlags)915 inline unsigned getSizeOfImm(uint64_t TSFlags) { 916 switch (TSFlags & X86II::ImmMask) { 917 default: llvm_unreachable("Unknown immediate size"); 918 case X86II::Imm8: 919 case X86II::Imm8PCRel: 920 case X86II::Imm8Reg: return 1; 921 case X86II::Imm16: 922 case X86II::Imm16PCRel: return 2; 923 case X86II::Imm32: 924 case X86II::Imm32S: 925 case X86II::Imm32PCRel: return 4; 926 case X86II::Imm64: return 8; 927 } 928 } 929 930 /// \returns true if the immediate of the specified instruction's TSFlags 931 /// indicates that it is pc relative. isImmPCRel(uint64_t TSFlags)932 inline bool isImmPCRel(uint64_t TSFlags) { 933 switch (TSFlags & X86II::ImmMask) { 934 default: llvm_unreachable("Unknown immediate size"); 935 case X86II::Imm8PCRel: 936 case X86II::Imm16PCRel: 937 case X86II::Imm32PCRel: 938 return true; 939 case X86II::Imm8: 940 case X86II::Imm8Reg: 941 case X86II::Imm16: 942 case X86II::Imm32: 943 case X86II::Imm32S: 944 case X86II::Imm64: 945 return false; 946 } 947 } 948 949 /// \returns true if the immediate of the specified instruction's 950 /// TSFlags indicates that it is signed. isImmSigned(uint64_t TSFlags)951 inline bool isImmSigned(uint64_t TSFlags) { 952 switch (TSFlags & X86II::ImmMask) { 953 default: llvm_unreachable("Unknown immediate signedness"); 954 case X86II::Imm32S: 955 return true; 956 case X86II::Imm8: 957 case X86II::Imm8PCRel: 958 case X86II::Imm8Reg: 959 case X86II::Imm16: 960 case X86II::Imm16PCRel: 961 case X86II::Imm32: 962 case X86II::Imm32PCRel: 963 case X86II::Imm64: 964 return false; 965 } 966 } 967 968 /// Compute whether all of the def operands are repeated in the uses and 969 /// therefore should be skipped. 970 /// This determines the start of the unique operand list. We need to determine 971 /// if all of the defs have a corresponding tied operand in the uses. 972 /// Unfortunately, the tied operand information is encoded in the uses not 973 /// the defs so we have to use some heuristics to find which operands to 974 /// query. getOperandBias(const MCInstrDesc & Desc)975 inline unsigned getOperandBias(const MCInstrDesc& Desc) { 976 unsigned NumDefs = Desc.getNumDefs(); 977 unsigned NumOps = Desc.getNumOperands(); 978 switch (NumDefs) { 979 default: llvm_unreachable("Unexpected number of defs"); 980 case 0: 981 return 0; 982 case 1: 983 // Common two addr case. 984 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 985 return 1; 986 // Check for AVX-512 scatter which has a TIED_TO in the second to last 987 // operand. 988 if (NumOps == 8 && 989 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0) 990 return 1; 991 return 0; 992 case 2: 993 // XCHG/XADD have two destinations and two sources. 994 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 995 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) 996 return 2; 997 // Check for gather. AVX-512 has the second tied operand early. AVX2 998 // has it as the last op. 999 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 1000 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 || 1001 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1)) 1002 return 2; 1003 return 0; 1004 } 1005 } 1006 1007 /// The function returns the MCInst operand # for the first field of the 1008 /// memory operand. If the instruction doesn't have a 1009 /// memory operand, this returns -1. 1010 /// 1011 /// Note that this ignores tied operands. If there is a tied register which 1012 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 1013 /// counted as one operand. 1014 /// getMemoryOperandNo(uint64_t TSFlags)1015 inline int getMemoryOperandNo(uint64_t TSFlags) { 1016 bool HasVEX_4V = TSFlags & X86II::VEX_4V; 1017 bool HasEVEX_K = TSFlags & X86II::EVEX_K; 1018 1019 switch (TSFlags & X86II::FormMask) { 1020 default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!"); 1021 case X86II::Pseudo: 1022 case X86II::RawFrm: 1023 case X86II::AddRegFrm: 1024 case X86II::RawFrmImm8: 1025 case X86II::RawFrmImm16: 1026 case X86II::RawFrmMemOffs: 1027 case X86II::RawFrmSrc: 1028 case X86II::RawFrmDst: 1029 case X86II::RawFrmDstSrc: 1030 case X86II::AddCCFrm: 1031 return -1; 1032 case X86II::MRMDestMem: 1033 return 0; 1034 case X86II::MRMSrcMem: 1035 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a 1036 // mask register. 1037 return 1 + HasVEX_4V + HasEVEX_K; 1038 case X86II::MRMSrcMem4VOp3: 1039 // Skip registers encoded in reg. 1040 return 1 + HasEVEX_K; 1041 case X86II::MRMSrcMemOp4: 1042 // Skip registers encoded in reg, VEX_VVVV, and I8IMM. 1043 return 3; 1044 case X86II::MRMSrcMemCC: 1045 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a 1046 // mask register. 1047 return 1; 1048 case X86II::MRMDestReg: 1049 case X86II::MRMSrcReg: 1050 case X86II::MRMSrcReg4VOp3: 1051 case X86II::MRMSrcRegOp4: 1052 case X86II::MRMSrcRegCC: 1053 case X86II::MRMXrCC: 1054 case X86II::MRMXr: 1055 case X86II::MRM0r: case X86II::MRM1r: 1056 case X86II::MRM2r: case X86II::MRM3r: 1057 case X86II::MRM4r: case X86II::MRM5r: 1058 case X86II::MRM6r: case X86II::MRM7r: 1059 return -1; 1060 case X86II::MRMXmCC: 1061 case X86II::MRMXm: 1062 case X86II::MRM0m: case X86II::MRM1m: 1063 case X86II::MRM2m: case X86II::MRM3m: 1064 case X86II::MRM4m: case X86II::MRM5m: 1065 case X86II::MRM6m: case X86II::MRM7m: 1066 // Start from 0, skip registers encoded in VEX_VVVV or a mask register. 1067 return 0 + HasVEX_4V + HasEVEX_K; 1068 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: 1069 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5: 1070 case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8: 1071 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: 1072 case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE: 1073 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1: 1074 case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4: 1075 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7: 1076 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA: 1077 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD: 1078 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0: 1079 case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3: 1080 case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6: 1081 case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9: 1082 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: 1083 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF: 1084 case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2: 1085 case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5: 1086 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8: 1087 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB: 1088 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE: 1089 case X86II::MRM_FF: 1090 return -1; 1091 } 1092 } 1093 1094 /// \returns true if the MachineOperand is a x86-64 extended (r8 or 1095 /// higher) register, e.g. r8, xmm8, xmm13, etc. isX86_64ExtendedReg(unsigned RegNo)1096 inline bool isX86_64ExtendedReg(unsigned RegNo) { 1097 if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || 1098 (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) || 1099 (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31)) 1100 return true; 1101 1102 switch (RegNo) { 1103 default: break; 1104 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 1105 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 1106 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 1107 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 1108 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 1109 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 1110 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 1111 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 1112 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: 1113 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: 1114 case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11: 1115 case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15: 1116 return true; 1117 } 1118 return false; 1119 } 1120 1121 /// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher) 1122 /// registers, e.g. zmm21, etc. is32ExtendedReg(unsigned RegNo)1123 static inline bool is32ExtendedReg(unsigned RegNo) { 1124 return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) || 1125 (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) || 1126 (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31)); 1127 } 1128 1129 isX86_64NonExtLowByteReg(unsigned reg)1130 inline bool isX86_64NonExtLowByteReg(unsigned reg) { 1131 return (reg == X86::SPL || reg == X86::BPL || 1132 reg == X86::SIL || reg == X86::DIL); 1133 } 1134 1135 /// \returns true if this is a masked instruction. isKMasked(uint64_t TSFlags)1136 inline bool isKMasked(uint64_t TSFlags) { 1137 return (TSFlags & X86II::EVEX_K) != 0; 1138 } 1139 1140 /// \returns true if this is a merge masked instruction. isKMergeMasked(uint64_t TSFlags)1141 inline bool isKMergeMasked(uint64_t TSFlags) { 1142 return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0; 1143 } 1144 } 1145 1146 } // end namespace llvm; 1147 1148 #endif 1149