1 /*
2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16 #include "i2s_aiao_hi35xx.h"
17 #include "hdf_base.h"
18 #include "hdf_log.h"
19 #include "osal_mem.h"
20 #include "los_vm_iomap.h"
21 #include "osal_io.h"
22
23
24 #define HDF_LOG_TAG i2s_aiao_hi35xx
GetI2sAiaoRxInfo(const struct I2sConfigInfo * i2sCfg)25 void GetI2sAiaoRxInfo(const struct I2sConfigInfo *i2sCfg)
26 {
27 uint32_t value = Hi35xxI2sRegRead(i2sCfg->crg103Addr);
28 I2S_PRINT_LOG_DBG("%s: PERI_CRG103[0x%px][0x%x]", __func__, i2sCfg->crg103Addr, value);
29 value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_AIAO_SWITCH_RX_BCLK);
30 I2S_PRINT_LOG_DBG("%s: I2S_AIAO_SWITCH_RX_BCLK[0x%x][0x%08x]", __func__, I2S_AIAO_SWITCH_RX_BCLK, value);
31 value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_CRG_CFG0_00);
32 I2S_PRINT_LOG_DBG("%s: I2S_CRG_CFG0_00[0x%x][0x%08x]", __func__, I2S_CRG_CFG0_00, value);
33 value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_CRG_CFG1_00);
34 I2S_PRINT_LOG_DBG("%s: I2S_CRG_CFG1_00[0x%x][0x%08x]", __func__, I2S_CRG_CFG1_00, value);
35 value = Hi35xxI2sRegRead(i2sCfg->regBase + RX_IF_ATTR1);
36 I2S_PRINT_LOG_DBG("%s: RX_IF_ATTR1[0x%x][0x%08x]", __func__, RX_IF_ATTR1, value);
37 value = Hi35xxI2sRegRead(i2sCfg->regBase + RX_INT_ENA);
38 I2S_PRINT_LOG_DBG("%s: RX_INT_ENA[0x%x][0x%08x]", __func__, RX_INT_ENA, value);
39 value = Hi35xxI2sRegRead(i2sCfg->regBase + RX_DSP_CTRL);
40 I2S_PRINT_LOG_DBG("%s: RX_DSP_CTRL[0x%x][0x%08x]", __func__, RX_DSP_CTRL, value);
41 value = Hi35xxI2sRegRead(i2sCfg->regBase + RX_BUFF_ASDDR);
42 I2S_PRINT_LOG_DBG("%s: RX_BUFF_ASDDR[0x%x][0x%08x]", __func__, RX_BUFF_ASDDR, value);
43 value = Hi35xxI2sRegRead(i2sCfg->regBase + RX_BUFF_SIZE);
44 I2S_PRINT_LOG_DBG("%s: RX_BUFF_SIZE[0x%x][0x%08x]", __func__, RX_BUFF_SIZE, value);
45 value = Hi35xxI2sRegRead(i2sCfg->regBase + RX_BUFF_WPTR);
46 I2S_PRINT_LOG_DBG("%s: RX_BUFF_WPTR[0x%x][0x%08x]", __func__, RX_BUFF_WPTR, value);
47 value = Hi35xxI2sRegRead(i2sCfg->regBase + RX_BUFF_RPTR);
48 I2S_PRINT_LOG_DBG("%s: RX_BUFF_RPTR[0x%x][0x%08x]", __func__, RX_BUFF_RPTR, value);
49 value = Hi35xxI2sRegRead(i2sCfg->regBase + RX_TRANS_SIZE);
50 I2S_PRINT_LOG_DBG("%s: RX_TRANS_SIZE[0x%x][0x%08x]", __func__, RX_TRANS_SIZE, value);
51 value = Hi35xxI2sRegRead(i2sCfg->regBase + RX_INT_STATUS);
52 I2S_PRINT_LOG_DBG("%s: RX_INT_STATUS[0x%x][0x%08x]", __func__, RX_INT_STATUS, value);
53 }
54
GetI2sAiaoTxInfo(const struct I2sConfigInfo * i2sCfg)55 void GetI2sAiaoTxInfo(const struct I2sConfigInfo *i2sCfg)
56 {
57 uint32_t value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_CRG_CFG0_08);
58 I2S_PRINT_LOG_DBG("%s: I2S_CRG_CFG0_08[0x%08x]", __func__, value);
59 value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_CRG_CFG1_08);
60 I2S_PRINT_LOG_DBG("%s: I2S_CRG_CFG1_08[0x%08x]", __func__, value);
61 value = Hi35xxI2sRegRead(i2sCfg->regBase + TX_IF_ATTR1);
62 I2S_PRINT_LOG_DBG("%s: TX_IF_ATTR1[0x%08x]", __func__, value);
63 value = Hi35xxI2sRegRead(i2sCfg->regBase + TX_INT_ENA);
64 I2S_PRINT_LOG_DBG("%s: TX_INT_ENA[0x%08x]", __func__, value);
65 value = Hi35xxI2sRegRead(i2sCfg->regBase + TX_DSP_CTRL);
66 I2S_PRINT_LOG_DBG("%s: TX_DSP_CTRL[0x%08x]", __func__, value);
67 value = Hi35xxI2sRegRead(i2sCfg->regBase + TX_BUFF_SADDR);
68 I2S_PRINT_LOG_DBG("%s: TX_BUFF_SADDR[0x%08x]", __func__, value);
69 value = Hi35xxI2sRegRead(i2sCfg->regBase + TX_BUFF_SIZE);
70 I2S_PRINT_LOG_DBG("%s: TX_BUFF_SIZE[0x%08x]", __func__, value);
71 value = Hi35xxI2sRegRead(i2sCfg->regBase + TX_BUFF_WPTR);
72 I2S_PRINT_LOG_DBG("%s: TX_BUFF_WPTR[0x%08x]", __func__, value);
73 value = Hi35xxI2sRegRead(i2sCfg->regBase + TX_BUFF_RPTR);
74 I2S_PRINT_LOG_DBG("%s: TX_BUFF_RPTR[0x%08x]", __func__, value);
75 value = Hi35xxI2sRegRead(i2sCfg->regBase + TX_TRANS_SIZE);
76 I2S_PRINT_LOG_DBG("%s: TX_TRANS_SIZE[0x%08x]", __func__, value);
77 value = Hi35xxI2sRegRead(i2sCfg->regBase + TX_INT_STATUS);
78 I2S_PRINT_LOG_DBG("%s: TX_INT_STATUS[0x%08x]", __func__, value);
79 }
80
Hi35xxSampleRateShift(enum I2sSampleRate sampleRate)81 int32_t Hi35xxSampleRateShift(enum I2sSampleRate sampleRate)
82 {
83 uint32_t rate;
84 switch (sampleRate) {
85 case I2S_SAMPLE_RATE_8K:
86 rate = I2S_AIAO_SAMPLE_RATE_8;
87 break;
88 case I2S_SAMPLE_RATE_16K:
89 rate = I2S_AIAO_SAMPLE_RATE_16;
90 break;
91 case I2S_SAMPLE_RATE_32K:
92 rate = I2S_AIAO_SAMPLE_RATE_32;
93 break;
94 case I2S_SAMPLE_RATE_48K:
95 rate = I2S_AIAO_SAMPLE_RATE_48;
96 break;
97 case I2S_SAMPLE_RATE_96K:
98 rate = I2S_AIAO_SAMPLE_RATE_96;
99 break;
100 case I2S_SAMPLE_RATE_192K:
101 rate = I2S_AIAO_SAMPLE_RATE_192;
102 break;
103 default:
104 {
105 I2S_PRINT_LOG_ERR("%s: error sampleRate [%d]", __func__, sampleRate);
106 return HDF_ERR_INVALID_PARAM;
107 }
108 }
109 return rate;
110 }
111
Hi35xxSetCfgAiaoFsclkDiv(uint8_t * pAiaoFsclkDiv,uint16_t fsNum)112 int32_t Hi35xxSetCfgAiaoFsclkDiv(uint8_t *pAiaoFsclkDiv, uint16_t fsNum)
113 {
114 if (pAiaoFsclkDiv == NULL) {
115 HDF_LOGE("%s: pAiaoFsclkDiv NULL", __func__);
116 return HDF_ERR_INVALID_PARAM;
117 }
118 switch (fsNum) {
119 case AIAO_FSCLK_DIV_16:
120 *pAiaoFsclkDiv = 0x0;
121 break;
122 case AIAO_FSCLK_DIV_32:
123 *pAiaoFsclkDiv = 0x1;
124 break;
125 case AIAO_FSCLK_DIV_48:
126 *pAiaoFsclkDiv = 0x2;
127 break;
128 case AIAO_FSCLK_DIV_64:
129 *pAiaoFsclkDiv = 0x3;
130 break;
131 case AIAO_FSCLK_DIV_128:
132 *pAiaoFsclkDiv = 0x4;
133 break;
134 case AIAO_FSCLK_DIV_256:
135 *pAiaoFsclkDiv = 0x5;
136 break;
137 case AIAO_FSCLK_DIV_8:
138 *pAiaoFsclkDiv = 0x6;
139 break;
140 default:
141 {
142 I2S_PRINT_LOG_ERR("%s: error fsNum [%d]", __func__, fsNum);
143 return HDF_ERR_INVALID_PARAM;
144 }
145 }
146 return HDF_SUCCESS;
147 }
148
Hi35xxSetCfgAiaoBclkDiv(uint8_t * pAiaoBclkDiv,uint16_t bclkNum)149 int32_t Hi35xxSetCfgAiaoBclkDiv(uint8_t *pAiaoBclkDiv, uint16_t bclkNum)
150 {
151 if (pAiaoBclkDiv == NULL) {
152 HDF_LOGE("%s: pAiaoBclkDiv NULL", __func__);
153 return HDF_ERR_INVALID_PARAM;
154 }
155
156 switch (bclkNum) {
157 case AIAO_BCLK_DIV_4:
158 *pAiaoBclkDiv = 0x3;
159 break;
160 case AIAO_BCLK_DIV_8:
161 *pAiaoBclkDiv = 0x5;
162 break;
163 default:
164 {
165 HDF_LOGE("%s: error bclkNum [%d]", __func__, bclkNum);
166 return HDF_ERR_INVALID_PARAM;
167 }
168 }
169 return HDF_SUCCESS;
170 }
171
AiaoGetRxIfAttri(struct I2sConfigInfo * i2sCfg,enum I2sProtocolType type,enum I2sChannelMode channelMode,enum I2sChannelIfMode channelIfMode,uint8_t samplePrecision)172 uint32_t AiaoGetRxIfAttri(struct I2sConfigInfo *i2sCfg, enum I2sProtocolType type, enum I2sChannelMode channelMode,
173 enum I2sChannelIfMode channelIfMode, uint8_t samplePrecision)
174 {
175 if (i2sCfg == NULL) {
176 HDF_LOGE("%s: input null", __func__);
177 return HDF_FAILURE;
178 }
179 if (type == I2S_PROTOCOL_I2S_LSB) {
180 i2sCfg->regRxIfAttr1.rxSdOffset = AIAO_RX_SD_OFFSET_LSB;
181 } else if (type == I2S_PROTOCOL_I2S_STD) {
182 i2sCfg->regRxIfAttr1.rxSdOffset = AIAO_RX_SD_OFFSET_STD;
183 } else {
184 HDF_LOGE("%s: rxSdOffset set error %d", __func__, type);
185 return HDF_FAILURE;
186 }
187 I2S_PRINT_LOG_DBG("%s: regRxIfAttr1.rxSdOffset %d", __func__, i2sCfg->regRxIfAttr1.rxSdOffset);
188
189 i2sCfg->channelMode = channelMode;
190 if (channelMode == I2S_CHANNEL_MODE_STEREO) {
191 i2sCfg->regRxIfAttr1.rxChNum = AIAO_RX_CH_NUM_2;
192 } else if (channelMode == I2S_CHANNEL_MODE_MONO) {
193 i2sCfg->regRxIfAttr1.rxChNum = AIAO_RX_CH_NUM_1;
194 } else {
195 HDF_LOGE("%s: rxChNum set error %d", __func__, channelMode);
196 return HDF_FAILURE;
197 }
198 I2S_PRINT_LOG_DBG("%s: regRxIfAttr1.rxChNum %d", __func__, i2sCfg->regRxIfAttr1.rxChNum);
199
200 i2sCfg->channelIfMode = channelIfMode;
201 i2sCfg->samplePrecision = samplePrecision;
202 if (channelIfMode == I2S_CHANNEL_IF_MODE_I2S) {
203 i2sCfg->regRxIfAttr1.rxMode = AIAO_RX_MODE_I2S;
204 if (samplePrecision == I2S_AIAO_SAMPLE_PRECISION_16) {
205 i2sCfg->regRxIfAttr1.rxI2sPrecision = AIAO_RX_I2S_PRECISION_I2S_16;
206 } else if (samplePrecision == I2S_AIAO_SAMPLE_PRECISION_24) {
207 i2sCfg->regRxIfAttr1.rxI2sPrecision = AIAO_RX_I2S_PRECISION_I2S_24;
208 } else {
209 HDF_LOGE("%s: I2S rxI2sPrecision set error %d", __func__, samplePrecision);
210 return HDF_FAILURE;
211 }
212 } else if (channelIfMode == I2S_CHANNEL_IF_MODE_PCM) {
213 i2sCfg->regRxIfAttr1.rxMode = AIAO_RX_MODE_PCM;
214 if (samplePrecision == I2S_AIAO_SAMPLE_PRECISION_16) {
215 i2sCfg->regRxIfAttr1.rxI2sPrecision = AIAO_RX_I2S_PRECISION_PCM_16;
216 } else {
217 HDF_LOGE("%s: PCM rxI2sPrecision set error %d", __func__, samplePrecision);
218 return HDF_FAILURE;
219 }
220 }
221 I2S_PRINT_LOG_DBG("%s: regRxIfAttr1.rxMode %d, rxI2sPrecision %d", __func__,
222 i2sCfg->regRxIfAttr1.rxMode, i2sCfg->regRxIfAttr1.rxI2sPrecision);
223
224 return HDF_SUCCESS;
225 }
226
AiaogetPllFre(void)227 uint32_t AiaogetPllFre(void)
228 {
229 return I2S_AIAO_PLL_FEQ; // default 1188M
230 }
231
AiaoCrgCfg0256Fs(enum I2sSampleRate sampleRate,uint32_t feq)232 uint32_t AiaoCrgCfg0256Fs(enum I2sSampleRate sampleRate, uint32_t feq)
233 {
234 if ((sampleRate == I2S_SAMPLE_RATE_48K) && (feq == I2S_AIAO_PLL_FEQ)) {
235 return AIAO_MCLK_48K_256FS_1188M;
236 } else if ((sampleRate == I2S_SAMPLE_RATE_44_1K) && (feq == I2S_AIAO_PLL_FEQ)) {
237 return AIAO_MCLK_441K_256FS_1188M;
238 } else if ((sampleRate == I2S_SAMPLE_RATE_32K) && (feq == I2S_AIAO_PLL_FEQ)) {
239 return AIAO_MCLK_32K_256FS_1188M;
240 } else {
241 return AIAO_MCLK_48K_256FS_1188M;
242 }
243 }
244
AiaoCrgCfg0320Fs(enum I2sSampleRate sampleRate,uint32_t feq)245 uint32_t AiaoCrgCfg0320Fs(enum I2sSampleRate sampleRate, uint32_t feq)
246 {
247 if ((sampleRate == I2S_SAMPLE_RATE_48K) && (feq == I2S_AIAO_PLL_FEQ)) {
248 return AIAO_MCLK_48K_320FS_1188M;
249 } else if ((sampleRate == I2S_SAMPLE_RATE_44_1K) && (feq == I2S_AIAO_PLL_FEQ)) {
250 return AIAO_MCLK_441K_320FS_1188M;
251 } else if ((sampleRate == I2S_SAMPLE_RATE_32K) && (feq == I2S_AIAO_PLL_FEQ)) {
252 return AIAO_MCLK_32K_320FS_1188M;
253 } else {
254 return AIAO_MCLK_48K_256FS_1188M;
255 }
256 }
257
CfgSetI2sCrgCfg000(const struct I2sConfigInfo * i2sCfg,enum I2slFsSel i2slFsSel,enum I2sSampleRate sampleRate)258 void CfgSetI2sCrgCfg000(const struct I2sConfigInfo *i2sCfg, enum I2slFsSel i2slFsSel, enum I2sSampleRate sampleRate)
259 {
260 uint32_t value;
261 uint32_t feq = AiaogetPllFre();
262 if (i2sCfg == NULL) {
263 HDF_LOGE("%s: input NULL", __func__);
264 return;
265 }
266 I2S_PRINT_LOG_DBG("%s:i2slFsSel[0x%d], sampleRate[0x%d], feq [0x%d]", __func__, i2slFsSel, sampleRate, feq);
267
268 if (i2slFsSel == I2SL_FS_SEL_256_FS) {
269 value = AiaoCrgCfg0256Fs(sampleRate, feq);
270 } else if (i2slFsSel == I2SL_FS_SEL_320_FS) {
271 value = AiaoCrgCfg0320Fs(sampleRate, feq);
272 } else {
273 value = AIAO_MCLK_48K_256FS_1188M;
274 }
275
276 Hi35xxI2sRegWrite(value, i2sCfg->regBase + I2S_CRG_CFG0_00);
277 }
278
CfgSetI2sCrgCfg100(const struct I2sConfigInfo * i2sCfg)279 void CfgSetI2sCrgCfg100(const struct I2sConfigInfo *i2sCfg)
280 {
281 if (i2sCfg == NULL) {
282 I2S_PRINT_LOG_ERR("%s: input NULL", __func__);
283 return;
284 }
285
286 I2S_PRINT_LOG_DBG("%s:[0x%x][0x%x][0x%x][0x%x]", __func__,
287 i2sCfg->regCfg100.aiaoSrstReq, i2sCfg->regCfg100.aiaoCken, i2sCfg->regCfg100.aiaoFsclkDiv,
288 i2sCfg->regCfg100.aiaoBclkDiv);
289
290 /**< bit 9, aiao_srst_req RX0 channel reset */
291 uint32_t value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_CRG_CFG1_00);
292 value &= ~I2S_AIAO_SRST_REQ;
293 value |= (i2sCfg->regCfg100.aiaoSrstReq << I2S_AIAO_SRST_REQ_SHIFT);
294
295 /**< bit 8, aiao_cken MCLK/BCLK/WS clk gate */
296 value &= ~I2S_AIAO_CKEN;
297 value |= (i2sCfg->regCfg100.aiaoCken << I2S_AIAO_CKEN_SHIFT);
298
299 /**< bit [6:4] aiao_fsclk_div, fs=xxx*BCLK */
300 value &= ~I2S_AIAO_FSCLK_DIV;
301 value |= (i2sCfg->regCfg100.aiaoFsclkDiv << I2S_AIAO_FSCLK_DIV_SHIFT);
302
303 /**< bit [3:0], aiao_bclk_div,MCLK=xxx*BCLK */
304 value &= ~I2S_AIAO_BCLK_DIV;
305 value |= (i2sCfg->regCfg100.aiaoBclkDiv << I2S_AIAO_BCLK_DIV_SHIFT);
306
307 Hi35xxI2sRegWrite(value, i2sCfg->regBase + I2S_CRG_CFG1_00);
308 }
309
CfgSetRxIfSAttr1(const struct I2sConfigInfo * i2sCfg)310 void CfgSetRxIfSAttr1(const struct I2sConfigInfo *i2sCfg)
311 {
312 uint32_t value;
313
314 if (i2sCfg == NULL) {
315 HDF_LOGE("%s: input NULL", __func__);
316 return;
317 }
318
319 I2S_PRINT_LOG_DBG("%s:[0x%x][0x%x][0x%x][0x%x][0x%x]", __func__,
320 i2sCfg->regRxIfAttr1.rxSdSourceSel, i2sCfg->regRxIfAttr1.rxSdOffset, i2sCfg->regRxIfAttr1.rxChNum,
321 i2sCfg->regRxIfAttr1.rxI2sPrecision, i2sCfg->regRxIfAttr1.rxMode);
322
323 /**< bit [23:20], rx_sd_source_sel, normal work val = 0x1000 */
324 value = Hi35xxI2sRegRead(i2sCfg->regBase + RX_IF_ATTR1);
325 value &= ~RX_SD_SOURCE_SEL;
326 value |= (i2sCfg->regRxIfAttr1.rxSdSourceSel << RX_SD_SOURCE_SEL_SHIFT);
327
328 /**< bit [15:8], rx_sd_offset, 0x1 STD/ 0x0LSB */
329 value &= ~RX_SD_OFFSET;
330 value |= (i2sCfg->regRxIfAttr1.rxSdOffset << RX_SD_OFFSET_SHIFT);
331
332 /**< bit [6:4], rx_ch_num, rx channel num */
333 value &= ~RX_CH_NUM;
334 value |= (i2sCfg->regRxIfAttr1.rxChNum << RX_CH_NUM_SHIFT);
335
336 /**< bit [3:2], rx_i2s_precision, date sample precision config bit */
337 value &= ~RX_I2S_PRECISION;
338 value |= (i2sCfg->regRxIfAttr1.rxI2sPrecision << RX_I2S_PRECISION_SHIFT);
339
340 /**< bit [1:0], recv channel mode I2S 00/PCM 01 */
341 value &= ~RX_MODE;
342 value |= (i2sCfg->regRxIfAttr1.rxMode << RX_MODE_SHIFT);
343
344 Hi35xxI2sRegWrite(value, i2sCfg->regBase + RX_IF_ATTR1);
345 }
346
CfgSetI2sCrgCfg008(const struct I2sConfigInfo * i2sCfg,enum I2slFsSel i2slFsSel,enum I2sSampleRate sampleRate)347 void CfgSetI2sCrgCfg008(const struct I2sConfigInfo *i2sCfg, enum I2slFsSel i2slFsSel, enum I2sSampleRate sampleRate)
348 {
349 uint32_t value;
350 uint32_t feq = AiaogetPllFre();
351 if (i2sCfg == NULL) {
352 HDF_LOGE("%s: input NULL", __func__);
353 return;
354 }
355 I2S_PRINT_LOG_DBG("%s:i2slFsSel[0x%d], sampleRate[0x%d], feq [0x%d]", __func__, i2slFsSel, sampleRate, feq);
356
357 if (i2slFsSel == I2SL_FS_SEL_256_FS) {
358 value = AiaoCrgCfg0256Fs(sampleRate, feq);
359 } else if (i2slFsSel == I2SL_FS_SEL_320_FS) {
360 value = AiaoCrgCfg0320Fs(sampleRate, feq);
361 } else {
362 value = AIAO_MCLK_48K_256FS_1188M;
363 }
364
365 Hi35xxI2sRegWrite(value, i2sCfg->regBase + I2S_CRG_CFG0_08);
366 }
367
CfgSetI2sCrgCfg108(const struct I2sConfigInfo * i2sCfg)368 void CfgSetI2sCrgCfg108(const struct I2sConfigInfo *i2sCfg)
369 {
370 uint32_t value;
371 if (i2sCfg == NULL) {
372 I2S_PRINT_LOG_ERR("%s: input NULL", __func__);
373 return;
374 }
375
376 I2S_PRINT_LOG_DBG("%s:[0x%x][0x%x][0x%x][0x%x]", __func__,
377 i2sCfg->regCfg100.aiaoSrstReq, i2sCfg->regCfg100.aiaoCken, i2sCfg->regCfg100.aiaoFsclkDiv,
378 i2sCfg->regCfg100.aiaoBclkDiv);
379
380 /**< bit 9, aiao_srst_req RX0 channel reset */
381 value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_CRG_CFG1_08);
382 value &= ~I2S_AIAO_SRST_REQ;
383 value |= (i2sCfg->regCfg100.aiaoSrstReq << I2S_AIAO_SRST_REQ_SHIFT);
384
385 /**< bit 8, aiao_cken MCLK/BCLK/WS clk gate */
386 value &= ~I2S_AIAO_CKEN;
387 value |= (i2sCfg->regCfg100.aiaoCken << I2S_AIAO_CKEN_SHIFT);
388
389 /**< bit [6:4] aiao_fsclk_div, fs=xxx*BCLK */
390 value &= ~I2S_AIAO_FSCLK_DIV;
391 value |= (i2sCfg->regCfg100.aiaoFsclkDiv << I2S_AIAO_FSCLK_DIV_SHIFT);
392
393 /**< bit [3:0], aiao_bclk_div,MCLK=xxx*BCLK */
394 value &= ~I2S_AIAO_BCLK_DIV;
395 value |= (i2sCfg->regCfg100.aiaoBclkDiv << I2S_AIAO_BCLK_DIV_SHIFT);
396
397 Hi35xxI2sRegWrite(value, i2sCfg->regBase + I2S_CRG_CFG1_08);
398 }
399
CfgSetTxIfSAttr1(const struct I2sConfigInfo * i2sCfg)400 void CfgSetTxIfSAttr1(const struct I2sConfigInfo *i2sCfg)
401 {
402 uint32_t value;
403 if (i2sCfg == NULL) {
404 I2S_PRINT_LOG_ERR("%s: input NULL", __func__);
405 return;
406 }
407
408 I2S_PRINT_LOG_DBG("%s:[0x%x][0x%x][0x%x][0x%x][0x%x]", __func__,
409 i2sCfg->regRxIfAttr1.rxSdSourceSel, i2sCfg->regRxIfAttr1.rxSdOffset, i2sCfg->regRxIfAttr1.rxChNum,
410 i2sCfg->regRxIfAttr1.rxI2sPrecision, i2sCfg->regRxIfAttr1.rxMode);
411
412 /**< bit [5:4], Tx_ch_num, Tx channel num */
413 value = Hi35xxI2sRegRead(i2sCfg->regBase + TX_IF_ATTR1);
414 value &= ~TX_CH_NUM;
415 value |= (i2sCfg->regRxIfAttr1.rxChNum << TX_CH_NUM_SHIFT);
416
417 /**< bit [3:2], Tx_i2s_precision, date sample precision config bit */
418 value &= ~TX_I2S_PRECISION;
419 value |= (i2sCfg->regRxIfAttr1.rxI2sPrecision << TX_I2S_PRECISION_SHIFT);
420
421 /**< bit [0:0], Tx_i2s_precision, date sample precision config bit */
422 value &= ~TX_MODE;
423 value |= (i2sCfg->regRxIfAttr1.rxMode << TX_MODE_SHIFT);
424
425 Hi35xxI2sRegWrite(value, i2sCfg->regBase + TX_IF_ATTR1);
426 }
427
CfgSetTxBuffInfo(struct I2sConfigInfo * i2sCfg)428 void CfgSetTxBuffInfo(struct I2sConfigInfo *i2sCfg)
429 {
430 uint32_t value;
431
432 if (i2sCfg == NULL) {
433 HDF_LOGE("%s: input NULL", __func__);
434 return;
435 }
436
437 // record cfg
438 if (i2sCfg->txVirData == NULL) {
439 value = 0x0;
440 I2S_PRINT_LOG_DBG("%s: txData null", __func__);
441 Hi35xxI2sRegWrite(value, i2sCfg->regBase + TX_BUFF_SADDR);
442 Hi35xxI2sRegWrite(value, i2sCfg->regBase + TX_BUFF_WPTR);
443 Hi35xxI2sRegWrite(value, i2sCfg->regBase + TX_BUFF_RPTR);
444 return;
445 }
446
447 Hi35xxI2sRegWrite(i2sCfg->txData, i2sCfg->regBase + TX_BUFF_SADDR);
448
449 i2sCfg->txSize = I2S_AIAO_BUFF_SIZE;
450 Hi35xxI2sRegWrite(I2S_AIAO_BUFF_SIZE, i2sCfg->regBase + TX_BUFF_SIZE);
451
452 value = i2sCfg->txWptr;
453 Hi35xxI2sRegWrite(value, i2sCfg->regBase + TX_BUFF_WPTR);
454
455 value = i2sCfg->txRptr;
456 Hi35xxI2sRegWrite(value, i2sCfg->regBase + TX_BUFF_RPTR);
457
458 i2sCfg->txTransSize = I2X_RX_TRANS_SIZE;
459 Hi35xxI2sRegWrite(i2sCfg->txTransSize, i2sCfg->regBase + TX_TRANS_SIZE);
460 }
461
CfgSetRxBuffInfo(struct I2sConfigInfo * i2sCfg)462 void CfgSetRxBuffInfo(struct I2sConfigInfo *i2sCfg)
463 {
464 uint32_t value;
465
466 if (i2sCfg == NULL) {
467 I2S_PRINT_LOG_ERR("%s: input NULL", __func__);
468 return;
469 }
470
471 if (i2sCfg->rxVirData == NULL) {
472 value = 0x0;
473 I2S_PRINT_LOG_DBG("%s: rxVirData null", __func__);
474 Hi35xxI2sRegWrite(value, i2sCfg->regBase + RX_BUFF_ASDDR);
475 Hi35xxI2sRegWrite(value, i2sCfg->regBase + RX_BUFF_WPTR);
476 Hi35xxI2sRegWrite(value, i2sCfg->regBase + RX_BUFF_RPTR);
477 return;
478 }
479
480 Hi35xxI2sRegWrite(i2sCfg->rxData, i2sCfg->regBase + RX_BUFF_ASDDR);
481
482 i2sCfg->rxSize = I2S_RX_BUFF_SIZE;
483 Hi35xxI2sRegWrite(i2sCfg->rxSize, i2sCfg->regBase + RX_BUFF_SIZE);
484
485 i2sCfg->rxTransSize = I2X_RX_TRANS_SIZE;
486 Hi35xxI2sRegWrite(i2sCfg->rxTransSize, i2sCfg->regBase + RX_TRANS_SIZE);
487
488 value = i2sCfg->rxWptr;
489 Hi35xxI2sRegWrite(value, i2sCfg->regBase + RX_BUFF_WPTR);
490
491 value = i2sCfg->rxRptr;
492 Hi35xxI2sRegWrite(value, i2sCfg->regBase + RX_BUFF_RPTR);
493 }
494
CfgStartRecord(const struct I2sConfigInfo * i2sCfg)495 void CfgStartRecord(const struct I2sConfigInfo *i2sCfg)
496 {
497 uint32_t value;
498 if (i2sCfg == NULL) {
499 HDF_LOGE("%s: input NULL", __func__);
500 return;
501 }
502
503 // START RECORD
504 value = Hi35xxI2sRegRead(i2sCfg->regBase + RX_DSP_CTRL);
505 value &= ~RX_ENABLE;
506 value |= (0x1 << RX_ENABLE_SHIFT);
507 Hi35xxI2sRegWrite(value, i2sCfg->regBase + RX_DSP_CTRL);
508 }
509
CfgStartPlay(struct I2sConfigInfo * i2sCfg)510 void CfgStartPlay(struct I2sConfigInfo *i2sCfg)
511 {
512 uint32_t value;
513 if (i2sCfg == NULL) {
514 HDF_LOGE("%s: input NULL", __func__);
515 return;
516 }
517
518 if (i2sCfg->txEn == false) {
519 // START PLAY
520 value = Hi35xxI2sRegRead(i2sCfg->regBase + TX_DSP_CTRL);
521 value &= ~TX_ENABLE;
522 value |= (0x1 << TX_ENABLE_SHIFT);
523 Hi35xxI2sRegWrite(value, i2sCfg->regBase + TX_DSP_CTRL);
524 i2sCfg->txEn = true;
525 }
526 }
527
Hi35xxI2sReadGetBuff(struct I2sConfigInfo * i2sInfo)528 int32_t Hi35xxI2sReadGetBuff(struct I2sConfigInfo *i2sInfo)
529 {
530 if (i2sInfo == NULL) {
531 HDF_LOGE("%s: input param is invalid", __func__);
532 return HDF_ERR_INVALID_PARAM;
533 }
534
535 i2sInfo->rxVirData = LOS_DmaMemAlloc(&i2sInfo->rxData, I2S_AIAO_BUFF_SIZE, I2S_DDR_BUFF_ALIGN_SIZE, DMA_NOCACHE);
536 if (i2sInfo->rxVirData == NULL) {
537 HDF_LOGE("%s: LOS_DmaMemAlloc rxData error", __func__);
538 return HDF_ERR_MALLOC_FAIL;
539 }
540
541 I2S_PRINT_LOG_DBG("%s: rxVirData:[%px]", __func__, i2sInfo->rxVirData);
542 i2sInfo->rxWptr = 0x0;
543 i2sInfo->rxRptr = 0x0;
544 i2sInfo->rxSize = I2S_AIAO_BUFF_SIZE;
545
546 return HDF_SUCCESS;
547 }
548
Hi35xxI2sWriteGetBuff(struct I2sConfigInfo * i2sInfo)549 int32_t Hi35xxI2sWriteGetBuff(struct I2sConfigInfo *i2sInfo)
550 {
551 if (i2sInfo == NULL) {
552 HDF_LOGE("%s: input param is invalid", __func__);
553 return HDF_ERR_INVALID_PARAM;
554 }
555
556 i2sInfo->txVirData = LOS_DmaMemAlloc(&i2sInfo->txData, I2S_AIAO_BUFF_SIZE, I2S_DDR_BUFF_ALIGN_SIZE, DMA_NOCACHE);
557 if (i2sInfo->txVirData == NULL) {
558 HDF_LOGE("%s: LOS_DmaMemAlloc txVirData error", __func__);
559 return HDF_ERR_MALLOC_FAIL;
560 }
561
562 I2S_PRINT_LOG_DBG("%s: txVirData:[%px], txData[%lx]", __func__, i2sInfo->txVirData, i2sInfo->txData);
563 i2sInfo->txWptr = 0x0;
564 i2sInfo->txRptr = 0x0;
565 i2sInfo->txSize = I2S_AIAO_BUFF_SIZE;
566
567 return HDF_SUCCESS;
568 }
569
570 #define AIAO_ONETIME_TRANS_SIZE 0x1000
GetRxBuffData(struct I2sConfigInfo * i2sCfg,struct I2sMsg * msgs,uint32_t * pOffset)571 int32_t GetRxBuffData(struct I2sConfigInfo *i2sCfg, struct I2sMsg *msgs, uint32_t *pOffset)
572 {
573 if (i2sCfg == NULL || msgs == NULL || pOffset == NULL) {
574 HDF_LOGE("%s: input param is invalid", __func__);
575 return HDF_ERR_INVALID_PARAM;
576 }
577 uint32_t ddrRxDataLen;
578 uint32_t dataLen = 0;
579 uint8_t *pData = NULL;
580 uint32_t transSize = AIAO_ONETIME_TRANS_SIZE;
581 uint32_t rxWptr = Hi35xxI2sRegRead(i2sCfg->regBase + RX_BUFF_WPTR);
582 uint32_t rxRptr = Hi35xxI2sRegRead(i2sCfg->regBase + RX_BUFF_RPTR);
583
584 pData = i2sCfg->rxVirData + rxRptr;
585
586 if (rxRptr <= rxWptr) {
587 ddrRxDataLen = rxWptr - rxRptr;
588 if (ddrRxDataLen > transSize) {
589 dataLen = transSize;
590 *pOffset = rxRptr + transSize;
591 } else {
592 I2S_PRINT_DATA_LOG_DBG("%s: not available data ddrRxDataLen[0x%x], rxRptr[0x%x], rxWptr[0x%x].",
593 __func__, ddrRxDataLen, rxRptr, rxWptr);
594 *pOffset = 0;
595 *msgs->pRlen = 0;
596 return HDF_SUCCESS;
597 }
598 } else {
599 ddrRxDataLen = rxRptr + transSize;
600 if (ddrRxDataLen < i2sCfg->rxSize) {
601 dataLen = transSize;
602 *pOffset = rxRptr + transSize;
603 } else {
604 dataLen = i2sCfg->rxSize - rxRptr;
605 *pOffset = 0;
606 }
607 }
608
609 int ret = LOS_CopyFromKernel((void *)msgs->rbuf, dataLen, i2sCfg->rxVirData + rxRptr, dataLen);
610 if (ret != LOS_OK) {
611 HDF_LOGE("%s: copy from kernel fail:%d", __func__, ret);
612 return HDF_FAILURE;
613 }
614
615 *msgs->pRlen = dataLen;
616
617 return HDF_SUCCESS;
618 }
619
WriteTxBuffData(struct I2sConfigInfo * i2sCfg,struct I2sMsg * msgs,uint32_t txWptr,uint32_t * pOffset)620 int32_t WriteTxBuffData(struct I2sConfigInfo *i2sCfg, struct I2sMsg *msgs,
621 uint32_t txWptr, uint32_t *pOffset)
622 {
623 int ret;
624 uint32_t buffFirstSize;
625 uint32_t buffSecordSize;
626
627 if (i2sCfg == NULL || msgs == NULL || pOffset == NULL) {
628 HDF_LOGE("%s: input param is invalid", __func__);
629 return HDF_ERR_INVALID_PARAM;
630 }
631
632 if ((i2sCfg->txSize - txWptr) >= msgs->len) {
633 *pOffset = txWptr + msgs->len;
634 ret = LOS_CopyToKernel(i2sCfg->txVirData + txWptr, msgs->len, msgs->wbuf, msgs->len);
635 if (ret != LOS_OK) {
636 HDF_LOGE("%s: copy to kernel fail:%d", __func__, ret);
637 return HDF_FAILURE;
638 }
639 if (*pOffset >= i2sCfg->txSize) {
640 *pOffset = 0;
641 }
642 } else {
643 buffFirstSize = i2sCfg->txSize - txWptr;
644 ret = LOS_CopyToKernel(i2sCfg->txVirData + txWptr, buffFirstSize, msgs->wbuf, buffFirstSize);
645 if (ret != LOS_OK) {
646 HDF_LOGE("%s: copy to kernel fail:%d", __func__, ret);
647 return HDF_FAILURE;
648 }
649
650 buffSecordSize = msgs->len - buffFirstSize;
651 ret = LOS_CopyToKernel(i2sCfg->txVirData, buffSecordSize, msgs->wbuf + buffFirstSize, buffSecordSize);
652 if (ret != LOS_OK) {
653 HDF_LOGE("%s: copy to kernel fail:%d", __func__, ret);
654 return HDF_FAILURE;
655 }
656 *pOffset = buffSecordSize;
657 }
658
659 return HDF_SUCCESS;
660 }
661
UpdateTxBuffData(struct I2sConfigInfo * i2sCfg,struct I2sMsg * msgs,uint32_t * pOffset)662 int32_t UpdateTxBuffData(struct I2sConfigInfo *i2sCfg, struct I2sMsg *msgs, uint32_t *pOffset)
663 {
664 if (i2sCfg == NULL || msgs == NULL || msgs->wbuf == NULL || pOffset == NULL) {
665 HDF_LOGE("%s: input param is invalid", __func__);
666 return HDF_ERR_INVALID_PARAM;
667 }
668
669 uint32_t ddrtxDataLen;
670 uint32_t txWptr = Hi35xxI2sRegRead(i2sCfg->regBase + TX_BUFF_WPTR);
671 uint32_t txRptr = Hi35xxI2sRegRead(i2sCfg->regBase + TX_BUFF_RPTR);
672 if (txRptr <= txWptr) {
673 ddrtxDataLen = i2sCfg->txSize - (txWptr - txRptr);
674 if (ddrtxDataLen < (msgs->len + I2S_TX_DATA_MIN)) {
675 I2S_PRINT_LOG_DBG("%s: tx buff full, wait to write", __func__);
676 *msgs->pRlen = 0;
677 *pOffset = 0;
678 return HDF_SUCCESS;
679 }
680 if (WriteTxBuffData(i2sCfg, msgs, txWptr, pOffset) != HDF_SUCCESS) {
681 I2S_PRINT_LOG_ERR("%s: WriteTxBuffData FAILED", __func__);
682 return HDF_FAILURE;
683 }
684 *msgs->pRlen = msgs->len;
685 } else {
686 ddrtxDataLen = txRptr - txWptr;
687 if (ddrtxDataLen < (msgs->len + I2S_TX_DATA_MIN)) {
688 I2S_PRINT_LOG_DBG("%s: tx buff full, wait to write", __func__);
689 *msgs->pRlen = 0;
690 *pOffset = 0;
691 return HDF_SUCCESS;
692 }
693 *pOffset = txWptr + msgs->len;
694
695 int ret = LOS_CopyToKernel(i2sCfg->txVirData + txWptr, msgs->len, msgs->wbuf, msgs->len);
696 if (ret != LOS_OK) {
697 HDF_LOGE("%s: copy to kernel fail:%d", __func__, ret);
698 return HDF_FAILURE;
699 }
700 *msgs->pRlen = msgs->len;
701 }
702
703 return HDF_SUCCESS;
704 }
705
AiaoInit(struct I2sConfigInfo * i2sCfg)706 uint32_t AiaoInit(struct I2sConfigInfo *i2sCfg)
707 {
708 if (i2sCfg == NULL) {
709 I2S_PRINT_LOG_ERR("%s: i2sCfg is null", __func__);
710 return HDF_FAILURE;
711 }
712
713 Hi35xxI2sRegWrite(RX_IF_ATTR1_INIT_VAL, i2sCfg->regBase + RX_IF_ATTR1);
714 Hi35xxI2sRegWrite(TX_IF_ATTR1_INIT_VAL, i2sCfg->regBase + TX_IF_ATTR1);
715 Hi35xxI2sRegWrite(TX_DSP_CTRL_INIT_VAL, i2sCfg->regBase + TX_DSP_CTRL);
716 Hi35xxI2sRegWrite(RX_DSP_CTRL_INIT_VAL, i2sCfg->regBase + RX_DSP_CTRL);
717
718 Hi35xxI2sRegWrite(I2S_CRG_CFG0_08_INIT_VAL, i2sCfg->regBase + I2S_CRG_CFG0_08);
719 Hi35xxI2sRegWrite(I2S_CRG_CFG1_08_INIT_VAL, i2sCfg->regBase + I2S_CRG_CFG1_08);
720 Hi35xxI2sRegWrite(I2S_CRG_CFG0_00_INIT_VAL, i2sCfg->regBase + I2S_CRG_CFG0_00);
721 Hi35xxI2sRegWrite(I2S_CRG_CFG1_00_INIT_VAL, i2sCfg->regBase + I2S_CRG_CFG1_00);
722
723 uint32_t value = Hi35xxI2sRegRead(i2sCfg->regBase + I2S_AIAO_SWITCH_RX_BCLK);
724 value &= ~INNER_BCLK_WS_SEL_RX_00;
725 value |= (0x8 << INNER_BCLK_WS_SEL_RX_00_SHIFT);
726 Hi35xxI2sRegWrite(value, i2sCfg->regBase + I2S_AIAO_SWITCH_RX_BCLK);
727
728 return HDF_SUCCESS;
729 }
730