1 /* 2 * Copyright (c) 2021-2022 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_DAO_H 10 #define HPM_DAO_H 11 12 typedef struct { 13 __RW uint32_t CTRL; /* 0x0: Control Register */ 14 __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */ 15 __RW uint32_t CMD; /* 0x8: Command Register */ 16 __RW uint32_t RX_CFGR; /* 0xC: Configuration Register */ 17 __RW uint32_t RXSLT; /* 0x10: RX Slot Control Register */ 18 __RW uint32_t HPF_MA; /* 0x14: HPF A Coef Register */ 19 __RW uint32_t HPF_B; /* 0x18: HPF B Coef Register */ 20 } DAO_Type; 21 22 23 /* Bitfield definition for register: CTRL */ 24 /* 25 * HPF_EN (RW) 26 * 27 * Whether HPF is enabled. This HPF is used to filter out the DC part. 28 */ 29 #define DAO_CTRL_HPF_EN_MASK (0x20000UL) 30 #define DAO_CTRL_HPF_EN_SHIFT (17U) 31 #define DAO_CTRL_HPF_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_HPF_EN_SHIFT) & DAO_CTRL_HPF_EN_MASK) 32 #define DAO_CTRL_HPF_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_HPF_EN_MASK) >> DAO_CTRL_HPF_EN_SHIFT) 33 34 /* 35 * SAT_ERR_IE (RW) 36 * 37 * Error interrupt enable 38 * This bit controls the generation of an interrupt when an error condition (saturation) occurs. 39 * 0: Error interrupt is masked 40 * 1: Error interrupt is enabled 41 */ 42 #define DAO_CTRL_SAT_ERR_IE_MASK (0x10000UL) 43 #define DAO_CTRL_SAT_ERR_IE_SHIFT (16U) 44 #define DAO_CTRL_SAT_ERR_IE_SET(x) (((uint32_t)(x) << DAO_CTRL_SAT_ERR_IE_SHIFT) & DAO_CTRL_SAT_ERR_IE_MASK) 45 #define DAO_CTRL_SAT_ERR_IE_GET(x) (((uint32_t)(x) & DAO_CTRL_SAT_ERR_IE_MASK) >> DAO_CTRL_SAT_ERR_IE_SHIFT) 46 47 /* 48 * MONO (RW) 49 * 50 * Asserted to let the left and right channel output the same value. 51 */ 52 #define DAO_CTRL_MONO_MASK (0x80U) 53 #define DAO_CTRL_MONO_SHIFT (7U) 54 #define DAO_CTRL_MONO_SET(x) (((uint32_t)(x) << DAO_CTRL_MONO_SHIFT) & DAO_CTRL_MONO_MASK) 55 #define DAO_CTRL_MONO_GET(x) (((uint32_t)(x) & DAO_CTRL_MONO_MASK) >> DAO_CTRL_MONO_SHIFT) 56 57 /* 58 * RIGHT_EN (RW) 59 * 60 * Asserted to enable the right channel 61 */ 62 #define DAO_CTRL_RIGHT_EN_MASK (0x40U) 63 #define DAO_CTRL_RIGHT_EN_SHIFT (6U) 64 #define DAO_CTRL_RIGHT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_RIGHT_EN_SHIFT) & DAO_CTRL_RIGHT_EN_MASK) 65 #define DAO_CTRL_RIGHT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_RIGHT_EN_MASK) >> DAO_CTRL_RIGHT_EN_SHIFT) 66 67 /* 68 * LEFT_EN (RW) 69 * 70 * Asserted to enable the left channel 71 */ 72 #define DAO_CTRL_LEFT_EN_MASK (0x20U) 73 #define DAO_CTRL_LEFT_EN_SHIFT (5U) 74 #define DAO_CTRL_LEFT_EN_SET(x) (((uint32_t)(x) << DAO_CTRL_LEFT_EN_SHIFT) & DAO_CTRL_LEFT_EN_MASK) 75 #define DAO_CTRL_LEFT_EN_GET(x) (((uint32_t)(x) & DAO_CTRL_LEFT_EN_MASK) >> DAO_CTRL_LEFT_EN_SHIFT) 76 77 /* 78 * REMAP (RW) 79 * 80 * 1: Use remap pwm version. The remap version is a version that one pwm output is tied to zero when the input pcm signal is positive or negative 81 * 0: Don't use remap pwm version 82 */ 83 #define DAO_CTRL_REMAP_MASK (0x10U) 84 #define DAO_CTRL_REMAP_SHIFT (4U) 85 #define DAO_CTRL_REMAP_SET(x) (((uint32_t)(x) << DAO_CTRL_REMAP_SHIFT) & DAO_CTRL_REMAP_MASK) 86 #define DAO_CTRL_REMAP_GET(x) (((uint32_t)(x) & DAO_CTRL_REMAP_MASK) >> DAO_CTRL_REMAP_SHIFT) 87 88 /* 89 * INVERT (RW) 90 * 91 * all the outputs are inverted before sending to pad 92 */ 93 #define DAO_CTRL_INVERT_MASK (0x8U) 94 #define DAO_CTRL_INVERT_SHIFT (3U) 95 #define DAO_CTRL_INVERT_SET(x) (((uint32_t)(x) << DAO_CTRL_INVERT_SHIFT) & DAO_CTRL_INVERT_MASK) 96 #define DAO_CTRL_INVERT_GET(x) (((uint32_t)(x) & DAO_CTRL_INVERT_MASK) >> DAO_CTRL_INVERT_SHIFT) 97 98 /* 99 * FALSE_LEVEL (RW) 100 * 101 * the pad output in False run mode, or when the module is disabled 102 * 0: all low 103 * 1: all high 104 * 2: P-high, N-low 105 * 3. output is not enabled 106 */ 107 #define DAO_CTRL_FALSE_LEVEL_MASK (0x6U) 108 #define DAO_CTRL_FALSE_LEVEL_SHIFT (1U) 109 #define DAO_CTRL_FALSE_LEVEL_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_LEVEL_SHIFT) & DAO_CTRL_FALSE_LEVEL_MASK) 110 #define DAO_CTRL_FALSE_LEVEL_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_LEVEL_MASK) >> DAO_CTRL_FALSE_LEVEL_SHIFT) 111 112 /* 113 * FALSE_RUN (RW) 114 * 115 * the module continues to comsume data, but all the pads are constant, thus no audio out 116 */ 117 #define DAO_CTRL_FALSE_RUN_MASK (0x1U) 118 #define DAO_CTRL_FALSE_RUN_SHIFT (0U) 119 #define DAO_CTRL_FALSE_RUN_SET(x) (((uint32_t)(x) << DAO_CTRL_FALSE_RUN_SHIFT) & DAO_CTRL_FALSE_RUN_MASK) 120 #define DAO_CTRL_FALSE_RUN_GET(x) (((uint32_t)(x) & DAO_CTRL_FALSE_RUN_MASK) >> DAO_CTRL_FALSE_RUN_SHIFT) 121 122 /* Bitfield definition for register: CMD */ 123 /* 124 * SFTRST (RW) 125 * 126 * Self-clear 127 */ 128 #define DAO_CMD_SFTRST_MASK (0x2U) 129 #define DAO_CMD_SFTRST_SHIFT (1U) 130 #define DAO_CMD_SFTRST_SET(x) (((uint32_t)(x) << DAO_CMD_SFTRST_SHIFT) & DAO_CMD_SFTRST_MASK) 131 #define DAO_CMD_SFTRST_GET(x) (((uint32_t)(x) & DAO_CMD_SFTRST_MASK) >> DAO_CMD_SFTRST_SHIFT) 132 133 /* 134 * RUN (RW) 135 * 136 * Enable this module to run. 137 */ 138 #define DAO_CMD_RUN_MASK (0x1U) 139 #define DAO_CMD_RUN_SHIFT (0U) 140 #define DAO_CMD_RUN_SET(x) (((uint32_t)(x) << DAO_CMD_RUN_SHIFT) & DAO_CMD_RUN_MASK) 141 #define DAO_CMD_RUN_GET(x) (((uint32_t)(x) & DAO_CMD_RUN_MASK) >> DAO_CMD_RUN_SHIFT) 142 143 /* Bitfield definition for register: RX_CFGR */ 144 /* 145 * CH_MAX (RW) 146 * 147 * CH_MAX[3:0] is the number if channels supported in TDM mode. When not in TDM mode, it must be set as 2. 148 * It must be an even number, so CH_MAX[0] is always 0. 149 * 4'h2: 2 channels 150 * 4'h4: 4 channels 151 * etc 152 */ 153 #define DAO_RX_CFGR_CH_MAX_MASK (0x7C0U) 154 #define DAO_RX_CFGR_CH_MAX_SHIFT (6U) 155 #define DAO_RX_CFGR_CH_MAX_SET(x) (((uint32_t)(x) << DAO_RX_CFGR_CH_MAX_SHIFT) & DAO_RX_CFGR_CH_MAX_MASK) 156 #define DAO_RX_CFGR_CH_MAX_GET(x) (((uint32_t)(x) & DAO_RX_CFGR_CH_MAX_MASK) >> DAO_RX_CFGR_CH_MAX_SHIFT) 157 158 /* Bitfield definition for register: RXSLT */ 159 /* 160 * EN (RW) 161 * 162 * Slot enable for the channels. 163 */ 164 #define DAO_RXSLT_EN_MASK (0xFFFFFFFFUL) 165 #define DAO_RXSLT_EN_SHIFT (0U) 166 #define DAO_RXSLT_EN_SET(x) (((uint32_t)(x) << DAO_RXSLT_EN_SHIFT) & DAO_RXSLT_EN_MASK) 167 #define DAO_RXSLT_EN_GET(x) (((uint32_t)(x) & DAO_RXSLT_EN_MASK) >> DAO_RXSLT_EN_SHIFT) 168 169 /* Bitfield definition for register: HPF_MA */ 170 /* 171 * COEF (RW) 172 * 173 * Composite value of coef A of the Order-1 HPF 174 */ 175 #define DAO_HPF_MA_COEF_MASK (0xFFFFFFFFUL) 176 #define DAO_HPF_MA_COEF_SHIFT (0U) 177 #define DAO_HPF_MA_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_MA_COEF_SHIFT) & DAO_HPF_MA_COEF_MASK) 178 #define DAO_HPF_MA_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_MA_COEF_MASK) >> DAO_HPF_MA_COEF_SHIFT) 179 180 /* Bitfield definition for register: HPF_B */ 181 /* 182 * COEF (RW) 183 * 184 * coef B of the Order-1 HPF 185 */ 186 #define DAO_HPF_B_COEF_MASK (0xFFFFFFFFUL) 187 #define DAO_HPF_B_COEF_SHIFT (0U) 188 #define DAO_HPF_B_COEF_SET(x) (((uint32_t)(x) << DAO_HPF_B_COEF_SHIFT) & DAO_HPF_B_COEF_MASK) 189 #define DAO_HPF_B_COEF_GET(x) (((uint32_t)(x) & DAO_HPF_B_COEF_MASK) >> DAO_HPF_B_COEF_SHIFT) 190 191 192 193 194 #endif /* HPM_DAO_H */