1 /* 2 * Copyright (c) 2021-2022 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_DMA_H 10 #define HPM_DMA_H 11 12 typedef struct { 13 __R uint8_t RESERVED0[16]; /* 0x0 - 0xF: Reserved */ 14 __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */ 15 __R uint8_t RESERVED1[12]; /* 0x14 - 0x1F: Reserved */ 16 __W uint32_t DMACTRL; /* 0x20: DMAC Control Register */ 17 __W uint32_t CHABORT; /* 0x24: Channel Abort Register */ 18 __R uint8_t RESERVED2[8]; /* 0x28 - 0x2F: Reserved */ 19 __W uint32_t INTSTATUS; /* 0x30: Interrupt Status Register */ 20 __R uint32_t CHEN; /* 0x34: Channel Enable Register */ 21 __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */ 22 struct { 23 __RW uint32_t CTRL; /* 0x40: Channel n Control Register */ 24 __RW uint32_t TRANSIZE; /* 0x44: Channel n Transfer Size Register */ 25 __RW uint32_t SRCADDR; /* 0x48: Channel n Source Address Low Part Register */ 26 __RW uint32_t SRCADDRH; /* 0x4C: Channel n Source Address High Part Register */ 27 __RW uint32_t DSTADDR; /* 0x50: Channel n Destination Address Low Part Register */ 28 __RW uint32_t DSTADDRH; /* 0x54: Channel n Destination Address High Part Register */ 29 __RW uint32_t LLPOINTER; /* 0x58: Channel n Linked List Pointer Low Part Register */ 30 __RW uint32_t LLPOINTERH; /* 0x5C: Channel n Linked List Pointer High Part Register */ 31 } CHCTRL[8]; 32 } DMA_Type; 33 34 35 /* Bitfield definition for register: DMACFG */ 36 /* 37 * CHAINXFR (RO) 38 * 39 * Chain transfer 40 * 0x0: Chain transfer is not configured 41 * 0x1: Chain transfer is configured 42 */ 43 #define DMA_DMACFG_CHAINXFR_MASK (0x80000000UL) 44 #define DMA_DMACFG_CHAINXFR_SHIFT (31U) 45 #define DMA_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMA_DMACFG_CHAINXFR_MASK) >> DMA_DMACFG_CHAINXFR_SHIFT) 46 47 /* 48 * REQSYNC (RO) 49 * 50 * DMA request synchronization. The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock, which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization. 51 * 0x0: Request synchronization is not configured 52 * 0x1: Request synchronization is configured 53 */ 54 #define DMA_DMACFG_REQSYNC_MASK (0x40000000UL) 55 #define DMA_DMACFG_REQSYNC_SHIFT (30U) 56 #define DMA_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMA_DMACFG_REQSYNC_MASK) >> DMA_DMACFG_REQSYNC_SHIFT) 57 58 /* 59 * DATAWIDTH (RO) 60 * 61 * AXI bus data width 62 * 0x0: 32 bits 63 * 0x1: 64 bits 64 * 0x2: 128 bits 65 * 0x3: 256 bits 66 */ 67 #define DMA_DMACFG_DATAWIDTH_MASK (0x3000000UL) 68 #define DMA_DMACFG_DATAWIDTH_SHIFT (24U) 69 #define DMA_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_DATAWIDTH_MASK) >> DMA_DMACFG_DATAWIDTH_SHIFT) 70 71 /* 72 * ADDRWIDTH (RO) 73 * 74 * AXI bus address width 75 * 0x18: 24 bits 76 * 0x19: 25 bits 77 * ... 78 * 0x40: 64 bits 79 * Others: Invalid 80 */ 81 #define DMA_DMACFG_ADDRWIDTH_MASK (0xFE0000UL) 82 #define DMA_DMACFG_ADDRWIDTH_SHIFT (17U) 83 #define DMA_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_ADDRWIDTH_MASK) >> DMA_DMACFG_ADDRWIDTH_SHIFT) 84 85 /* 86 * CORENUM (RO) 87 * 88 * DMA core number 89 * 0x0: 1 core 90 * 0x1: 2 cores 91 */ 92 #define DMA_DMACFG_CORENUM_MASK (0x10000UL) 93 #define DMA_DMACFG_CORENUM_SHIFT (16U) 94 #define DMA_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_CORENUM_MASK) >> DMA_DMACFG_CORENUM_SHIFT) 95 96 /* 97 * BUSNUM (RO) 98 * 99 * AXI bus interface number 100 * 0x0: 1 AXI bus 101 * 0x1: 2 AXI busses 102 */ 103 #define DMA_DMACFG_BUSNUM_MASK (0x8000U) 104 #define DMA_DMACFG_BUSNUM_SHIFT (15U) 105 #define DMA_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_BUSNUM_MASK) >> DMA_DMACFG_BUSNUM_SHIFT) 106 107 /* 108 * REQNUM (RO) 109 * 110 * Request/acknowledge pair number 111 * 0x0: 0 pair 112 * 0x1: 1 pair 113 * 0x2: 2 pairs 114 * ... 115 * 0x10: 16 pairs 116 */ 117 #define DMA_DMACFG_REQNUM_MASK (0x7C00U) 118 #define DMA_DMACFG_REQNUM_SHIFT (10U) 119 #define DMA_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_REQNUM_MASK) >> DMA_DMACFG_REQNUM_SHIFT) 120 121 /* 122 * FIFODEPTH (RO) 123 * 124 * FIFO depth 125 * 0x4: 4 entries 126 * 0x8: 8 entries 127 * 0x10: 16 entries 128 * 0x20: 32 entries 129 * Others: Invalid 130 */ 131 #define DMA_DMACFG_FIFODEPTH_MASK (0x3F0U) 132 #define DMA_DMACFG_FIFODEPTH_SHIFT (4U) 133 #define DMA_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMA_DMACFG_FIFODEPTH_MASK) >> DMA_DMACFG_FIFODEPTH_SHIFT) 134 135 /* 136 * CHANNELNUM (RO) 137 * 138 * Channel number 139 * 0x1: 1 channel 140 * 0x2: 2 channels 141 * ... 142 * 0x8: 8 channels 143 * Others: Invalid 144 */ 145 #define DMA_DMACFG_CHANNELNUM_MASK (0xFU) 146 #define DMA_DMACFG_CHANNELNUM_SHIFT (0U) 147 #define DMA_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMA_DMACFG_CHANNELNUM_MASK) >> DMA_DMACFG_CHANNELNUM_SHIFT) 148 149 /* Bitfield definition for register: DMACTRL */ 150 /* 151 * RESET (WO) 152 * 153 * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels. 154 * Note: The software reset may cause the in-completion of AXI transaction. 155 */ 156 #define DMA_DMACTRL_RESET_MASK (0x1U) 157 #define DMA_DMACTRL_RESET_SHIFT (0U) 158 #define DMA_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMA_DMACTRL_RESET_SHIFT) & DMA_DMACTRL_RESET_MASK) 159 #define DMA_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMA_DMACTRL_RESET_MASK) >> DMA_DMACTRL_RESET_SHIFT) 160 161 /* Bitfield definition for register: CHABORT */ 162 /* 163 * CHABORT (WO) 164 * 165 * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled. Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels) 166 */ 167 #define DMA_CHABORT_CHABORT_MASK (0xFFFFFFFFUL) 168 #define DMA_CHABORT_CHABORT_SHIFT (0U) 169 #define DMA_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMA_CHABORT_CHABORT_SHIFT) & DMA_CHABORT_CHABORT_MASK) 170 #define DMA_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMA_CHABORT_CHABORT_MASK) >> DMA_CHABORT_CHABORT_SHIFT) 171 172 /* Bitfield definition for register: INTSTATUS */ 173 /* 174 * TC (W1C) 175 * 176 * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event. 177 * 0x0: Channel n has no terminal count status 178 * 0x1: Channel n has terminal count status 179 */ 180 #define DMA_INTSTATUS_TC_MASK (0xFF0000UL) 181 #define DMA_INTSTATUS_TC_SHIFT (16U) 182 #define DMA_INTSTATUS_TC_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_TC_SHIFT) & DMA_INTSTATUS_TC_MASK) 183 #define DMA_INTSTATUS_TC_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_TC_MASK) >> DMA_INTSTATUS_TC_SHIFT) 184 185 /* 186 * ABORT (W1C) 187 * 188 * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted. 189 * 0x0: Channel n has no abort status 190 * 0x1: Channel n has abort status 191 */ 192 #define DMA_INTSTATUS_ABORT_MASK (0xFF00U) 193 #define DMA_INTSTATUS_ABORT_SHIFT (8U) 194 #define DMA_INTSTATUS_ABORT_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_ABORT_SHIFT) & DMA_INTSTATUS_ABORT_MASK) 195 #define DMA_INTSTATUS_ABORT_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_ABORT_MASK) >> DMA_INTSTATUS_ABORT_SHIFT) 196 197 /* 198 * ERROR (W1C) 199 * 200 * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events: 201 * - Bus error 202 * - Unaligned address 203 * - Unaligned transfer width 204 * - Reserved configuration 205 * 0x0: Channel n has no error status 206 * 0x1: Channel n has error status 207 */ 208 #define DMA_INTSTATUS_ERROR_MASK (0xFFU) 209 #define DMA_INTSTATUS_ERROR_SHIFT (0U) 210 #define DMA_INTSTATUS_ERROR_SET(x) (((uint32_t)(x) << DMA_INTSTATUS_ERROR_SHIFT) & DMA_INTSTATUS_ERROR_MASK) 211 #define DMA_INTSTATUS_ERROR_GET(x) (((uint32_t)(x) & DMA_INTSTATUS_ERROR_MASK) >> DMA_INTSTATUS_ERROR_SHIFT) 212 213 /* Bitfield definition for register: CHEN */ 214 /* 215 * CHEN (RO) 216 * 217 * Alias of the Enable field of all ChnCtrl registers 218 */ 219 #define DMA_CHEN_CHEN_MASK (0xFFFFFFFFUL) 220 #define DMA_CHEN_CHEN_SHIFT (0U) 221 #define DMA_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMA_CHEN_CHEN_MASK) >> DMA_CHEN_CHEN_SHIFT) 222 223 /* Bitfield definition for register of struct array CHCTRL: CTRL */ 224 /* 225 * SRCBUSINFIDX (RW) 226 * 227 * Bus interface index that source data is read from 228 * 0x0: Data is read from bus interface 0 229 * 0x1: Data is read from bus interface 230 */ 231 #define DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK (0x80000000UL) 232 #define DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT (31U) 233 #define DMA_CHCTRL_CTRL_SRCBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT) & DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK) 234 #define DMA_CHCTRL_CTRL_SRCBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCBUSINFIDX_MASK) >> DMA_CHCTRL_CTRL_SRCBUSINFIDX_SHIFT) 235 236 /* 237 * DSTBUSINFIDX (RW) 238 * 239 * Bus interface index that destination data is written to 240 * 0x0: Data is written to bus interface 0 241 * 0x1: Data is written to bus interface 1 242 */ 243 #define DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK (0x40000000UL) 244 #define DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT (30U) 245 #define DMA_CHCTRL_CTRL_DSTBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT) & DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK) 246 #define DMA_CHCTRL_CTRL_DSTBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTBUSINFIDX_MASK) >> DMA_CHCTRL_CTRL_DSTBUSINFIDX_SHIFT) 247 248 /* 249 * PRIORITY (RW) 250 * 251 * Channel priority level 252 * 0x0: Lower priority 253 * 0x1: Higher priority 254 */ 255 #define DMA_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL) 256 #define DMA_CHCTRL_CTRL_PRIORITY_SHIFT (29U) 257 #define DMA_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_PRIORITY_SHIFT) & DMA_CHCTRL_CTRL_PRIORITY_MASK) 258 #define DMA_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_PRIORITY_MASK) >> DMA_CHCTRL_CTRL_PRIORITY_SHIFT) 259 260 /* 261 * SRCBURSTSIZE (RW) 262 * 263 * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration. 264 * The burst transfer byte number is (SrcBurstSize * SrcWidth). 265 * 0x0: 1 transfer 266 * 0x1: 2 transfers 267 * 0x2: 4 transfers 268 * 0x3: 8 transfers 269 * 0x4: 16 transfers 270 * 0x5: 32 transfers 271 * 0x6: 64 transfers 272 * 0x7: 128 transfers 273 * 0x8: 256 transfers 274 * 0x9:512 transfers 275 * 0xa: 1024 transfers 276 * 0xb �?0xf: Reserved, setting this field with a reserved value triggers the error exception 277 */ 278 #define DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL) 279 #define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U) 280 #define DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) 281 #define DMA_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMA_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) 282 283 /* 284 * SRCWIDTH (RW) 285 * 286 * Source transfer width 287 * 0x0: Byte transfer 288 * 0x1: Half-word transfer 289 * 0x2: Word transfer 290 * 0x3: Double word transfer 291 * 0x4: Quad word transfer 292 * 0x5: Eight word transfer 293 * 0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception 294 */ 295 #define DMA_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL) 296 #define DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U) 297 #define DMA_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMA_CHCTRL_CTRL_SRCWIDTH_MASK) 298 #define DMA_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMA_CHCTRL_CTRL_SRCWIDTH_SHIFT) 299 300 /* 301 * DSTWIDTH (RW) 302 * 303 * Destination transfer width. 304 * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width; otherwise the error event will be triggered. For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word. 305 * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number. 306 * 0x0: Byte transfer 307 * 0x1: Half-word transfer 308 * 0x2: Word transfer 309 * 0x3: Double word transfer 310 * 0x4: Quad word transfer 311 * 0x5: Eight word transfer 312 * 0x6�?x7: Reserved, setting this field with a reserved value triggers the error exception 313 */ 314 #define DMA_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL) 315 #define DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U) 316 #define DMA_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMA_CHCTRL_CTRL_DSTWIDTH_MASK) 317 #define DMA_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMA_CHCTRL_CTRL_DSTWIDTH_SHIFT) 318 319 /* 320 * SRCMODE (RW) 321 * 322 * Source DMA handshake mode 323 * 0x0: Normal mode 324 * 0x1: Handshake mode 325 */ 326 #define DMA_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL) 327 #define DMA_CHCTRL_CTRL_SRCMODE_SHIFT (17U) 328 #define DMA_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCMODE_SHIFT) & DMA_CHCTRL_CTRL_SRCMODE_MASK) 329 #define DMA_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCMODE_MASK) >> DMA_CHCTRL_CTRL_SRCMODE_SHIFT) 330 331 /* 332 * DSTMODE (RW) 333 * 334 * Destination DMA handshake mode 335 * 0x0: Normal mode 336 * 0x1: Handshake mode 337 */ 338 #define DMA_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL) 339 #define DMA_CHCTRL_CTRL_DSTMODE_SHIFT (16U) 340 #define DMA_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTMODE_SHIFT) & DMA_CHCTRL_CTRL_DSTMODE_MASK) 341 #define DMA_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTMODE_MASK) >> DMA_CHCTRL_CTRL_DSTMODE_SHIFT) 342 343 /* 344 * SRCADDRCTRL (RW) 345 * 346 * Source address control 347 * 0x0: Increment address 348 * 0x1: Decrement address 349 * 0x2: Fixed address 350 * 0x3: Reserved, setting the field with this value triggers the error exception 351 */ 352 #define DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U) 353 #define DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U) 354 #define DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) 355 #define DMA_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMA_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) 356 357 /* 358 * DSTADDRCTRL (RW) 359 * 360 * Destination address control 361 * 0x0: Increment address 362 * 0x1: Decrement address 363 * 0x2: Fixed address 364 * 0x3: Reserved, setting the field with this value triggers the error exception 365 */ 366 #define DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U) 367 #define DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U) 368 #define DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) 369 #define DMA_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMA_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) 370 371 /* 372 * SRCREQSEL (RW) 373 * 374 * Source DMA request select. Select the request/ack handshake pair that the source device is connected to. 375 */ 376 #define DMA_CHCTRL_CTRL_SRCREQSEL_MASK (0xF00U) 377 #define DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT (8U) 378 #define DMA_CHCTRL_CTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT) & DMA_CHCTRL_CTRL_SRCREQSEL_MASK) 379 #define DMA_CHCTRL_CTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_SRCREQSEL_MASK) >> DMA_CHCTRL_CTRL_SRCREQSEL_SHIFT) 380 381 /* 382 * DSTREQSEL (RW) 383 * 384 * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to. 385 */ 386 #define DMA_CHCTRL_CTRL_DSTREQSEL_MASK (0xF0U) 387 #define DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT (4U) 388 #define DMA_CHCTRL_CTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT) & DMA_CHCTRL_CTRL_DSTREQSEL_MASK) 389 #define DMA_CHCTRL_CTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_DSTREQSEL_MASK) >> DMA_CHCTRL_CTRL_DSTREQSEL_SHIFT) 390 391 /* 392 * INTABTMASK (RW) 393 * 394 * Channel abort interrupt mask 395 * 0x0: Allow the abort interrupt to be triggered 396 * 0x1: Disable the abort interrupt 397 */ 398 #define DMA_CHCTRL_CTRL_INTABTMASK_MASK (0x8U) 399 #define DMA_CHCTRL_CTRL_INTABTMASK_SHIFT (3U) 400 #define DMA_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMA_CHCTRL_CTRL_INTABTMASK_MASK) 401 #define DMA_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTABTMASK_MASK) >> DMA_CHCTRL_CTRL_INTABTMASK_SHIFT) 402 403 /* 404 * INTERRMASK (RW) 405 * 406 * Channel error interrupt mask 407 * 0x0: Allow the error interrupt to be triggered 408 * 0x1: Disable the error interrupt 409 */ 410 #define DMA_CHCTRL_CTRL_INTERRMASK_MASK (0x4U) 411 #define DMA_CHCTRL_CTRL_INTERRMASK_SHIFT (2U) 412 #define DMA_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMA_CHCTRL_CTRL_INTERRMASK_MASK) 413 #define DMA_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTERRMASK_MASK) >> DMA_CHCTRL_CTRL_INTERRMASK_SHIFT) 414 415 /* 416 * INTTCMASK (RW) 417 * 418 * Channel terminal count interrupt mask 419 * 0x0: Allow the terminal count interrupt to be triggered 420 * 0x1: Disable the terminal count interrupt 421 */ 422 #define DMA_CHCTRL_CTRL_INTTCMASK_MASK (0x2U) 423 #define DMA_CHCTRL_CTRL_INTTCMASK_SHIFT (1U) 424 #define DMA_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMA_CHCTRL_CTRL_INTTCMASK_MASK) 425 #define DMA_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_INTTCMASK_MASK) >> DMA_CHCTRL_CTRL_INTTCMASK_SHIFT) 426 427 /* 428 * ENABLE (RW) 429 * 430 * Channel enable bit 431 * 0x0: Disable 432 * 0x1: Enable 433 */ 434 #define DMA_CHCTRL_CTRL_ENABLE_MASK (0x1U) 435 #define DMA_CHCTRL_CTRL_ENABLE_SHIFT (0U) 436 #define DMA_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_CTRL_ENABLE_SHIFT) & DMA_CHCTRL_CTRL_ENABLE_MASK) 437 #define DMA_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_CTRL_ENABLE_MASK) >> DMA_CHCTRL_CTRL_ENABLE_SHIFT) 438 439 /* Bitfield definition for register of struct array CHCTRL: TRANSIZE */ 440 /* 441 * TRANSIZE (RW) 442 * 443 * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done. 444 * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated. 445 */ 446 #define DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFFUL) 447 #define DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U) 448 #define DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK) 449 #define DMA_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMA_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMA_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) 450 451 /* Bitfield definition for register of struct array CHCTRL: SRCADDR */ 452 /* 453 * SRCADDRL (RW) 454 * 455 * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. 456 * This address must be aligned to the source transfer size; otherwise, an error event will be triggered. 457 */ 458 #define DMA_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL) 459 #define DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U) 460 #define DMA_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMA_CHCTRL_SRCADDR_SRCADDRL_MASK) 461 #define DMA_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMA_CHCTRL_SRCADDR_SRCADDRL_SHIFT) 462 463 /* Bitfield definition for register of struct array CHCTRL: SRCADDRH */ 464 /* 465 * SRCADDRH (RW) 466 * 467 * High part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address. 468 * This register exists only when the address bus width is wider than 32 bits. 469 */ 470 #define DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK (0xFFFFFFFFUL) 471 #define DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT (0U) 472 #define DMA_CHCTRL_SRCADDRH_SRCADDRH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT) & DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK) 473 #define DMA_CHCTRL_SRCADDRH_SRCADDRH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_SRCADDRH_SRCADDRH_MASK) >> DMA_CHCTRL_SRCADDRH_SRCADDRH_SHIFT) 474 475 /* Bitfield definition for register of struct array CHCTRL: DSTADDR */ 476 /* 477 * DSTADDRL (RW) 478 * 479 * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. 480 * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. 481 */ 482 #define DMA_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL) 483 #define DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U) 484 #define DMA_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMA_CHCTRL_DSTADDR_DSTADDRL_MASK) 485 #define DMA_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMA_CHCTRL_DSTADDR_DSTADDRL_SHIFT) 486 487 /* Bitfield definition for register of struct array CHCTRL: DSTADDRH */ 488 /* 489 * DSTADDRH (RW) 490 * 491 * High part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address. 492 * This address must be aligned to the destination transfer size; otherwise the error event will be triggered. 493 * This register exists only when the address bus width is wider than 32 bits. 494 */ 495 #define DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK (0xFFFFFFFFUL) 496 #define DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT (0U) 497 #define DMA_CHCTRL_DSTADDRH_DSTADDRH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT) & DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK) 498 #define DMA_CHCTRL_DSTADDRH_DSTADDRH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_DSTADDRH_DSTADDRH_MASK) >> DMA_CHCTRL_DSTADDRH_DSTADDRH_SHIFT) 499 500 /* Bitfield definition for register of struct array CHCTRL: LLPOINTER */ 501 /* 502 * LLPOINTERL (RW) 503 * 504 * Low part of the pointer to the next descriptor. The pointer must be double word aligned. 505 */ 506 #define DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL) 507 #define DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U) 508 #define DMA_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK) 509 #define DMA_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMA_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) 510 511 /* 512 * LLDBUSINFIDX (RW) 513 * 514 * Bus interface index that the next descriptor is read from 515 * 0x0: The next descriptor is read from bus interface 0 516 */ 517 #define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK (0x1U) 518 #define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT (0U) 519 #define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT) & DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK) 520 #define DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_MASK) >> DMA_CHCTRL_LLPOINTER_LLDBUSINFIDX_SHIFT) 521 522 /* Bitfield definition for register of struct array CHCTRL: LLPOINTERH */ 523 /* 524 * LLPOINTERH (RW) 525 * 526 * High part of the pointer to the next descriptor. 527 * This register exists only when the address bus width is wider than 32 bits. 528 */ 529 #define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK (0xFFFFFFFFUL) 530 #define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT (0U) 531 #define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SET(x) (((uint32_t)(x) << DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT) & DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK) 532 #define DMA_CHCTRL_LLPOINTERH_LLPOINTERH_GET(x) (((uint32_t)(x) & DMA_CHCTRL_LLPOINTERH_LLPOINTERH_MASK) >> DMA_CHCTRL_LLPOINTERH_LLPOINTERH_SHIFT) 533 534 535 536 /* CHCTRL register group index macro definition */ 537 #define DMA_CHCTRL_CH0 (0UL) 538 #define DMA_CHCTRL_CH1 (1UL) 539 #define DMA_CHCTRL_CH2 (2UL) 540 #define DMA_CHCTRL_CH3 (3UL) 541 #define DMA_CHCTRL_CH4 (4UL) 542 #define DMA_CHCTRL_CH5 (5UL) 543 #define DMA_CHCTRL_CH6 (6UL) 544 #define DMA_CHCTRL_CH7 (7UL) 545 546 547 #endif /* HPM_DMA_H */