1 /*
2 * Copyright 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef DRM_FOURCC_H
25 #define DRM_FOURCC_H
26
27 #include "drm.h"
28
29 #if defined(__cplusplus)
30 extern "C" {
31 #endif
32
33 /**
34 * DOC: overview
35 *
36 * In the DRM subsystem, framebuffer pixel formats are described using the
37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
40 *
41 * Format Modifiers
42 * ----------------
43 *
44 * Format modifiers are used in conjunction with a fourcc code, forming a
45 * unique fourcc:modifier pair. This format:modifier pair must fully define the
46 * format and data layout of the buffer, and should be the only way to describe
47 * that particular buffer.
48 *
49 * Having multiple fourcc:modifier pairs which describe the same layout should
50 * be avoided, as such aliases run the risk of different drivers exposing
51 * different names for the same data format, forcing userspace to understand
52 * that they are aliases.
53 *
54 * Format modifiers may change any property of the buffer, including the number
55 * of planes and/or the required allocation size. Format modifiers are
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * modifier is specific to the modifer being used. For example, some modifiers
58 * may preserve meaning - such as number of planes - from the fourcc code,
59 * whereas others may not.
60 *
61 * Vendors should document their modifier usage in as much detail as
62 * possible, to ensure maximum compatibility across devices, drivers and
63 * applications.
64 *
65 * The authoritative list of format modifier codes is found in
66 * `include/uapi/drm/drm_fourcc.h`
67 */
68 #define DRM_FOURCC_TWELVE 12
69
70 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | ((__u32)(c) << 16) | ((__u32)(d) << 24))
71
72 #define DRM_FORMAT_BIG_ENDIAN (1U << 31) /* format is big endian instead of little endian */
73
74 /* Reserve 0 for the invalid format specifier */
75 #define DRM_FORMAT_INVALID 0
76
77 /* color index */
78 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
79
80 /* 8 bpp Red */
81 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
82
83 /* 16 bpp Red */
84 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
85
86 /* 16 bpp RG */
87 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
88 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
89
90 /* 32 bpp RG */
91 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
92 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
93
94 /* 8 bpp RGB */
95 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
96 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
97
98 /* 16 bpp RGB */
99 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
100 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
101 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
102 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
103
104 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
105 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
106 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
107 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
108
109 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
110 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
111 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
112 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
113
114 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
115 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
116 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
117 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
118
119 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
120 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
121
122 /* 24 bpp RGB */
123 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
124 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
125
126 /* 32 bpp RGB */
127 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
128 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
129 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
130 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
131
132 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
133 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
134 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
135 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
136
137 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
138 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
139 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
140 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
141
142 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
143 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
144 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
145 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
146
147 /*
148 * Floating point 64bpp RGB
149 * IEEE 754-2008 binary16 half-precision float
150 * [15:0] sign:exponent:mantissa 1:5:10
151 */
152 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
153 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
154
155 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
156 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
157
158 /* packed YCbCr */
159 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
160 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
161 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
162 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
163
164 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
165 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
166 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
167 #define DRM_FORMAT_VUY101010 \
168 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
169
170 /*
171 * packed Y2xx indicate for each component, xx valid data occupy msb
172 * 16-xx padding occupy lsb
173 */
174 #define DRM_FORMAT_Y210 \
175 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels \
176 */
177 #define DRM_FORMAT_Y212 \
178 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels \
179 */
180 #define DRM_FORMAT_Y216 \
181 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
182
183 /*
184 * packed Y4xx indicate for each component, xx valid data occupy msb
185 * 16-xx padding occupy lsb except Y410
186 */
187 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
188 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian \
189 */
190 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
191
192 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
193 #define DRM_FORMAT_XVYU12_16161616 \
194 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
195 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
196
197 /*
198 * packed YCbCr420 2x2 tiled formats
199 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
200 */
201 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
202 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
203 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
204 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
205
206 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
207 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
208 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
209 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
210
211 /*
212 * 1-plane YUV 4:2:0
213 * In these formats, the component ordering is specified (Y, followed by U
214 * then V), but the exact Linear layout is undefined.
215 * These formats can only be used with a non-Linear modifier.
216 */
217 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
218 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
219
220 /*
221 * 2 plane RGB + A
222 * index 0 = RGB plane, same format as the corresponding non _A8 format has
223 * index 1 = A plane, [7:0] A
224 */
225 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
226 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
227 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
228 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
229 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
230 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
231 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
232 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
233
234 /*
235 * 2 plane YCbCr
236 * index 0 = Y plane, [7:0] Y
237 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
238 * or
239 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
240 */
241 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
242 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
243 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
244 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
245 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
246 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
247 /*
248 * 2 plane YCbCr
249 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
250 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
251 */
252 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
253 #define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
254 #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
255
256 /*
257 * 2 plane YCbCr MSB aligned
258 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
259 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
260 */
261 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
262
263 /*
264 * 2 plane YCbCr MSB aligned
265 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
266 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
267 */
268 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
269
270 /*
271 * 2 plane YCbCr MSB aligned
272 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
273 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
274 */
275 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
276
277 /*
278 * 2 plane YCbCr MSB aligned
279 * index 0 = Y plane, [15:0] Y little endian
280 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
281 */
282 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
283
284 /* 3 plane non-subsampled (444) YCbCr
285 * 16 bits per component, but only 10 bits are used and 6 bits are padded
286 * index 0: Y plane, [15:0] Y:x [10:6] little endian
287 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
288 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
289 */
290 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
291
292 /* 3 plane non-subsampled (444) YCrCb
293 * 16 bits per component, but only 10 bits are used and 6 bits are padded
294 * index 0: Y plane, [15:0] Y:x [10:6] little endian
295 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
296 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
297 */
298 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
299
300 /*
301 * 3 plane YCbCr
302 * index 0: Y plane, [7:0] Y
303 * index 1: Cb plane, [7:0] Cb
304 * index 2: Cr plane, [7:0] Cr
305 * or
306 * index 1: Cr plane, [7:0] Cr
307 * index 2: Cb plane, [7:0] Cb
308 */
309 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
310 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
311 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
312 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
313 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
314 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
315 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
316 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
317 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
318 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
319
320 /*
321 * Format Modifiers:
322 *
323 * Format modifiers describe, typically, a re-ordering or modification
324 * of the data in a plane of an FB. This can be used to express tiled/
325 * swizzled formats, or compression, or a combination of the two.
326 *
327 * The upper 8 bits of the format modifier are a vendor-id as assigned
328 * below. The lower 56 bits are assigned as vendor sees fit.
329 */
330
331 /* Vendor Ids: */
332 #define DRM_FORMAT_MOD_NONE 0
333 #define DRM_FORMAT_MOD_VENDOR_NONE 0
334 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
335 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
336 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
337 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
338 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
339 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
340 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
341 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
342 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
343 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
344
345 /* add more to the end as needed */
346
347 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
348
349 #define fourcc_mod_code(vendor, val) ((((__u64)DRM_FORMAT_MOD_VENDOR_##vendor) << 56) | ((val)&0x00ffffffffffffffULL))
350
351 /*
352 * Format Modifier tokens:
353 *
354 * When adding a new token please document the layout with a code comment,
355 * similar to the fourcc codes above. drm_fourcc.h is considered the
356 * authoritative source for all of these.
357 *
358 * Generic modifier names:
359 *
360 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
361 * for layouts which are common across multiple vendors. To preserve
362 * compatibility, in cases where a vendor-specific definition already exists and
363 * a generic name for it is desired, the common name is a purely symbolic alias
364 * and must use the same numerical value as the original definition.
365 *
366 * Note that generic names should only be used for modifiers which describe
367 * generic layouts (such as pixel re-ordering), which may have
368 * independently-developed support across multiple vendors.
369 *
370 * In future cases where a generic layout is identified before merging with a
371 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
372 * 'NONE' could be considered. This should only be for obvious, exceptional
373 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
374 * apply to a single vendor.
375 *
376 * Generic names should not be used for cases where multiple hardware vendors
377 * have implementations of the same standardised compression scheme (such as
378 * AFBC). In those cases, all implementations should use the same format
379 * modifier(s), reflecting the vendor of the standard.
380 */
381
382 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
383
384 /*
385 * Invalid Modifier
386 *
387 * This modifier can be used as a sentinel to terminate the format modifiers
388 * list, or to initialize a variable with an invalid modifier. It might also be
389 * used to report an error back to userspace for certain APIs.
390 */
391 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
392
393 /*
394 * Linear Layout
395 *
396 * Just plain linear layout. Note that this is different from no specifying any
397 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
398 * which tells the driver to also take driver-internal information into account
399 * and so might actually result in a tiled framebuffer.
400 */
401 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
402
403 /* Intel framebuffer modifiers */
404
405 /*
406 * Intel X-tiling layout
407 *
408 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
409 * in row-major layout. Within the tile bytes are laid out row-major, with
410 * a platform-dependent stride. On top of that the memory can apply
411 * platform-depending swizzling of some higher address bits into bit6.
412 *
413 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
414 * On earlier platforms the is highly platforms specific and not useful for
415 * cross-driver sharing. It exists since on a given platform it does uniquely
416 * identify the layout in a simple way for i915-specific userspace, which
417 * facilitated conversion of userspace to modifiers. Additionally the exact
418 * format on some really old platforms is not known.
419 */
420 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
421
422 /*
423 * Intel Y-tiling layout
424 *
425 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
426 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
427 * chunks column-major, with a platform-dependent height. On top of that the
428 * memory can apply platform-depending swizzling of some higher address bits
429 * into bit6.
430 *
431 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
432 * On earlier platforms the is highly platforms specific and not useful for
433 * cross-driver sharing. It exists since on a given platform it does uniquely
434 * identify the layout in a simple way for i915-specific userspace, which
435 * facilitated conversion of userspace to modifiers. Additionally the exact
436 * format on some really old platforms is not known.
437 */
438 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
439
440 /*
441 * Intel Yf-tiling layout
442 *
443 * This is a tiled layout using 4Kb tiles in row-major layout.
444 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
445 * are arranged in four groups (two wide, two high) with column-major layout.
446 * Each group therefore consits out of four 256 byte units, which are also laid
447 * out as 2x2 column-major.
448 * 256 byte units are made out of four 64 byte blocks of pixels, producing
449 * either a square block or a 2:1 unit.
450 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
451 * in pixel depends on the pixel depth.
452 */
453 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
454
455 /*
456 * Intel color control surface (CCS) for render compression
457 *
458 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
459 * The main surface will be plane index 0 and must be Y/Yf-tiled,
460 * the CCS will be plane index 1.
461 *
462 * Each CCS tile matches a 1024x512 pixel area of the main surface.
463 * To match certain aspects of the 3D hardware the CCS is
464 * considered to be made up of normal 128Bx32 Y tiles, Thus
465 * the CCS pitch must be specified in multiples of 128 bytes.
466 *
467 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
468 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
469 * But that fact is not relevant unless the memory is accessed
470 * directly.
471 */
472 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
473 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
474
475 /*
476 * Intel color control surfaces (CCS) for Gen-12 render compression.
477 *
478 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
479 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
480 * main surface. In other words, 4 bits in CCS map to a main surface cache
481 * line pair. The main surface pitch is required to be a multiple of four
482 * Y-tile widths.
483 */
484 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
485
486 /*
487 * Intel color control surfaces (CCS) for Gen-12 media compression
488 *
489 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
490 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
491 * main surface. In other words, 4 bits in CCS map to a main surface cache
492 * line pair. The main surface pitch is required to be a multiple of four
493 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
494 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
495 * planes 2 and 3 for the respective CCS.
496 */
497 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
498
499 /*
500 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
501 *
502 * Macroblocks are laid in a Z-shape, and each pixel data is following the
503 * standard NV12 style.
504 * As for NV12, an image is the result of two frame buffers: one for Y,
505 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
506 * Alignment requirements are (for each buffer):
507 * - multiple of 128 pixels for the width
508 * - multiple of 32 pixels for the height
509 *
510 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
511 */
512 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
513
514 /*
515 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
516 *
517 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
518 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
519 * they correspond to their 16x16 luma block.
520 */
521 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
522
523 /*
524 * Qualcomm Compressed Format
525 *
526 * Refers to a compressed variant of the base format that is compressed.
527 * Implementation may be platform and base-format specific.
528 *
529 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
530 * Pixel data pitch/stride is aligned with macrotile width.
531 * Pixel data height is aligned with macrotile height.
532 * Entire pixel data buffer is aligned with 4k(bytes).
533 */
534 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
535
536 /* Vivante framebuffer modifiers */
537
538 /*
539 * Vivante 4x4 tiling layout
540 *
541 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
542 * layout.
543 */
544 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
545
546 /*
547 * Vivante 64x64 super-tiling layout
548 *
549 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
550 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
551 * major layout.
552 *
553 * For more information: see
554 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
555 */
556 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
557
558 /*
559 * Vivante 4x4 tiling layout for dual-pipe
560 *
561 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
562 * different base address. Offsets from the base addresses are therefore halved
563 * compared to the non-split tiled layout.
564 */
565 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
566
567 /*
568 * Vivante 64x64 super-tiling layout for dual-pipe
569 *
570 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
571 * starts at a different base address. Offsets from the base addresses are
572 * therefore halved compared to the non-split super-tiled layout.
573 */
574 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
575
576 /* NVIDIA frame buffer modifiers */
577
578 /*
579 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
580 *
581 * Pixels are arranged in simple tiles of 16 x 16 bytes.
582 */
583 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
584
585 /*
586 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
587 * and Tegra GPUs starting with Tegra K1.
588 *
589 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
590 * based on the architecture generation. GOBs themselves are then arranged in
591 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
592 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
593 * a block depth or height of "4").
594 *
595 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
596 * in full detail.
597 *
598 * Macro
599 * Bits Param Description
600 * ---- ----- -----------------------------------------------------------------
601 *
602 * 3:0 h log2(height) of each block, in GOBs. Placed here for
603 * compatibility with the existing
604 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
605 *
606 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
607 * compatibility with the existing
608 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
609 *
610 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
611 * size). Must be zero.
612 *
613 * Note there is no log2(width) parameter. Some portions of the
614 * hardware support a block width of two gobs, but it is impractical
615 * to use due to lack of support elsewhere, and has no known
616 * benefits.
617 *
618 * 11:9 - Reserved (To support 2D-array textures with variable array stride
619 * in blocks, specified via log2(tile width in blocks)). Must be
620 * zero.
621 *
622 * 19:12 k Page Kind. This value directly maps to a field in the page
623 * tables of all GPUs >= NV50. It affects the exact layout of bits
624 * in memory and can be derived from the tuple
625 *
626 * (format, GPU model, compression type, samples per pixel)
627 *
628 * Where compression type is defined below. If GPU model were
629 * implied by the format modifier, format, or memory buffer, page
630 * kind would not need to be included in the modifier itself, but
631 * since the modifier should define the layout of the associated
632 * memory buffer independent from any device or other context, it
633 * must be included here.
634 *
635 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
636 * starting with Fermi GPUs. Additionally, the mapping between page
637 * kind and bit layout has changed at various points.
638 *
639 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
640 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
641 * 2 = Gob Height 8, Turing+ Page Kind mapping
642 * 3 = Reserved for future use.
643 *
644 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
645 * bit remapping step that occurs at an even lower level than the
646 * page kind and block linear swizzles. This causes the layout of
647 * surfaces mapped in those SOC's GPUs to be incompatible with the
648 * equivalent mapping on other GPUs in the same system.
649 *
650 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
651 * 1 = Desktop GPU and Tegra Xavier+ Layout
652 *
653 * 25:23 c Lossless Framebuffer Compression type.
654 *
655 * 0 = none
656 * 1 = ROP/3D, layout 1, exact compression format implied by Page
657 * Kind field
658 * 2 = ROP/3D, layout 2, exact compression format implied by Page
659 * Kind field
660 * 3 = CDE horizontal
661 * 4 = CDE vertical
662 * 5 = Reserved for future use
663 * 6 = Reserved for future use
664 * 7 = Reserved for future use
665 *
666 * 55:25 - Reserved for future use. Must be zero.
667 */
668 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
669 fourcc_mod_code( \
670 NVIDIA, (0x10 | ((h)&0xf) | (((k)&0xff) << 12) | (((g)&0x3) << 20) | (((s)&0x1) << 22) | (((c)&0x7) << 23)))
671
672 /* To grandfather in prior block linear format modifiers to the above layout,
673 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
674 * with block-linear layouts, is remapped within drivers to the value 0xfe,
675 * which corresponds to the "generic" kind used for simple single-sample
676 * uncompressed color formats on Fermi - Volta GPUs.
677 */
drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)678 static inline __u64 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
679 {
680 if (!(modifier & 0x10) || (modifier & (0xff << DRM_FOURCC_TWELVE))) {
681 return modifier;
682 } else {
683 return modifier | (0xfe << DRM_FOURCC_TWELVE);
684 }
685 }
686
687 /*
688 * 16Bx2 Block Linear layout, used by Tegra K1 and later
689 *
690 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
691 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
692 *
693 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
694 *
695 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
696 * Valid values are:
697 *
698 * 0 == ONE_GOB
699 * 1 == TWO_GOBS
700 * 2 == FOUR_GOBS
701 * 3 == EIGHT_GOBS
702 * 4 == SIXTEEN_GOBS
703 * 5 == THIRTYTWO_GOBS
704 *
705 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
706 * in full detail.
707 */
708 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
709
710 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
711 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
712 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
713 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
714 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
715 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
716
717 /*
718 * Some Broadcom modifiers take parameters, for example the number of
719 * vertical lines in the image. Reserve the lower 32 bits for modifier
720 * type, and the next 24 bits for parameters. Top 8 bits are the
721 * vendor code.
722 */
723 #define _fourcc_mod_broadcom_param_shift 8
724 #define _fourcc_mod_broadcom_param_bits 48
725 #define fourcc_mod_broadcom_code(val, params) \
726 fourcc_mod_code(BROADCOM, ((((__u64)(params)) << (_fourcc_mod_broadcom_param_shift)) | (val)))
727 #define fourcc_mod_broadcom_param(m) \
728 ((int)(((m) >> _fourcc_mod_broadcom_param_shift) & ((1ULL << _fourcc_mod_broadcom_param_bits) - 1)))
729 #define fourcc_mod_broadcom_mod(m) \
730 ((m) & ~(((1ULL << _fourcc_mod_broadcom_param_bits) - 1) << _fourcc_mod_broadcom_param_shift))
731
732 /*
733 * Broadcom VC4 "T" format
734 *
735 * This is the primary layout that the V3D GPU can texture from (it
736 * can't do linear). The T format has:
737 *
738 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
739 * pixels at 32 bit depth.
740 *
741 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
742 * 16x16 pixels).
743 *
744 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
745 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
746 * they're (TR, BR, BL, TL), where bottom left is start of memory.
747 *
748 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
749 * tiles) or right-to-left (odd rows of 4k tiles).
750 */
751 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
752
753 /*
754 * Broadcom SAND format
755 *
756 * This is the native format that the H.264 codec block uses. For VC4
757 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
758 *
759 * The image can be considered to be split into columns, and the
760 * columns are placed consecutively into memory. The width of those
761 * columns can be either 32, 64, 128, or 256 pixels, but in practice
762 * only 128 pixel columns are used.
763 *
764 * The pitch between the start of each column is set to optimally
765 * switch between SDRAM banks. This is passed as the number of lines
766 * of column width in the modifier (we can't use the stride value due
767 * to various core checks that look at it , so you should set the
768 * stride to width*cpp).
769 *
770 * Note that the column height for this format modifier is the same
771 * for all of the planes, assuming that each column contains both Y
772 * and UV. Some SAND-using hardware stores UV in a separate tiled
773 * image from Y to reduce the column height, which is not supported
774 * with these modifiers.
775 */
776
777 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) fourcc_mod_broadcom_code(2, v)
778 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) fourcc_mod_broadcom_code(3, v)
779 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) fourcc_mod_broadcom_code(4, v)
780 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) fourcc_mod_broadcom_code(5, v)
781
782 #define DRM_FORMAT_MOD_BROADCOM_SAND32 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
783 #define DRM_FORMAT_MOD_BROADCOM_SAND64 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
784 #define DRM_FORMAT_MOD_BROADCOM_SAND128 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
785 #define DRM_FORMAT_MOD_BROADCOM_SAND256 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
786
787 /* Broadcom UIF format
788 *
789 * This is the common format for the current Broadcom multimedia
790 * blocks, including V3D 3.x and newer, newer video codecs, and
791 * displays.
792 *
793 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
794 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
795 * stored in columns, with padding between the columns to ensure that
796 * moving from one column to the next doesn't hit the same SDRAM page
797 * bank.
798 *
799 * To calculate the padding, it is assumed that each hardware block
800 * and the software driving it knows the platform's SDRAM page size,
801 * number of banks, and XOR address, and that it's identical between
802 * all blocks using the format. This tiling modifier will use XOR as
803 * necessary to reduce the padding. If a hardware block can't do XOR,
804 * the assumption is that a no-XOR tiling modifier will be created.
805 */
806 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
807
808 /*
809 * Arm Framebuffer Compression (AFBC) modifiers
810 *
811 * AFBC is a proprietary lossless image compression protocol and format.
812 * It provides fine-grained random access and minimizes the amount of data
813 * transferred between IP blocks.
814 *
815 * AFBC has several features which may be supported and/or used, which are
816 * represented using bits in the modifier. Not all combinations are valid,
817 * and different devices or use-cases may support different combinations.
818 *
819 * Further information on the use of AFBC modifiers can be found in
820 * Documentation/gpu/afbc.rst
821 */
822
823 /*
824 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
825 * modifiers) denote the category for modifiers. Currently we have only two
826 * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen
827 * different categories.
828 */
829 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
830 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val)&0x000fffffffffffffULL))
831
832 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
833 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
834
835 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
836
837 /*
838 * AFBC superblock size
839 *
840 * Indicates the superblock size(s) used for the AFBC buffer. The buffer
841 * size (in pixels) must be aligned to a multiple of the superblock size.
842 * Four lowest significant bits(LSBs) are reserved for block size.
843 *
844 * Where one superblock size is specified, it applies to all planes of the
845 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
846 * the first applies to the Luma plane and the second applies to the Chroma
847 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
848 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
849 */
850 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
851 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
852 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
853 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
854 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
855
856 /*
857 * AFBC lossless colorspace transform
858 *
859 * Indicates that the buffer makes use of the AFBC lossless colorspace
860 * transform.
861 */
862 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
863
864 /*
865 * AFBC block-split
866 *
867 * Indicates that the payload of each superblock is split. The second
868 * half of the payload is positioned at a predefined offset from the start
869 * of the superblock payload.
870 */
871 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
872
873 /*
874 * AFBC sparse layout
875 *
876 * This flag indicates that the payload of each superblock must be stored at a
877 * predefined position relative to the other superblocks in the same AFBC
878 * buffer. This order is the same order used by the header buffer. In this mode
879 * each superblock is given the same amount of space as an uncompressed
880 * superblock of the particular format would require, rounding up to the next
881 * multiple of 128 bytes in size.
882 */
883 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
884
885 /*
886 * AFBC copy-block restrict
887 *
888 * Buffers with this flag must obey the copy-block restriction. The restriction
889 * is such that there are no copy-blocks referring across the border of 8x8
890 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
891 */
892 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
893
894 /*
895 * AFBC tiled layout
896 *
897 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
898 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
899 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
900 * larger bpp formats. The order between the tiles is scan line.
901 * When the tiled layout is used, the buffer size (in pixels) must be aligned
902 * to the tile size.
903 */
904 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
905
906 /*
907 * AFBC solid color blocks
908 *
909 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
910 * can be reduced if a whole superblock is a single color.
911 */
912 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
913
914 /*
915 * AFBC double-buffer
916 *
917 * Indicates that the buffer is allocated in a layout safe for front-buffer
918 * rendering.
919 */
920 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
921
922 /*
923 * AFBC buffer content hints
924 *
925 * Indicates that the buffer includes per-superblock content hints.
926 */
927 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
928
929 /* AFBC uncompressed storage mode
930 *
931 * Indicates that the buffer is using AFBC uncompressed storage mode.
932 * In this mode all superblock payloads in the buffer use the uncompressed
933 * storage mode, which is usually only used for data which cannot be compressed.
934 * The buffer layout is the same as for AFBC buffers without USM set, this only
935 * affects the storage mode of the individual superblocks. Note that even a
936 * buffer without USM set may use uncompressed storage mode for some or all
937 * superblocks, USM just guarantees it for all.
938 */
939 #define AFBC_FORMAT_MOD_USM (1ULL << 12)
940
941 /*
942 * Arm 16x16 Block U-Interleaved modifier
943 *
944 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
945 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
946 * in the block are reordered.
947 */
948 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
949
950 /*
951 * Allwinner tiled modifier
952 *
953 * This tiling mode is implemented by the VPU found on all Allwinner platforms,
954 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
955 * planes.
956 *
957 * With this tiling, the luminance samples are disposed in tiles representing
958 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
959 * The pixel order in each tile is linear and the tiles are disposed linearly,
960 * both in row-major order.
961 */
962 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
963
964 /*
965 * Amlogic Video Framebuffer Compression modifiers
966 *
967 * Amlogic uses a proprietary lossless image compression protocol and format
968 * for their hardware video codec accelerators, either video decoders or
969 * video input encoders.
970 *
971 * It considerably reduces memory bandwidth while writing and reading
972 * frames in memory.
973 *
974 * The underlying storage is considered to be 3 components, 8bit or 10-bit
975 * per component YCbCr 420, single plane :
976 * - DRM_FORMAT_YUV420_8BIT
977 * - DRM_FORMAT_YUV420_10BIT
978 *
979 * The first 8 bits of the mode defines the layout, then the following 8 bits
980 * defines the options changing the layout.
981 *
982 * Not all combinations are valid, and different SoCs may support different
983 * combinations of layout and options.
984 */
985 #define __fourcc_mod_amlogic_layout_mask 0xff
986 #define __fourcc_mod_amlogic_options_shift 8
987 #define __fourcc_mod_amlogic_options_mask 0xff
988
989 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
990 fourcc_mod_code(AMLOGIC, \
991 ((__layout)&__fourcc_mod_amlogic_layout_mask) | \
992 (((__options)&__fourcc_mod_amlogic_options_mask) << __fourcc_mod_amlogic_options_shift))
993
994 /* Amlogic FBC Layouts */
995
996 /*
997 * Amlogic FBC Basic Layout
998 *
999 * The basic layout is composed of:
1000 * - a body content organized in 64x32 superblocks with 4096 bytes per
1001 * superblock in default mode.
1002 * - a 32 bytes per 128x64 header block
1003 *
1004 * This layout is transferrable between Amlogic SoCs supporting this modifier.
1005 */
1006 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
1007
1008 /*
1009 * Amlogic FBC Scatter Memory layout
1010 *
1011 * Indicates the header contains IOMMU references to the compressed
1012 * frames content to optimize memory access and layout.
1013 *
1014 * In this mode, only the header memory address is needed, thus the
1015 * content memory organization is tied to the current producer
1016 * execution and cannot be saved/dumped neither transferrable between
1017 * Amlogic SoCs supporting this modifier.
1018 *
1019 * Due to the nature of the layout, these buffers are not expected to
1020 * be accessible by the user-space clients, but only accessible by the
1021 * hardware producers and consumers.
1022 *
1023 * The user-space clients should expect a failure while trying to mmap
1024 * the DMA-BUF handle returned by the producer.
1025 */
1026 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
1027
1028 /* Amlogic FBC Layout Options Bit Mask */
1029
1030 /*
1031 * Amlogic FBC Memory Saving mode
1032 *
1033 * Indicates the storage is packed when pixel size is multiple of word
1034 * boudaries, i.e. 8bit should be stored in this mode to save allocation
1035 * memory.
1036 *
1037 * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1038 * the basic layout and 3200 bytes per 64x32 superblock combined with
1039 * the scatter layout.
1040 */
1041 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
1042
1043 #if defined(__cplusplus)
1044 }
1045 #endif
1046
1047 #endif /* DRM_FOURCC_H */
1048