1 /* 2 * Copyright (c) 2022 ASR Microelectronics (Shanghai) Co., Ltd. All rights reserved. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 /** 17 **************************************************************************************** 18 * 19 * @file lega_cm4.h 20 * 21 * @brief define arm cm4 SOC architecture 22 * 23 **************************************************************************************** 24 */ 25 26 /************************* **************************************/ 27 #ifndef __DUET_CM4_H__ 28 #define __DUET_CM4_H__ 29 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #define __CM0_REV 0 /* !< Core Revision r0p0 */ 37 #define __MPU_PRESENT 0 /* !< combo provide MPU */ 38 #define __ICACHE_PRESENT 1 /* !< instruction cache present */ 39 #define __DCACHE_PRESENT 1 /* !< data cache present */ 40 #define __NVIC_PRIO_BITS 3 /* !< legawifi uses 3 Bits for the Priority Levels */ 41 #define __Vendor_SysTickConfig 0 /* !< Set to 1 if different SysTick Config is used */ 42 // hightest interrupt priority is configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY&((1<<__NVIC_PRIO_BITS)-1)=5 43 // lowest interrupt priority is configLIBRARY_LOWEST_INTERRUPT_PRIORITY&((1<<__NVIC_PRIO_BITS)-1)=7 44 // set normal interrupt priority 6 45 #define configLIBRARY_NORMAL_INTERRUPT_PRIORITY 6 46 47 typedef enum IRQn { 48 /************** Processor Exceptions Numbers ******************************************/ 49 NonMaskableInt_IRQn = -14, /* !< 2 Non Maskable Interrupt */ 50 MemoryManagement_IRQn = -12, /* !< 4 Cortex-M3 Memory Management Interrupt */ 51 BusFault_IRQn = -11, /* !< 5 Cortex-M3 Bus Fault Interrupt */ 52 UsageFault_IRQn = -10, /* !< 6 Cortex-M3 Usage Fault Interrupt */ 53 SVCall_IRQn = -5, /* !< 11 Cortex-M3 SV Call Interrupt */ 54 DebugMonitor_IRQn = -4, /* !< 12 Cortex-M3 Debug Monitor Interrupt */ 55 PendSV_IRQn = -2, /* !< 14 Cortex-M3 Pend SV Interrupt */ 56 SysTick_IRQn = -1, /* !< 15 Cortex-M3 System Tick Interrupt */ 57 /****** Interrupt Numbers *******************************************************/ 58 CEVA_RW_IP_IRQn = 0, /* !< CEVA RW IP Interrupt */ 59 SLEEP_IRQn = 1, /* !< Sleep Wake-Up Interrupt */ 60 WDG_IRQn = 2, /* !< Window WatchDog */ 61 FLASH_IRQn = 3, /* !< FLASH Interrupt */ 62 GPIO_IRQn = 4, /* !< GPIO Interrupt */ 63 TIMER_IRQn = 5, /* !< Timer Interrupt */ 64 CRYPTOCELL310_IRQn = 6, /* !< CryptoCell 310 Interrupt */ 65 DMA_IRQn = 7, /* !< Generic DMA Ctrl Interrupt */ 66 UART0_IRQn = 8, /* !< UART0 Interrupt */ 67 UART1_IRQn = 9, /* !< UART1 Interrupt */ 68 UART2_IRQn = 10, /* !< UART2 Interrupt */ 69 SPI0_IRQn = 11, /* !< SPI0 Interrupt */ 70 SPI1_IRQn = 12, /* !< SPI1 Interrupt */ 71 SPI2_IRQn = 13, /* !< SPI2 */ 72 I2C0_IRQn = 14, /* !< I2C0 Interrupt */ 73 I2C1_IRQn = 15, /* !< I2C1 Interrupt */ 74 SDIO_IRQn = 16, /* !< SDIO Combined Interrupt */ 75 D_APLL_UNLOCK_IRQn = 17, /* !< RF added: D_APLL_UNLOCK Interrupt */ 76 D_SX_UNLOCK_IRQn = 18, /* !< RF added: D_SX_UNLOCK Interrupt */ 77 AUX_ADC_IRQn = 20, /* !< ADC Interrupt */ 78 PLF_WAKEUP_IRQn = 23, /* !< WiFi Platform Wake-Up Interrupt */ 79 I2S_IRQn = 24, /* !< I2S Interrupt */ 80 RW_BLE_IRQn = 25, /* !< BLE Interrupt */ 81 } IRQn_Type; 82 83 // --------------------------------------------------------------------------- 84 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITstatus; 85 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 86 87 typedef unsigned char u8; 88 typedef unsigned short u16; 89 typedef unsigned int u32; 90 // --------------------------------------------------------------------------- 91 92 // --------------------------------------------------------------------------- 93 #define XTAL_26M 26000000 94 95 extern uint32_t system_bus_clk; 96 extern uint32_t system_core_clk; 97 98 #define SYSTEM_CORE_CLOCK system_core_clk 99 #define SYSTEM_CLOCK system_bus_clk 100 101 #define SYSTEM_CORE_CLOCK_INIT (52000000) 102 #define SYSTEM_BUS_CLOCK_INIT (52000000) 103 104 #define HAPS_FPGA 0 105 #define V7_FPGA 1 106 #define FPGA_PLATFORM V7_FPGA 107 108 #define PINMUX_CTRL_REG0 0x40000004 // pad0-7 109 #define PINMUX_CTRL_REG1 0x40000008 // pad8-15 110 #define PINMUX_CTRL_REG2 0x4000000C // pad16-23 111 #define PINMUX_CTRL_REG3 0x40000010 // pad24-31 112 113 #define SYS_REG_BASE 0x40000000 114 #define SYS_REG_BASE_FLASH_CLK ((SYS_REG_BASE + 0x808)) 115 #define PERI_CLK_CFG (SYS_REG_BASE + 0x850) 116 117 #define WIFI_BLE_FLASH_CLK_CTRL_REG (0x40000804) 118 #define APB_PERI_CLK_CTRL_REG (0x40000808) 119 #define ADC_SDIO_BLE_DEBUG_CTRL_REG (0x40000908) 120 #define SYS_REG_BASE_CLK1_ENABLE (SYS_REG_BASE + 0x840) 121 122 #define CC310_CLOCK_ENABLE (1 << 11) 123 124 #define SYS_REG_BASE_CLK1_DISABLE (SYS_REG_BASE + 0x848) 125 #define CC310_CLOCK_DISABLE (1 << 11) 126 127 #define REG_INTERRUPT_ENABLE (SYS_REG_BASE + 0x944) 128 #define REG_INTERRUPT_DISABLE (SYS_REG_BASE + 0x948) 129 130 #define SYS_CRM_SYS_CLK_CTRL1 *((volatile uint32_t *)(SYS_REG_BASE + 0x950)) 131 #define SYS_CRM_REG_0x804 *((volatile uint32_t *)(SYS_REG_BASE + 0x804)) 132 #define SYS_CRM_UART2_FRAC_DIV *((volatile uint32_t *)(SYS_REG_BASE + 0x82C)) 133 134 #define ALWAYS_ON_REGFILE 0x40000A00 135 #define REG_AHB_BUS_CTRL *((volatile uint32_t *)(ALWAYS_ON_REGFILE + 0x90)) 136 137 #define REG_PLF_WAKEUP_INT_EN (0x1<<23) 138 #define SDIO_HCLK_EN (1 << 4) 139 #define PWM_CLK_EN (1 << 2) 140 #define WDG_CLK_EN (1 << 1) 141 #define TIMER_SCLK_EN 0x1 142 143 #define SYS_CRM_WIFI_BLK_CLK *((volatile uint32_t *)(SYS_REG_BASE + 0x85C)) 144 #define MDM_CLKGATEFCTRL0_ADDR 0x60C00874 145 #define MDM_CLKGATEFCTRL0 *((volatile uint32_t *)(MDM_CLKGATEFCTRL0_ADDR)) 146 #define RTC_REG_RCO32K_ADDR 0x40000A44 147 #define RTC_REG_RCO32K *((volatile uint32_t *)(RTC_REG_RCO32K_ADDR)) 148 #define SYS_CRM_CLR_HCLK_REC *((volatile uint32_t *)(SYS_REG_BASE + 0x844)) 149 150 #define TRX_PD_CTRL1_REG_ADDR 0x06 151 #define TRX_PD_CTRL2_REG_ADDR 0x07 152 #define APLL_PD_CTRL_REG_ADDR 0x0D 153 #define APLL_RST_CTRL_REG_ADDR 0x0E 154 #define XO_PD_CTRL_REG_ADDR 0x0F 155 #define APLL_CLK_PHY_REG_ADDR 0x6B 156 #define APLL_FCAL_FSM_CTRL_ADDR 0x6E 157 158 // efuse memory 159 typedef struct { 160 uint8_t mac_addr0[6]; // 0x90-0x95 161 uint8_t freq_err; // 0x96 162 uint8_t tmmt1; // 0x97 163 uint8_t tmmt2; // 0x98 164 uint8_t cus_tx_pwr[19]; // 0x99-0xab 165 uint8_t cal_tx_pwr0[6]; // 0xac-0xb1 166 uint8_t cus_tx_total_pwr[3]; // 0xb2-0xb4 167 uint8_t cal_tx_evm0[6]; // 0xb5-0xba 168 uint8_t ble_tx_pwr0[3]; // 0xbb-0xbd 169 uint8_t reserved1[2]; // 0xbe-0xbf 170 uint8_t mac_addr1[6]; // 0xc0-0xc5 171 uint8_t mac_addr2[6]; // 0xc6-0xcb 172 uint8_t cal_tx_pwr1[6]; // 0xcc-0xd1 173 uint8_t cal_tx_evm1[6]; // 0xd2-0xd7 174 uint8_t cal_tx_pwr2[6]; // 0xd8-0xdd 175 uint8_t cal_tx_evm2[6]; // 0xde-0xe3 176 uint8_t ble_tx_pwr1[3]; // 0xe4-0xe6 177 uint8_t ble_tx_pwr2[3]; // 0xe7-0xe9 178 uint8_t reserved2[6]; // 0xea-0xef 179 } efuse_info_t; 180 #define EFUSE_INFO_START_ADDR 0x90 181 #define EFUSE_INFO_LEN (sizeof(efuse_info_t)) 182 #define EFUSE_INFO_CHIP_TYPE_ADDR 0x1F6 183 184 // #if 1 185 // #define BOOTLOADER_MAX_SIZE 0x10000 186 // #define INFO_MAX_SIZE 0x2000 187 // #define KV_MAX_SIZE 0x18000 188 // #define NVDS_MAX_SIZE 0x2000 189 // #define MIDEA_INFO_MAX_SIZE 0x1000 190 // #define MIDEA_INFO_BKUP_MAX_SIZE 0x1000 191 // #define APP_MAX_SIZE 0x166000 192 // #define OTA_MAX_SIZE 0x166000 193 // #define CUST1_MAX_SIZE 0x3000 194 // #ifdef MS_CONFIG_OTA_SUPPORT 195 // #define OTA_PARA_MAX_SIZE 0x1000 196 // #define OTA_HEAD_PARA_MAX_SIZE 0x1000 197 // #define OTA_MCU_MAX_SIZE 0x30000 198 // #endif 199 200 // #define BOOTLOADER_FLASH_START_ADDR 0x10000000 201 // #define INFO_FLASH_START_ADDR 0x10010000 202 // #define KV_FLASH_START_ADDR 0x10366000 203 // #define NVDS_FLASH_START_ADDR 0x1037E000 204 // #define MIDEA_INFO_START_ADDR 0x101FE000 205 // #define MIDEA_INFO_BKUP_START_ADDR 0x101FF000 206 // #define APP_FLASH_START_ADDR 0x10012000 207 // #define OTA_FLASH_START_ADDR 0x10200000 208 // #define CUST1_FLASH_START_ADDR (OTA_FLASH_START_ADDR+OTA_MAX_SIZE) 209 // #ifdef MS_CONFIG_OTA_SUPPORT 210 // #define OTA_PARA_START_ADDR 0x101C9000 211 // #define OTA_HEAD_PARA_START_ADDR 0x101CA000 212 // #define OTA_MCU_FLASH_START_ADDR 0x101CB000 213 // #endif 214 // #endif 215 216 #if 1 217 #define BOOTLOADER_MAX_SIZE 0x10000 218 #define INFO_MAX_SIZE 0x2000 219 #define KV_MAX_SIZE 0x18000 220 #define NVDS_MAX_SIZE 0x2000 221 #define MIDEA_INFO_MAX_SIZE 0x1000 222 #define MIDEA_INFO_BKUP_MAX_SIZE 0x1000 223 #define APP_MAX_SIZE 0x166000 224 #define OTA_MAX_SIZE 0x166000 225 #define CUST1_MAX_SIZE 0x3000 226 #ifdef MS_CONFIG_OTA_SUPPORT 227 #define OTA_PARA_MAX_SIZE 0x1000 228 #define OTA_HEAD_PARA_MAX_SIZE 0x1000 229 #define OTA_MCU_MAX_SIZE 0x30000 230 #endif 231 232 #define BOOTLOADER_FLASH_START_ADDR 0x10000000 233 #define INFO_FLASH_START_ADDR (BOOTLOADER_FLASH_START_ADDR+BOOTLOADER_MAX_SIZE) // 0x10010000 234 #define APP_FLASH_START_ADDR (INFO_FLASH_START_ADDR+INFO_MAX_SIZE) // 0x10012000 END 10178000 235 #define APAPP_FLASH_END_ADDR (APP_FLASH_START_ADDR+APP_MAX_SIZE) 236 #define CUST1_FLASH_START_ADDR (APAPP_FLASH_END_ADDR+0x4000) 237 238 #define MIDEA_INFO_START_ADDR 0x101FE000 239 #define MIDEA_INFO_BKUP_START_ADDR 0x101FF000 240 #define NVDS_FLASH_START_ADDR 0x1037E000 241 242 #define OTA_FLASH_START_ADDR 0x10200000 // can't change 243 244 #define KV_FLASH_START_ADDR (OTA_FLASH_START_ADDR+OTA_MAX_SIZE) // 0x10366000 245 #ifdef MS_CONFIG_OTA_SUPPORT 246 #define OTA_PARA_START_ADDR 0x101C9000 247 #define OTA_HEAD_PARA_START_ADDR 0x101CA000 248 #define OTA_MCU_FLASH_START_ADDR 0x101CB000 249 #endif 250 #endif 251 252 #if 0 253 254 #define BOOTLOADER_FLASH_START_ADDR 0x10000000 255 #define INFO_FLASH_START_ADDR 0x10010000 256 #define KV_FLASH_START_ADDR 0x101F9000 257 #define MIDEA_INFO_START_ADDR 0x101FC000 258 #define MIDEA_INFO_BKUP_START_ADDR 0x101FD000 259 #define APP_FLASH_START_ADDR 0x10012000 260 #define OTA_FLASH_START_ADDR 0x10100000 261 #ifdef MS_CONFIG_OTA_SUPPORT 262 #define OTA_PARA_START_ADDR 0x101FE000 263 #define OTA_HEAD_PARA_START_ADDR 0x101FF000 264 #define OTA_MCU_FLASH_START_ADDR 0x101EE000 265 #endif 266 267 #define BOOTLOADER_MAX_SIZE 0x10000 268 #define INFO_MAX_SIZE 0x2000 269 #define KV_MAX_SIZE 0x3000 270 #define MIDEA_INFO_MAX_SIZE 0x1000 271 #define MIDEA_INFO_BKUP_MAX_SIZE 0x1000 272 #define APP_MAX_SIZE 0xEE000 273 #define OTA_MAX_SIZE 0xEE000 274 #ifdef MS_CONFIG_OTA_SUPPORT 275 #define OTA_PARA_MAX_SIZE 0x1000 276 #define OTA_HEAD_PARA_MAX_SIZE 0x1000 277 #define OTA_MCU_MAX_SIZE 0xB000 278 #endif 279 280 #endif 281 282 #if 0 283 284 #define BOOTLOADER_FLASH_START_ADDR 0x10000000 285 #define INFO_FLASH_START_ADDR 0x10010000 286 #define KV_FLASH_START_ADDR 0x1000B000 287 #define MIDEA_INFO_START_ADDR 0x1000E000 288 #define MIDEA_INFO_BKUP_START_ADDR 0x1000F000 289 #define APP_FLASH_START_ADDR 0x10012000 290 #define OTA_FLASH_START_ADDR 0x10100000 291 #ifdef MS_CONFIG_OTA_SUPPORT 292 #define OTA_PARA_START_ADDR 0x10010000 293 #define OTA_HEAD_PARA_START_ADDR 0x10011000 294 #define OTA_MCU_FLASH_START_ADDR 0x101EE000 295 #endif 296 297 #define BOOTLOADER_MAX_SIZE 0xB000 298 #define INFO_MAX_SIZE 0x2000 299 #define KV_MAX_SIZE 0x3000 300 #define MIDEA_INFO_MAX_SIZE 0x1000 301 #define MIDEA_INFO_BKUP_MAX_SIZE 0x1000 302 #define APP_MAX_SIZE 0xEE000 303 #define OTA_MAX_SIZE 0xEE000 304 #ifdef MS_CONFIG_OTA_SUPPORT 305 #define OTA_PARA_MAX_SIZE 0x1000 306 #define OTA_HEAD_PARA_MAX_SIZE 0x1000 307 #define OTA_MCU_MAX_SIZE 0x12000 308 #endif 309 310 #endif 311 312 #define duet_intrpt_enter() 313 #define duet_intrpt_exit() 314 315 #ifdef __cplusplus 316 } 317 #endif /* __cplusplus */ 318 319 #ifdef DUET_CM4 320 #include "core_cm4.h" 321 #include "cachel1_armv7.h" 322 #endif 323 324 #endif // __DUET_CM4_H__ 325 326