1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #ifndef EEPROM_H 18 #define EEPROM_H 19 20 #define AR_EEPROM_MODAL_SPURS 5 21 22 #include "../ath.h" 23 #include <net/cfg80211.h> 24 #include "ar9003_eeprom.h" 25 26 /* helpers to swap EEPROM fields, which are stored as __le16 or __le32. Since 27 * we are 100% sure about it we __force these to u16/u32 for the swab calls to 28 * silence the sparse checks. These macros are used when we have a Big Endian 29 * EEPROM (according to AR5416_EEPMISC_BIG_ENDIAN) and need to convert the 30 * fields to __le16/__le32. 31 */ 32 #define EEPROM_FIELD_SWAB16(field) \ 33 (field = (__force __le16)swab16((__force u16)field)) 34 #define EEPROM_FIELD_SWAB32(field) \ 35 (field = (__force __le32)swab32((__force u32)field)) 36 37 #ifdef __BIG_ENDIAN 38 #define AR5416_EEPROM_MAGIC 0x5aa5 39 #else 40 #define AR5416_EEPROM_MAGIC 0xa55a 41 #endif 42 43 #define CTRY_DEBUG 0x1ff 44 #define CTRY_DEFAULT 0 45 46 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 47 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002 48 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 49 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 50 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 51 #define AR_EEPROM_EEPCAP_MAXQCU_S 4 52 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 53 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 54 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 55 56 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 57 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 58 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 59 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 60 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 61 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 62 63 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 64 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 65 66 #define AR5416_EEPROM_MAGIC_OFFSET 0x0 67 #define AR5416_EEPROM_S 2 68 #define AR5416_EEPROM_OFFSET 0x2000 69 #define AR5416_EEPROM_MAX 0xae0 70 71 #define AR5416_EEPROM_START_ADDR \ 72 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 73 74 #define SD_NO_CTL 0xE0 75 #define NO_CTL 0xff 76 #define CTL_MODE_M 0xf 77 #define CTL_11A 0 78 #define CTL_11B 1 79 #define CTL_11G 2 80 #define CTL_2GHT20 5 81 #define CTL_5GHT20 6 82 #define CTL_2GHT40 7 83 #define CTL_5GHT40 8 84 85 #define EXT_ADDITIVE (0x8000) 86 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 87 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 88 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 89 90 #define SUB_NUM_CTL_MODES_AT_5G_40 2 91 #define SUB_NUM_CTL_MODES_AT_2G_40 3 92 93 #define POWER_CORRECTION_FOR_TWO_CHAIN 6 /* 10*log10(2)*2 */ 94 #define POWER_CORRECTION_FOR_THREE_CHAIN 10 /* 10*log10(3)*2 */ 95 96 /* 97 * For AR9285 and later chipsets, the following bits are not being programmed 98 * in EEPROM and so need to be enabled always. 99 * 100 * Bit 0: en_fcc_mid 101 * Bit 1: en_jap_mid 102 * Bit 2: en_fcc_dfs_ht40 103 * Bit 3: en_jap_ht40 104 * Bit 4: en_jap_dfs_ht40 105 */ 106 #define AR9285_RDEXT_DEFAULT 0x1F 107 108 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 109 #define FREQ2FBIN(x, y) (u8)((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 110 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x)) 111 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) 112 113 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ 114 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 115 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_11_OR_LATER(ah) && \ 116 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 117 118 #define EEP_RFSILENT_ENABLED 0x0001 119 #define EEP_RFSILENT_ENABLED_S 0 120 #define EEP_RFSILENT_POLARITY 0x0002 121 #define EEP_RFSILENT_POLARITY_S 1 122 #define EEP_RFSILENT_GPIO_SEL ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00fc : 0x001c) 123 #define EEP_RFSILENT_GPIO_SEL_S 2 124 125 #define AR5416_OPFLAGS_11A 0x01 126 #define AR5416_OPFLAGS_11G 0x02 127 #define AR5416_OPFLAGS_N_5G_HT40 0x04 128 #define AR5416_OPFLAGS_N_2G_HT40 0x08 129 #define AR5416_OPFLAGS_N_5G_HT20 0x10 130 #define AR5416_OPFLAGS_N_2G_HT20 0x20 131 132 #define AR5416_EEP_NO_BACK_VER 0x1 133 #define AR5416_EEP_VER 0xE 134 #define AR5416_EEP_VER_MAJOR_SHIFT 12 135 #define AR5416_EEP_VER_MAJOR_MASK 0xF000 136 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF 137 #define AR5416_EEP_MINOR_VER_2 0x2 138 #define AR5416_EEP_MINOR_VER_3 0x3 139 #define AR5416_EEP_MINOR_VER_7 0x7 140 #define AR5416_EEP_MINOR_VER_9 0x9 141 #define AR5416_EEP_MINOR_VER_16 0x10 142 #define AR5416_EEP_MINOR_VER_17 0x11 143 #define AR5416_EEP_MINOR_VER_19 0x13 144 #define AR5416_EEP_MINOR_VER_20 0x14 145 #define AR5416_EEP_MINOR_VER_21 0x15 146 #define AR5416_EEP_MINOR_VER_22 0x16 147 148 #define AR5416_NUM_5G_CAL_PIERS 8 149 #define AR5416_NUM_2G_CAL_PIERS 4 150 #define AR5416_NUM_5G_20_TARGET_POWERS 8 151 #define AR5416_NUM_5G_40_TARGET_POWERS 8 152 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3 153 #define AR5416_NUM_2G_20_TARGET_POWERS 4 154 #define AR5416_NUM_2G_40_TARGET_POWERS 4 155 #define AR5416_NUM_CTLS 24 156 #define AR5416_NUM_BAND_EDGES 8 157 #define AR5416_NUM_PD_GAINS 4 158 #define AR5416_PD_GAINS_IN_MASK 4 159 #define AR5416_PD_GAIN_ICEPTS 5 160 #define AR5416_NUM_PDADC_VALUES 128 161 #define AR5416_BCHAN_UNUSED 0xFF 162 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 163 #define AR5416_MAX_CHAINS 3 164 #define AR9300_MAX_CHAINS 3 165 #define AR5416_PWR_TABLE_OFFSET_DB -5 166 167 /* Rx gain type values */ 168 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 169 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 170 #define AR5416_EEP_RXGAIN_ORIG 2 171 172 /* Tx gain type values */ 173 #define AR5416_EEP_TXGAIN_ORIGINAL 0 174 #define AR5416_EEP_TXGAIN_HIGH_POWER 1 175 176 /* Endianness of EEPROM content */ 177 #define AR5416_EEPMISC_BIG_ENDIAN 0x01 178 179 #define AR5416_EEP4K_START_LOC 64 180 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 181 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 182 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 183 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 184 #define AR5416_EEP4K_NUM_CTLS 12 185 #define AR5416_EEP4K_NUM_BAND_EDGES 4 186 #define AR5416_EEP4K_NUM_PD_GAINS 2 187 #define AR5416_EEP4K_MAX_CHAINS 1 188 189 #define AR9280_TX_GAIN_TABLE_SIZE 22 190 191 #define AR9287_EEP_VER 0xE 192 #define AR9287_EEP_MINOR_VER_1 0x1 193 #define AR9287_EEP_MINOR_VER_2 0x2 194 #define AR9287_EEP_MINOR_VER_3 0x3 195 #define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3 196 #define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER 197 #define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1 198 199 #define AR9287_EEP_START_LOC 128 200 #define AR9287_HTC_EEP_START_LOC 256 201 #define AR9287_NUM_2G_CAL_PIERS 3 202 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3 203 #define AR9287_NUM_2G_20_TARGET_POWERS 3 204 #define AR9287_NUM_2G_40_TARGET_POWERS 3 205 #define AR9287_NUM_CTLS 12 206 #define AR9287_NUM_BAND_EDGES 4 207 #define AR9287_PD_GAIN_ICEPTS 1 208 #define AR9287_EEPMISC_WOW 0x02 209 #define AR9287_MAX_CHAINS 2 210 #define AR9287_ANT_16S 32 211 212 #define AR9287_DATA_SZ 32 213 214 #define AR9287_PWR_TABLE_OFFSET_DB -5 215 216 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1) 217 218 #define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f) 219 #define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03) 220 221 #define LNA_CTL_BUF_MODE BIT(0) 222 #define LNA_CTL_ISEL_LO BIT(1) 223 #define LNA_CTL_ISEL_HI BIT(2) 224 #define LNA_CTL_BUF_IN BIT(3) 225 #define LNA_CTL_FEM_BAND BIT(4) 226 #define LNA_CTL_LOCAL_BIAS BIT(5) 227 #define LNA_CTL_FORCE_XPA BIT(6) 228 #define LNA_CTL_USE_ANT1 BIT(7) 229 230 enum eeprom_param { 231 EEP_NFTHRESH_5, 232 EEP_NFTHRESH_2, 233 EEP_MAC_MSW, 234 EEP_MAC_MID, 235 EEP_MAC_LSW, 236 EEP_REG_0, 237 EEP_OP_CAP, 238 EEP_OP_MODE, 239 EEP_RF_SILENT, 240 EEP_OB_5, 241 EEP_DB_5, 242 EEP_OB_2, 243 EEP_DB_2, 244 EEP_TX_MASK, 245 EEP_RX_MASK, 246 EEP_FSTCLK_5G, 247 EEP_RXGAIN_TYPE, 248 EEP_OL_PWRCTRL, 249 EEP_TXGAIN_TYPE, 250 EEP_RC_CHAIN_MASK, 251 EEP_DAC_HPWR_5G, 252 EEP_FRAC_N_5G, 253 EEP_DEV_TYPE, 254 EEP_TEMPSENSE_SLOPE, 255 EEP_TEMPSENSE_SLOPE_PAL_ON, 256 EEP_PWR_TABLE_OFFSET, 257 EEP_PAPRD, 258 EEP_MODAL_VER, 259 EEP_ANT_DIV_CTL1, 260 EEP_CHAIN_MASK_REDUCE, 261 EEP_ANTENNA_GAIN_2G, 262 EEP_ANTENNA_GAIN_5G, 263 }; 264 265 enum ar5416_rates { 266 rate6mb, rate9mb, rate12mb, rate18mb, 267 rate24mb, rate36mb, rate48mb, rate54mb, 268 rate1l, rate2l, rate2s, rate5_5l, 269 rate5_5s, rate11l, rate11s, rateXr, 270 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 271 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 272 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 273 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 274 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 275 Ar5416RateSize 276 }; 277 278 enum ath9k_hal_freq_band { 279 ATH9K_HAL_FREQ_BAND_5GHZ = 0, 280 ATH9K_HAL_FREQ_BAND_2GHZ = 1 281 }; 282 283 struct base_eep_header { 284 __le16 length; 285 __le16 checksum; 286 __le16 version; 287 u8 opCapFlags; 288 u8 eepMisc; 289 __le16 regDmn[2]; 290 u8 macAddr[6]; 291 u8 rxMask; 292 u8 txMask; 293 __le16 rfSilent; 294 __le16 blueToothOptions; 295 __le16 deviceCap; 296 __le32 binBuildNumber; 297 u8 deviceType; 298 u8 pwdclkind; 299 u8 fastClk5g; 300 u8 divChain; 301 u8 rxGainType; 302 u8 dacHiPwrMode_5G; 303 u8 openLoopPwrCntl; 304 u8 dacLpMode; 305 u8 txGainType; 306 u8 rcChainMask; 307 u8 desiredScaleCCK; 308 u8 pwr_table_offset; 309 u8 frac_n_5g; 310 u8 futureBase_3[21]; 311 } __packed; 312 313 struct base_eep_header_4k { 314 __le16 length; 315 __le16 checksum; 316 __le16 version; 317 u8 opCapFlags; 318 u8 eepMisc; 319 __le16 regDmn[2]; 320 u8 macAddr[6]; 321 u8 rxMask; 322 u8 txMask; 323 __le16 rfSilent; 324 __le16 blueToothOptions; 325 __le16 deviceCap; 326 __le32 binBuildNumber; 327 u8 deviceType; 328 u8 txGainType; 329 } __packed; 330 331 332 struct spur_chan { 333 __le16 spurChan; 334 u8 spurRangeLow; 335 u8 spurRangeHigh; 336 } __packed; 337 338 struct modal_eep_header { 339 __le32 antCtrlChain[AR5416_MAX_CHAINS]; 340 __le32 antCtrlCommon; 341 u8 antennaGainCh[AR5416_MAX_CHAINS]; 342 u8 switchSettling; 343 u8 txRxAttenCh[AR5416_MAX_CHAINS]; 344 u8 rxTxMarginCh[AR5416_MAX_CHAINS]; 345 u8 adcDesiredSize; 346 u8 pgaDesiredSize; 347 u8 xlnaGainCh[AR5416_MAX_CHAINS]; 348 u8 txEndToXpaOff; 349 u8 txEndToRxOn; 350 u8 txFrameToXpaOn; 351 u8 thresh62; 352 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; 353 u8 xpdGain; 354 u8 xpd; 355 u8 iqCalICh[AR5416_MAX_CHAINS]; 356 u8 iqCalQCh[AR5416_MAX_CHAINS]; 357 u8 pdGainOverlap; 358 u8 ob; 359 u8 db; 360 u8 xpaBiasLvl; 361 u8 pwrDecreaseFor2Chain; 362 u8 pwrDecreaseFor3Chain; 363 u8 txFrameToDataStart; 364 u8 txFrameToPaOn; 365 u8 ht40PowerIncForPdadc; 366 u8 bswAtten[AR5416_MAX_CHAINS]; 367 u8 bswMargin[AR5416_MAX_CHAINS]; 368 u8 swSettleHt40; 369 u8 xatten2Db[AR5416_MAX_CHAINS]; 370 u8 xatten2Margin[AR5416_MAX_CHAINS]; 371 u8 ob_ch1; 372 u8 db_ch1; 373 u8 lna_ctl; 374 u8 miscBits; 375 __le16 xpaBiasLvlFreq[3]; 376 u8 futureModal[6]; 377 378 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 379 } __packed; 380 381 struct calDataPerFreqOpLoop { 382 u8 pwrPdg[2][5]; 383 u8 vpdPdg[2][5]; 384 u8 pcdac[2][5]; 385 u8 empty[2][5]; 386 } __packed; 387 388 struct modal_eep_4k_header { 389 __le32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; 390 __le32 antCtrlCommon; 391 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; 392 u8 switchSettling; 393 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; 394 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; 395 u8 adcDesiredSize; 396 u8 pgaDesiredSize; 397 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; 398 u8 txEndToXpaOff; 399 u8 txEndToRxOn; 400 u8 txFrameToXpaOn; 401 u8 thresh62; 402 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; 403 u8 xpdGain; 404 u8 xpd; 405 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; 406 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; 407 u8 pdGainOverlap; 408 #ifdef __BIG_ENDIAN_BITFIELD 409 u8 ob_1:4, ob_0:4; 410 u8 db1_1:4, db1_0:4; 411 #else 412 u8 ob_0:4, ob_1:4; 413 u8 db1_0:4, db1_1:4; 414 #endif 415 u8 xpaBiasLvl; 416 u8 txFrameToDataStart; 417 u8 txFrameToPaOn; 418 u8 ht40PowerIncForPdadc; 419 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; 420 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; 421 u8 swSettleHt40; 422 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; 423 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; 424 #ifdef __BIG_ENDIAN_BITFIELD 425 u8 db2_1:4, db2_0:4; 426 #else 427 u8 db2_0:4, db2_1:4; 428 #endif 429 u8 version; 430 #ifdef __BIG_ENDIAN_BITFIELD 431 u8 ob_3:4, ob_2:4; 432 u8 antdiv_ctl1:4, ob_4:4; 433 u8 db1_3:4, db1_2:4; 434 u8 antdiv_ctl2:4, db1_4:4; 435 u8 db2_2:4, db2_3:4; 436 u8 reserved:4, db2_4:4; 437 #else 438 u8 ob_2:4, ob_3:4; 439 u8 ob_4:4, antdiv_ctl1:4; 440 u8 db1_2:4, db1_3:4; 441 u8 db1_4:4, antdiv_ctl2:4; 442 u8 db2_2:4, db2_3:4; 443 u8 db2_4:4, reserved:4; 444 #endif 445 u8 tx_diversity; 446 u8 flc_pwr_thresh; 447 u8 bb_scale_smrt_antenna; 448 #define EEP_4K_BB_DESIRED_SCALE_MASK 0x1f 449 u8 futureModal[1]; 450 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 451 } __packed; 452 453 struct base_eep_ar9287_header { 454 __le16 length; 455 __le16 checksum; 456 __le16 version; 457 u8 opCapFlags; 458 u8 eepMisc; 459 __le16 regDmn[2]; 460 u8 macAddr[6]; 461 u8 rxMask; 462 u8 txMask; 463 __le16 rfSilent; 464 __le16 blueToothOptions; 465 __le16 deviceCap; 466 __le32 binBuildNumber; 467 u8 deviceType; 468 u8 openLoopPwrCntl; 469 int8_t pwrTableOffset; 470 int8_t tempSensSlope; 471 int8_t tempSensSlopePalOn; 472 u8 futureBase[29]; 473 } __packed; 474 475 struct modal_eep_ar9287_header { 476 __le32 antCtrlChain[AR9287_MAX_CHAINS]; 477 __le32 antCtrlCommon; 478 int8_t antennaGainCh[AR9287_MAX_CHAINS]; 479 u8 switchSettling; 480 u8 txRxAttenCh[AR9287_MAX_CHAINS]; 481 u8 rxTxMarginCh[AR9287_MAX_CHAINS]; 482 int8_t adcDesiredSize; 483 u8 txEndToXpaOff; 484 u8 txEndToRxOn; 485 u8 txFrameToXpaOn; 486 u8 thresh62; 487 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; 488 u8 xpdGain; 489 u8 xpd; 490 int8_t iqCalICh[AR9287_MAX_CHAINS]; 491 int8_t iqCalQCh[AR9287_MAX_CHAINS]; 492 u8 pdGainOverlap; 493 u8 xpaBiasLvl; 494 u8 txFrameToDataStart; 495 u8 txFrameToPaOn; 496 u8 ht40PowerIncForPdadc; 497 u8 bswAtten[AR9287_MAX_CHAINS]; 498 u8 bswMargin[AR9287_MAX_CHAINS]; 499 u8 swSettleHt40; 500 u8 version; 501 u8 db1; 502 u8 db2; 503 u8 ob_cck; 504 u8 ob_psk; 505 u8 ob_qam; 506 u8 ob_pal_off; 507 u8 futureModal[30]; 508 struct spur_chan spurChans[AR_EEPROM_MODAL_SPURS]; 509 } __packed; 510 511 struct cal_data_per_freq { 512 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 513 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 514 } __packed; 515 516 struct cal_data_per_freq_4k { 517 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 518 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 519 } __packed; 520 521 struct cal_target_power_leg { 522 u8 bChannel; 523 u8 tPow2x[4]; 524 } __packed; 525 526 struct cal_target_power_ht { 527 u8 bChannel; 528 u8 tPow2x[8]; 529 } __packed; 530 531 struct cal_ctl_edges { 532 u8 bChannel; 533 u8 ctl; 534 } __packed; 535 536 struct cal_data_op_loop_ar9287 { 537 u8 pwrPdg[2][5]; 538 u8 vpdPdg[2][5]; 539 u8 pcdac[2][5]; 540 u8 empty[2][5]; 541 } __packed; 542 543 struct cal_data_per_freq_ar9287 { 544 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 545 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 546 } __packed; 547 548 union cal_data_per_freq_ar9287_u { 549 struct cal_data_op_loop_ar9287 calDataOpen; 550 struct cal_data_per_freq_ar9287 calDataClose; 551 } __packed; 552 553 struct cal_ctl_data_ar9287 { 554 struct cal_ctl_edges 555 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES]; 556 } __packed; 557 558 struct cal_ctl_data { 559 struct cal_ctl_edges 560 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 561 } __packed; 562 563 struct cal_ctl_data_4k { 564 struct cal_ctl_edges 565 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]; 566 } __packed; 567 568 struct ar5416_eeprom_def { 569 struct base_eep_header baseEepHeader; 570 u8 custData[64]; 571 struct modal_eep_header modalHeader[2]; 572 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 573 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 574 struct cal_data_per_freq 575 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; 576 struct cal_data_per_freq 577 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; 578 struct cal_target_power_leg 579 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; 580 struct cal_target_power_ht 581 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 582 struct cal_target_power_ht 583 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 584 struct cal_target_power_leg 585 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 586 struct cal_target_power_leg 587 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; 588 struct cal_target_power_ht 589 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 590 struct cal_target_power_ht 591 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 592 u8 ctlIndex[AR5416_NUM_CTLS]; 593 struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; 594 u8 padding; 595 } __packed; 596 597 struct ar5416_eeprom_4k { 598 struct base_eep_header_4k baseEepHeader; 599 u8 custData[20]; 600 struct modal_eep_4k_header modalHeader; 601 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]; 602 struct cal_data_per_freq_4k 603 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]; 604 struct cal_target_power_leg 605 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]; 606 struct cal_target_power_leg 607 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 608 struct cal_target_power_ht 609 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 610 struct cal_target_power_ht 611 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]; 612 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]; 613 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]; 614 u8 padding; 615 } __packed; 616 617 struct ar9287_eeprom { 618 struct base_eep_ar9287_header baseEepHeader; 619 u8 custData[AR9287_DATA_SZ]; 620 struct modal_eep_ar9287_header modalHeader; 621 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; 622 union cal_data_per_freq_ar9287_u 623 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; 624 struct cal_target_power_leg 625 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; 626 struct cal_target_power_leg 627 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; 628 struct cal_target_power_ht 629 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; 630 struct cal_target_power_ht 631 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; 632 u8 ctlIndex[AR9287_NUM_CTLS]; 633 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; 634 u8 padding; 635 } __packed; 636 637 enum reg_ext_bitmap { 638 REG_EXT_FCC_MIDBAND = 0, 639 REG_EXT_JAPAN_MIDBAND = 1, 640 REG_EXT_FCC_DFS_HT40 = 2, 641 REG_EXT_JAPAN_NONDFS_HT40 = 3, 642 REG_EXT_JAPAN_DFS_HT40 = 4 643 }; 644 645 struct ath9k_country_entry { 646 u16 countryCode; 647 u16 regDmnEnum; 648 u16 regDmn5G; 649 u16 regDmn2G; 650 u8 isMultidomain; 651 u8 iso[3]; 652 }; 653 654 struct eeprom_ops { 655 int (*check_eeprom)(struct ath_hw *hw); 656 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param); 657 bool (*fill_eeprom)(struct ath_hw *hw); 658 u32 (*dump_eeprom)(struct ath_hw *hw, bool dump_base_hdr, u8 *buf, 659 u32 len, u32 size); 660 int (*get_eeprom_ver)(struct ath_hw *hw); 661 int (*get_eeprom_rev)(struct ath_hw *hw); 662 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); 663 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); 664 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, 665 u16 cfgCtl, u8 twiceAntennaReduction, 666 u8 powerLimit, bool test); 667 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); 668 u8 (*get_eepmisc)(struct ath_hw *ah); 669 }; 670 671 void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val); 672 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, 673 u32 shift, u32 val); 674 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, 675 int16_t targetLeft, 676 int16_t targetRight); 677 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, 678 u16 *indexL, u16 *indexR); 679 bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data); 680 int ath9k_hw_nvram_swap_data(struct ath_hw *ah, bool *swap_needed, int size); 681 bool ath9k_hw_nvram_validate_checksum(struct ath_hw *ah, int size); 682 bool ath9k_hw_nvram_check_version(struct ath_hw *ah, int version, int minrev); 683 void ath9k_hw_usb_gen_fill_eeprom(struct ath_hw *ah, u16 *eep_data, 684 int eep_start_loc, int size); 685 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 686 u8 *pVpdList, u16 numIntercepts, 687 u8 *pRetVpdList); 688 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, 689 struct ath9k_channel *chan, 690 struct cal_target_power_leg *powInfo, 691 u16 numChannels, 692 struct cal_target_power_leg *pNewPower, 693 u16 numRates, bool isExtTarget); 694 void ath9k_hw_get_target_powers(struct ath_hw *ah, 695 struct ath9k_channel *chan, 696 struct cal_target_power_ht *powInfo, 697 u16 numChannels, 698 struct cal_target_power_ht *pNewPower, 699 u16 numRates, bool isHt40Target); 700 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, 701 bool is2GHz, int num_band_edges); 702 u16 ath9k_hw_get_scaled_power(struct ath_hw *ah, u16 power_limit, 703 u8 antenna_reduction); 704 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah); 705 int ath9k_hw_eeprom_init(struct ath_hw *ah); 706 707 void ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hw *ah, 708 struct ath9k_channel *chan, 709 void *pRawDataSet, 710 u8 *bChans, u16 availPiers, 711 u16 tPdGainOverlap, 712 u16 *pPdGainBoundaries, u8 *pPDADCValues, 713 u16 numXpdGains); 714 ath9k_hw_fbin2freq(u8 fbin,bool is2GHz)715 static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) 716 { 717 if (fbin == AR5416_BCHAN_UNUSED) 718 return fbin; 719 720 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); 721 } 722 723 #define ar5416_get_ntxchains(_txchainmask) \ 724 (((_txchainmask >> 2) & 1) + \ 725 ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 726 727 extern const struct eeprom_ops eep_def_ops; 728 extern const struct eeprom_ops eep_4k_ops; 729 extern const struct eeprom_ops eep_ar9287_ops; 730 extern const struct eeprom_ops eep_ar9287_ops; 731 extern const struct eeprom_ops eep_ar9300_ops; 732 733 #endif /* EEPROM_H */ 734