1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef _SOC_EFUSE_REG_H_ 15 #define _SOC_EFUSE_REG_H_ 16 17 18 #include "soc.h" 19 #define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000) 20 /* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[26:20] ;default: 7'b0 ; */ 21 /*description: read for flash_crypt_cnt*/ 22 #define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007F 23 #define EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V)<<(EFUSE_RD_FLASH_CRYPT_CNT_S)) 24 #define EFUSE_RD_FLASH_CRYPT_CNT_V 0x7F 25 #define EFUSE_RD_FLASH_CRYPT_CNT_S 20 26 /* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; */ 27 /*description: read for efuse_rd_disable*/ 28 #define EFUSE_RD_EFUSE_RD_DIS 0x0000000F 29 #define EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V)<<(EFUSE_RD_EFUSE_RD_DIS_S)) 30 #define EFUSE_RD_EFUSE_RD_DIS_V 0xF 31 #define EFUSE_RD_EFUSE_RD_DIS_S 16 32 33 /* Read disable bits for efuse blocks 1-3 */ 34 #define EFUSE_RD_DIS_BLK1 (1<<16) 35 #define EFUSE_RD_DIS_BLK2 (1<<17) 36 #define EFUSE_RD_DIS_BLK3 (1<<18) 37 /* Read disable FLASH_CRYPT_CONFIG, CODING_SCHEME & KEY_STATUS 38 in efuse block 0 39 */ 40 #define EFUSE_RD_DIS_BLK0_PARTIAL (1<<19) 41 42 /* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; */ 43 /*description: read for efuse_wr_disable*/ 44 #define EFUSE_RD_EFUSE_WR_DIS 0x0000FFFF 45 #define EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V)<<(EFUSE_RD_EFUSE_WR_DIS_S)) 46 #define EFUSE_RD_EFUSE_WR_DIS_V 0xFFFF 47 #define EFUSE_RD_EFUSE_WR_DIS_S 0 48 49 /* Write disable bits */ 50 #define EFUSE_WR_DIS_RD_DIS (1<<0) /*< disable writing read disable reg */ 51 #define EFUSE_WR_DIS_WR_DIS (1<<1) /*< disable writing write disable reg */ 52 #define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1<<2) 53 #define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1<<3) /*< disable writing MAC & SPI config hd efuses */ 54 #define EFUSE_WR_DIS_XPD_SDIO (1<<5) /*< disable writing SDIO config efuses */ 55 #define EFUSE_WR_DIS_SPI_PAD_CONFIG (1<<6) /*< disable writing SPI_PAD_CONFIG efuses */ 56 #define EFUSE_WR_DIS_BLK1 (1<<7) /*< disable writing BLK1 efuses */ 57 #define EFUSE_WR_DIS_BLK2 (1<<8) /*< disable writing BLK2 efuses */ 58 #define EFUSE_WR_DIS_BLK3 (1<<9) /*< disable writing BLK3 efuses */ 59 #define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1<<10) /*< disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ 60 #define EFUSE_WR_DIS_ABS_DONE_0 (1<<12) /*< disable writing ABS_DONE_0 efuse */ 61 #define EFUSE_WR_DIS_ABS_DONE_1 (1<<13) /*< disable writing ABS_DONE_1 efuse */ 62 #define EFUSE_WR_DIS_JTAG_DISABLE (1<<14) /*< disable writing JTAG_DISABLE efuse */ 63 #define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1<<15) /*< disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ 64 65 #define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004) 66 /* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; */ 67 /*description: read for low 32bit WIFI_MAC_Address*/ 68 #define EFUSE_RD_WIFI_MAC_CRC_LOW 0xFFFFFFFF 69 #define EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V)<<(EFUSE_RD_WIFI_MAC_CRC_LOW_S)) 70 #define EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF 71 #define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0 72 73 #define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008) 74 /* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; */ 75 /*description: read for high 24bit WIFI_MAC_Address*/ 76 #define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00FFFFFF 77 #define EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_RD_WIFI_MAC_CRC_HIGH_S)) 78 #define EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xFFFFFF 79 #define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0 80 81 #define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) 82 /* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ 83 /*description: bit is set to 1 for rev1 silicon*/ 84 #define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) 85 #define EFUSE_RD_CHIP_VER_REV1_M ((EFUSE_RD_CHIP_VER_REV1_V)<<(EFUSE_RD_CHIP_VER_REV1_S)) 86 #define EFUSE_RD_CHIP_VER_REV1_V 0x1 87 #define EFUSE_RD_CHIP_VER_REV1_S 15 88 /* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ 89 /*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/ 90 #define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) 91 #define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V)<<(EFUSE_RD_BLK3_PART_RESERVE_S)) 92 #define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 93 #define EFUSE_RD_BLK3_PART_RESERVE_S 14 94 /* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */ 95 /*description: If set, the ESP32's maximum CPU frequency has been rated*/ 96 #define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) 97 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_M ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_RD_CHIP_CPU_FREQ_RATED_S)) 98 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x1 99 #define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 100 /* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */ 101 /*description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/ 102 #define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) 103 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_M ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_RD_CHIP_CPU_FREQ_LOW_S)) 104 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1 105 #define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 106 /* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ 107 /*description: least significant bits of chip package */ 108 #define EFUSE_RD_CHIP_VER_PKG 0x00000007 109 #define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V)<<(EFUSE_RD_CHIP_VER_PKG_S)) 110 #define EFUSE_RD_CHIP_VER_PKG_V 0x7 111 #define EFUSE_RD_CHIP_VER_PKG_S 9 112 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 113 #define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 114 #define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 115 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 /* Deprecated: this chip was never mass produced */ 116 #define EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH 4 117 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 118 #define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6 119 /* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; */ 120 /*description: read for SPI_pad_config_hd*/ 121 #define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001F 122 #define EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V)<<(EFUSE_RD_SPI_PAD_CONFIG_HD_S)) 123 #define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1F 124 #define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 125 /* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; */ 126 /*description: */ 127 #define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3)) 128 #define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3)) 129 #define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1 130 #define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3 131 /* EFUSE_RD_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */ 132 /*description: most significant bit of chip package */ 133 #define EFUSE_RD_CHIP_VER_PKG_4BIT (BIT(2)) 134 #define EFUSE_RD_CHIP_VER_PKG_4BIT_M (BIT(2)) 135 #define EFUSE_RD_CHIP_VER_PKG_4BIT_V 0x1 136 #define EFUSE_RD_CHIP_VER_PKG_4BIT_S 2 137 /* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; */ 138 /*description: */ 139 #define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1)) 140 #define EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1)) 141 #define EFUSE_RD_CHIP_VER_DIS_BT_V 0x1 142 #define EFUSE_RD_CHIP_VER_DIS_BT_S 1 143 /* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; */ 144 /*description: */ 145 #define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0)) 146 #define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0)) 147 #define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1 148 #define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0 149 150 #define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) 151 /* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */ 152 /*description: read for sdio_force*/ 153 #define EFUSE_RD_SDIO_FORCE (BIT(16)) 154 #define EFUSE_RD_SDIO_FORCE_M (BIT(16)) 155 #define EFUSE_RD_SDIO_FORCE_V 0x1 156 #define EFUSE_RD_SDIO_FORCE_S 16 157 /* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */ 158 /*description: read for SDIO_TIEH*/ 159 #define EFUSE_RD_SDIO_TIEH (BIT(15)) 160 #define EFUSE_RD_SDIO_TIEH_M (BIT(15)) 161 #define EFUSE_RD_SDIO_TIEH_V 0x1 162 #define EFUSE_RD_SDIO_TIEH_S 15 163 /* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */ 164 /*description: read for XPD_SDIO_REG*/ 165 #define EFUSE_RD_XPD_SDIO_REG (BIT(14)) 166 #define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) 167 #define EFUSE_RD_XPD_SDIO_REG_V 0x1 168 #define EFUSE_RD_XPD_SDIO_REG_S 14 169 /* EFUSE_RD_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */ 170 /*description: True ADC reference voltage */ 171 #define EFUSE_RD_ADC_VREF 0x0000001F 172 #define EFUSE_RD_ADC_VREF_M ((EFUSE_RD_ADC_VREF_V)<<(EFUSE_RD_ADC_VREF_S)) 173 #define EFUSE_RD_ADC_VREF_V 0x1F 174 #define EFUSE_RD_ADC_VREF_S 8 175 /* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer 176 * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore 177 * SDIO_DREFH/M/L is only available in older versions of ESP32 */ 178 /* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */ 179 /*description: */ 180 #define EFUSE_RD_SDIO_DREFL 0x00000003 181 #define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V)<<(EFUSE_RD_SDIO_DREFL_S)) 182 #define EFUSE_RD_SDIO_DREFL_V 0x3 183 #define EFUSE_RD_SDIO_DREFL_S 12 184 /* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */ 185 /*description: */ 186 #define EFUSE_RD_SDIO_DREFM 0x00000003 187 #define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V)<<(EFUSE_RD_SDIO_DREFM_S)) 188 #define EFUSE_RD_SDIO_DREFM_V 0x3 189 #define EFUSE_RD_SDIO_DREFM_S 10 190 /* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */ 191 /*description: */ 192 #define EFUSE_RD_SDIO_DREFH 0x00000003 193 #define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V)<<(EFUSE_RD_SDIO_DREFH_S)) 194 #define EFUSE_RD_SDIO_DREFH_V 0x3 195 #define EFUSE_RD_SDIO_DREFH_S 8 196 /* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; */ 197 /*description: */ 198 #define EFUSE_RD_CK8M_FREQ 0x000000FF 199 #define EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V)<<(EFUSE_RD_CK8M_FREQ_S)) 200 #define EFUSE_RD_CK8M_FREQ_V 0xFF 201 #define EFUSE_RD_CK8M_FREQ_S 0 202 203 #define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) 204 /* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; */ 205 /*description: read for flash_crypt_config*/ 206 #define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000F 207 #define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S)) 208 #define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF 209 #define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 210 /* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; */ 211 /*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (RO) 212 BIT[27] is the sign bit, 0: + , 1: - 213 BIT[26:24] is the difference value, unit: 0.017V 214 volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ 215 #define EFUSE_RD_DIG_VOL_L6 0x0F 216 #define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) 217 #define EFUSE_RD_DIG_VOL_L6_V 0x0F 218 #define EFUSE_RD_DIG_VOL_L6_S 24 219 /* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */ 220 /*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. 221 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/ 222 #define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 223 #define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) 224 #define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 225 #define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 226 /* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; */ 227 /* Deprecated */ 228 #define EFUSE_RD_INST_CONFIG 0x000000FF /** Deprecated **/ 229 #define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V)<<(EFUSE_RD_INST_CONFIG_S)) /** Deprecated **/ 230 #define EFUSE_RD_INST_CONFIG_V 0xFF /** Deprecated **/ 231 #define EFUSE_RD_INST_CONFIG_S 20 /** Deprecated **/ 232 /* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; */ 233 /*description: read for SPI_pad_config_cs0*/ 234 #define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001F 235 #define EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CS0_S)) 236 #define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1F 237 #define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 238 /* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; */ 239 /*description: read for SPI_pad_config_d*/ 240 #define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001F 241 #define EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V)<<(EFUSE_RD_SPI_PAD_CONFIG_D_S)) 242 #define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1F 243 #define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 244 /* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; */ 245 /*description: read for SPI_pad_config_q*/ 246 #define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001F 247 #define EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V)<<(EFUSE_RD_SPI_PAD_CONFIG_Q_S)) 248 #define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1F 249 #define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 250 /* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; */ 251 /*description: read for SPI_pad_config_clk*/ 252 #define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001F 253 #define EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_RD_SPI_PAD_CONFIG_CLK_S)) 254 #define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1F 255 #define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 256 257 #define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018) 258 /* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; */ 259 /*description: read for key_status*/ 260 #define EFUSE_RD_KEY_STATUS (BIT(10)) 261 #define EFUSE_RD_KEY_STATUS_M (BIT(10)) 262 #define EFUSE_RD_KEY_STATUS_V 0x1 263 #define EFUSE_RD_KEY_STATUS_S 10 264 /* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; */ 265 /*description: read for download_dis_cache*/ 266 #define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) 267 #define EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9)) 268 #define EFUSE_RD_DISABLE_DL_CACHE_V 0x1 269 #define EFUSE_RD_DISABLE_DL_CACHE_S 9 270 /* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; */ 271 /*description: read for download_dis_decrypt*/ 272 #define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) 273 #define EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8)) 274 #define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1 275 #define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 276 /* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; */ 277 /*description: read for download_dis_encrypt*/ 278 #define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) 279 #define EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7)) 280 #define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1 281 #define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 282 /* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; */ 283 /*description: read for JTAG_disable*/ 284 #define EFUSE_RD_DISABLE_JTAG (BIT(6)) 285 #define EFUSE_RD_DISABLE_JTAG_M (BIT(6)) 286 #define EFUSE_RD_DISABLE_JTAG_V 0x1 287 #define EFUSE_RD_DISABLE_JTAG_S 6 288 /* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; */ 289 /*description: read for abstract_done_1*/ 290 #define EFUSE_RD_ABS_DONE_1 (BIT(5)) 291 #define EFUSE_RD_ABS_DONE_1_M (BIT(5)) 292 #define EFUSE_RD_ABS_DONE_1_V 0x1 293 #define EFUSE_RD_ABS_DONE_1_S 5 294 /* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; */ 295 /*description: read for abstract_done_0*/ 296 #define EFUSE_RD_ABS_DONE_0 (BIT(4)) 297 #define EFUSE_RD_ABS_DONE_0_M (BIT(4)) 298 #define EFUSE_RD_ABS_DONE_0_V 0x1 299 #define EFUSE_RD_ABS_DONE_0_S 4 300 /* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; */ 301 /*description: */ 302 #define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) 303 #define EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3)) 304 #define EFUSE_RD_DISABLE_SDIO_HOST_V 0x1 305 #define EFUSE_RD_DISABLE_SDIO_HOST_S 3 306 /* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; */ 307 /*description: read for console_debug_disable*/ 308 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) 309 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2)) 310 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1 311 #define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 312 /* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; */ 313 /*description: read for coding_scheme*/ 314 #define EFUSE_RD_CODING_SCHEME 0x00000003 315 #define EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V)<<(EFUSE_RD_CODING_SCHEME_S)) 316 #define EFUSE_RD_CODING_SCHEME_V 0x3 317 #define EFUSE_RD_CODING_SCHEME_S 0 318 319 #define EFUSE_CODING_SCHEME_VAL_NONE 0x0 320 #define EFUSE_CODING_SCHEME_VAL_34 0x1 321 #define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 322 323 #define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c) 324 /* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[26:20] ;default: 7'b0 ; */ 325 /*description: program for flash_crypt_cnt*/ 326 #define EFUSE_FLASH_CRYPT_CNT 0x0000007F 327 #define EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V)<<(EFUSE_FLASH_CRYPT_CNT_S)) 328 #define EFUSE_FLASH_CRYPT_CNT_V 0x7F 329 #define EFUSE_FLASH_CRYPT_CNT_S 20 330 /* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; */ 331 /*description: program for efuse_rd_disable*/ 332 #define EFUSE_RD_DIS 0x0000000F 333 #define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S)) 334 #define EFUSE_RD_DIS_V 0xF 335 #define EFUSE_RD_DIS_S 16 336 /* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ 337 /*description: program for efuse_wr_disable*/ 338 #define EFUSE_WR_DIS 0x0000FFFF 339 #define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S)) 340 #define EFUSE_WR_DIS_V 0xFFFF 341 #define EFUSE_WR_DIS_S 0 342 343 #define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020) 344 /* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ 345 /*description: program for low 32bit WIFI_MAC_Address*/ 346 #define EFUSE_WIFI_MAC_CRC_LOW 0xFFFFFFFF 347 #define EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V)<<(EFUSE_WIFI_MAC_CRC_LOW_S)) 348 #define EFUSE_WIFI_MAC_CRC_LOW_V 0xFFFFFFFF 349 #define EFUSE_WIFI_MAC_CRC_LOW_S 0 350 351 #define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024) 352 /* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ 353 /*description: program for high 24bit WIFI_MAC_Address*/ 354 #define EFUSE_WIFI_MAC_CRC_HIGH 0x00FFFFFF 355 #define EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V)<<(EFUSE_WIFI_MAC_CRC_HIGH_S)) 356 #define EFUSE_WIFI_MAC_CRC_HIGH_V 0xFFFFFF 357 #define EFUSE_WIFI_MAC_CRC_HIGH_S 0 358 359 #define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028) 360 /* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ 361 /*description: */ 362 #define EFUSE_CHIP_VER_REV1 (BIT(15)) 363 #define EFUSE_CHIP_VER_REV1_M ((EFUSE_CHIP_VER_REV1_V)<<(EFUSE_CHIP_VER_REV1_S)) 364 #define EFUSE_CHIP_VER_REV1_V 0x1 365 #define EFUSE_CHIP_VER_REV1_S 15 366 /* EFUSE_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ 367 /*description: If set, this bit indicates that BLOCK3[143:96] is reserved for internal use*/ 368 #define EFUSE_BLK3_PART_RESERVE (BIT(14)) 369 #define EFUSE_BLK3_PART_RESERVE_M ((EFUSE_BLK3_PART_RESERVE_V)<<(EFUSE_BLK3_PART_RESERVE_S)) 370 #define EFUSE_BLK3_PART_RESERVE_V 0x1 371 #define EFUSE_BLK3_PART_RESERVE_S 14 372 /* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; */ 373 /*description: If set, the ESP32's maximum CPU frequency has been rated*/ 374 #define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) 375 #define EFUSE_CHIP_CPU_FREQ_RATED_M ((EFUSE_CHIP_CPU_FREQ_RATED_V)<<(EFUSE_CHIP_CPU_FREQ_RATED_S)) 376 #define EFUSE_CHIP_CPU_FREQ_RATED_V 0x1 377 #define EFUSE_CHIP_CPU_FREQ_RATED_S 13 378 /* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; */ 379 /*description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max CPU frequency is rated for 160MHz. 240MHz otherwise*/ 380 #define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) 381 #define EFUSE_CHIP_CPU_FREQ_LOW_M ((EFUSE_CHIP_CPU_FREQ_LOW_V)<<(EFUSE_CHIP_CPU_FREQ_LOW_S)) 382 #define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1 383 #define EFUSE_CHIP_CPU_FREQ_LOW_S 12 384 /* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; */ 385 /*description: least significant bits of chip package */ 386 #define EFUSE_CHIP_VER_PKG 0x00000007 387 #define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V)<<(EFUSE_CHIP_VER_PKG_S)) 388 #define EFUSE_CHIP_VER_PKG_V 0x7 389 #define EFUSE_CHIP_VER_PKG_S 9 390 #define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6 0 391 #define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5 1 392 #define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2 393 #define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4 394 #define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5 395 #define EFUSE_CHIP_VER_PKG_ESP32PICOV302 6 396 /* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; */ 397 /*description: program for SPI_pad_config_hd*/ 398 #define EFUSE_SPI_PAD_CONFIG_HD 0x0000001F 399 #define EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V)<<(EFUSE_SPI_PAD_CONFIG_HD_S)) 400 #define EFUSE_SPI_PAD_CONFIG_HD_V 0x1F 401 #define EFUSE_SPI_PAD_CONFIG_HD_S 4 402 /* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; */ 403 /*description: */ 404 #define EFUSE_CHIP_VER_DIS_CACHE (BIT(3)) 405 #define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3)) 406 #define EFUSE_CHIP_VER_DIS_CACHE_V 0x1 407 #define EFUSE_CHIP_VER_DIS_CACHE_S 3 408 /* EFUSE_CHIP_VER_PKG_4BIT : RO ;bitpos:[2] ;default: 1'b0 ; */ 409 /*description: most significant bit of chip package */ 410 #define EFUSE_CHIP_VER_PKG_4BIT (BIT(2)) 411 #define EFUSE_CHIP_VER_PKG_4BIT_M (BIT(2)) 412 #define EFUSE_CHIP_VER_PKG_4BIT_V 0x1 413 #define EFUSE_CHIP_VER_PKG_4BIT_S 2 414 /* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; */ 415 /*description: */ 416 #define EFUSE_CHIP_VER_DIS_BT (BIT(1)) 417 #define EFUSE_CHIP_VER_DIS_BT_M (BIT(1)) 418 #define EFUSE_CHIP_VER_DIS_BT_V 0x1 419 #define EFUSE_CHIP_VER_DIS_BT_S 1 420 /* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */ 421 /*description: */ 422 #define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0)) 423 #define EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0)) 424 #define EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1 425 #define EFUSE_CHIP_VER_DIS_APP_CPU_S 0 426 427 #define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c) 428 /* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ 429 /*description: program for sdio_force*/ 430 #define EFUSE_SDIO_FORCE (BIT(16)) 431 #define EFUSE_SDIO_FORCE_M (BIT(16)) 432 #define EFUSE_SDIO_FORCE_V 0x1 433 #define EFUSE_SDIO_FORCE_S 16 434 /* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; */ 435 /*description: program for SDIO_TIEH*/ 436 #define EFUSE_SDIO_TIEH (BIT(15)) 437 #define EFUSE_SDIO_TIEH_M (BIT(15)) 438 #define EFUSE_SDIO_TIEH_V 0x1 439 #define EFUSE_SDIO_TIEH_S 15 440 /* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; */ 441 /*description: program for XPD_SDIO_REG*/ 442 #define EFUSE_XPD_SDIO_REG (BIT(14)) 443 #define EFUSE_XPD_SDIO_REG_M (BIT(14)) 444 #define EFUSE_XPD_SDIO_REG_V 0x1 445 #define EFUSE_XPD_SDIO_REG_S 14 446 /* EFUSE_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; */ 447 /*description: True ADC reference voltage */ 448 #define EFUSE_ADC_VREF 0x0000001F 449 #define EFUSE_ADC_VREF_M ((EFUSE_ADC_VREF_V)<<(EFUSE_ADC_VREF_S)) 450 #define EFUSE_ADC_VREF_V 0x1F 451 #define EFUSE_ADC_VREF_S 8 452 /* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. Newer 453 * versions of ESP32 come with EFUSE_ADC_VREF already burned, therefore 454 * SDIO_DREFH/M/L is only available in older versions of ESP32 */ 455 /* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ 456 /*description: */ 457 #define EFUSE_SDIO_DREFL 0x00000003 458 #define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S)) 459 #define EFUSE_SDIO_DREFL_V 0x3 460 #define EFUSE_SDIO_DREFL_S 12 461 /* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ 462 /*description: */ 463 #define EFUSE_SDIO_DREFM 0x00000003 464 #define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S)) 465 #define EFUSE_SDIO_DREFM_V 0x3 466 #define EFUSE_SDIO_DREFM_S 10 467 /* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ 468 /*description: */ 469 #define EFUSE_SDIO_DREFH 0x00000003 470 #define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S)) 471 #define EFUSE_SDIO_DREFH_V 0x3 472 #define EFUSE_SDIO_DREFH_S 8 473 /* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ 474 /*description: */ 475 #define EFUSE_CK8M_FREQ 0x000000FF 476 #define EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V)<<(EFUSE_CK8M_FREQ_S)) 477 #define EFUSE_CK8M_FREQ_V 0xFF 478 #define EFUSE_CK8M_FREQ_S 0 479 480 #define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030) 481 /* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; */ 482 /*description: program for flash_crypt_config*/ 483 #define EFUSE_FLASH_CRYPT_CONFIG 0x0000000F 484 #define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V)<<(EFUSE_FLASH_CRYPT_CONFIG_S)) 485 #define EFUSE_FLASH_CRYPT_CONFIG_V 0xF 486 #define EFUSE_FLASH_CRYPT_CONFIG_S 28 487 /* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; */ 488 /*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (R/W) 489 BIT[27] is the sign bit, 0: + , 1: - 490 BIT[26:24] is the difference value, unit: 0.017V 491 volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */ 492 #define EFUSE_DIG_VOL_L6 0x0F 493 #define EFUSE_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S)) 494 #define EFUSE_DIG_VOL_L6_V 0x0F 495 #define EFUSE_DIG_VOL_L6_S 24 496 /* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] */ 497 /*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. 498 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)*/ 499 #define EFUSE_VOL_LEVEL_HP_INV 0x03 500 #define EFUSE_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V)<<(EFUSE_RD_VOL_LEVEL_HP_INV_S)) 501 #define EFUSE_VOL_LEVEL_HP_INV_V 0x03 502 #define EFUSE_VOL_LEVEL_HP_INV_S 22 503 /* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; */ 504 /* Deprecated */ 505 #define EFUSE_INST_CONFIG 0x000000FF /** Deprecated **/ 506 #define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V)<<(EFUSE_INST_CONFIG_S)) /** Deprecated **/ 507 #define EFUSE_INST_CONFIG_V 0xFF /** Deprecated **/ 508 #define EFUSE_INST_CONFIG_S 20 /** Deprecated **/ 509 /* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; */ 510 /*description: program for SPI_pad_config_cs0*/ 511 #define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001F 512 #define EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V)<<(EFUSE_SPI_PAD_CONFIG_CS0_S)) 513 #define EFUSE_SPI_PAD_CONFIG_CS0_V 0x1F 514 #define EFUSE_SPI_PAD_CONFIG_CS0_S 15 515 /* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; */ 516 /*description: program for SPI_pad_config_d*/ 517 #define EFUSE_SPI_PAD_CONFIG_D 0x0000001F 518 #define EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V)<<(EFUSE_SPI_PAD_CONFIG_D_S)) 519 #define EFUSE_SPI_PAD_CONFIG_D_V 0x1F 520 #define EFUSE_SPI_PAD_CONFIG_D_S 10 521 /* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ 522 /*description: program for SPI_pad_config_q*/ 523 #define EFUSE_SPI_PAD_CONFIG_Q 0x0000001F 524 #define EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V)<<(EFUSE_SPI_PAD_CONFIG_Q_S)) 525 #define EFUSE_SPI_PAD_CONFIG_Q_V 0x1F 526 #define EFUSE_SPI_PAD_CONFIG_Q_S 5 527 /* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ 528 /*description: program for SPI_pad_config_clk*/ 529 #define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001F 530 #define EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V)<<(EFUSE_SPI_PAD_CONFIG_CLK_S)) 531 #define EFUSE_SPI_PAD_CONFIG_CLK_V 0x1F 532 #define EFUSE_SPI_PAD_CONFIG_CLK_S 0 533 534 #define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034) 535 /* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; */ 536 /*description: program for key_status*/ 537 #define EFUSE_KEY_STATUS (BIT(10)) 538 #define EFUSE_KEY_STATUS_M (BIT(10)) 539 #define EFUSE_KEY_STATUS_V 0x1 540 #define EFUSE_KEY_STATUS_S 10 541 /* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */ 542 /*description: program for download_dis_cache*/ 543 #define EFUSE_DISABLE_DL_CACHE (BIT(9)) 544 #define EFUSE_DISABLE_DL_CACHE_M (BIT(9)) 545 #define EFUSE_DISABLE_DL_CACHE_V 0x1 546 #define EFUSE_DISABLE_DL_CACHE_S 9 547 /* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; */ 548 /*description: program for download_dis_decrypt*/ 549 #define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) 550 #define EFUSE_DISABLE_DL_DECRYPT_M (BIT(8)) 551 #define EFUSE_DISABLE_DL_DECRYPT_V 0x1 552 #define EFUSE_DISABLE_DL_DECRYPT_S 8 553 /* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; */ 554 /*description: program for download_dis_encrypt*/ 555 #define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) 556 #define EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7)) 557 #define EFUSE_DISABLE_DL_ENCRYPT_V 0x1 558 #define EFUSE_DISABLE_DL_ENCRYPT_S 7 559 /* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; */ 560 /*description: program for JTAG_disable*/ 561 #define EFUSE_DISABLE_JTAG (BIT(6)) 562 #define EFUSE_DISABLE_JTAG_M (BIT(6)) 563 #define EFUSE_DISABLE_JTAG_V 0x1 564 #define EFUSE_DISABLE_JTAG_S 6 565 /* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ 566 /*description: program for abstract_done_1*/ 567 #define EFUSE_ABS_DONE_1 (BIT(5)) 568 #define EFUSE_ABS_DONE_1_M (BIT(5)) 569 #define EFUSE_ABS_DONE_1_V 0x1 570 #define EFUSE_ABS_DONE_1_S 5 571 /* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ 572 /*description: program for abstract_done_0*/ 573 #define EFUSE_ABS_DONE_0 (BIT(4)) 574 #define EFUSE_ABS_DONE_0_M (BIT(4)) 575 #define EFUSE_ABS_DONE_0_V 0x1 576 #define EFUSE_ABS_DONE_0_S 4 577 /* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; */ 578 /*description: */ 579 #define EFUSE_DISABLE_SDIO_HOST (BIT(3)) 580 #define EFUSE_DISABLE_SDIO_HOST_M (BIT(3)) 581 #define EFUSE_DISABLE_SDIO_HOST_V 0x1 582 #define EFUSE_DISABLE_SDIO_HOST_S 3 583 /* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ 584 /*description: program for console_debug_disable*/ 585 #define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) 586 #define EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2)) 587 #define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1 588 #define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 589 /* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ 590 /*description: program for coding_scheme*/ 591 #define EFUSE_CODING_SCHEME 0x00000003 592 #define EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V)<<(EFUSE_CODING_SCHEME_S)) 593 #define EFUSE_CODING_SCHEME_V 0x3 594 #define EFUSE_CODING_SCHEME_S 0 595 596 #define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038) 597 /* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 598 /*description: read for BLOCK1*/ 599 #define EFUSE_BLK1_DOUT0 0xFFFFFFFF 600 #define EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V)<<(EFUSE_BLK1_DOUT0_S)) 601 #define EFUSE_BLK1_DOUT0_V 0xFFFFFFFF 602 #define EFUSE_BLK1_DOUT0_S 0 603 604 #define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c) 605 /* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 606 /*description: read for BLOCK1*/ 607 #define EFUSE_BLK1_DOUT1 0xFFFFFFFF 608 #define EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V)<<(EFUSE_BLK1_DOUT1_S)) 609 #define EFUSE_BLK1_DOUT1_V 0xFFFFFFFF 610 #define EFUSE_BLK1_DOUT1_S 0 611 612 #define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040) 613 /* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 614 /*description: read for BLOCK1*/ 615 #define EFUSE_BLK1_DOUT2 0xFFFFFFFF 616 #define EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V)<<(EFUSE_BLK1_DOUT2_S)) 617 #define EFUSE_BLK1_DOUT2_V 0xFFFFFFFF 618 #define EFUSE_BLK1_DOUT2_S 0 619 620 #define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044) 621 /* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 622 /*description: read for BLOCK1*/ 623 #define EFUSE_BLK1_DOUT3 0xFFFFFFFF 624 #define EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V)<<(EFUSE_BLK1_DOUT3_S)) 625 #define EFUSE_BLK1_DOUT3_V 0xFFFFFFFF 626 #define EFUSE_BLK1_DOUT3_S 0 627 628 #define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048) 629 /* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 630 /*description: read for BLOCK1*/ 631 #define EFUSE_BLK1_DOUT4 0xFFFFFFFF 632 #define EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V)<<(EFUSE_BLK1_DOUT4_S)) 633 #define EFUSE_BLK1_DOUT4_V 0xFFFFFFFF 634 #define EFUSE_BLK1_DOUT4_S 0 635 636 #define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c) 637 /* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 638 /*description: read for BLOCK1*/ 639 #define EFUSE_BLK1_DOUT5 0xFFFFFFFF 640 #define EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V)<<(EFUSE_BLK1_DOUT5_S)) 641 #define EFUSE_BLK1_DOUT5_V 0xFFFFFFFF 642 #define EFUSE_BLK1_DOUT5_S 0 643 644 #define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050) 645 /* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 646 /*description: read for BLOCK1*/ 647 #define EFUSE_BLK1_DOUT6 0xFFFFFFFF 648 #define EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V)<<(EFUSE_BLK1_DOUT6_S)) 649 #define EFUSE_BLK1_DOUT6_V 0xFFFFFFFF 650 #define EFUSE_BLK1_DOUT6_S 0 651 652 #define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054) 653 /* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 654 /*description: read for BLOCK1*/ 655 #define EFUSE_BLK1_DOUT7 0xFFFFFFFF 656 #define EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V)<<(EFUSE_BLK1_DOUT7_S)) 657 #define EFUSE_BLK1_DOUT7_V 0xFFFFFFFF 658 #define EFUSE_BLK1_DOUT7_S 0 659 660 #define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058) 661 /* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 662 /*description: read for BLOCK2*/ 663 #define EFUSE_BLK2_DOUT0 0xFFFFFFFF 664 #define EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V)<<(EFUSE_BLK2_DOUT0_S)) 665 #define EFUSE_BLK2_DOUT0_V 0xFFFFFFFF 666 #define EFUSE_BLK2_DOUT0_S 0 667 668 #define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c) 669 /* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 670 /*description: read for BLOCK2*/ 671 #define EFUSE_BLK2_DOUT1 0xFFFFFFFF 672 #define EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V)<<(EFUSE_BLK2_DOUT1_S)) 673 #define EFUSE_BLK2_DOUT1_V 0xFFFFFFFF 674 #define EFUSE_BLK2_DOUT1_S 0 675 676 #define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060) 677 /* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 678 /*description: read for BLOCK2*/ 679 #define EFUSE_BLK2_DOUT2 0xFFFFFFFF 680 #define EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V)<<(EFUSE_BLK2_DOUT2_S)) 681 #define EFUSE_BLK2_DOUT2_V 0xFFFFFFFF 682 #define EFUSE_BLK2_DOUT2_S 0 683 684 #define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064) 685 /* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 686 /*description: read for BLOCK2*/ 687 #define EFUSE_BLK2_DOUT3 0xFFFFFFFF 688 #define EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V)<<(EFUSE_BLK2_DOUT3_S)) 689 #define EFUSE_BLK2_DOUT3_V 0xFFFFFFFF 690 #define EFUSE_BLK2_DOUT3_S 0 691 692 #define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068) 693 /* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 694 /*description: read for BLOCK2*/ 695 #define EFUSE_BLK2_DOUT4 0xFFFFFFFF 696 #define EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V)<<(EFUSE_BLK2_DOUT4_S)) 697 #define EFUSE_BLK2_DOUT4_V 0xFFFFFFFF 698 #define EFUSE_BLK2_DOUT4_S 0 699 700 #define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c) 701 /* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 702 /*description: read for BLOCK2*/ 703 #define EFUSE_BLK2_DOUT5 0xFFFFFFFF 704 #define EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V)<<(EFUSE_BLK2_DOUT5_S)) 705 #define EFUSE_BLK2_DOUT5_V 0xFFFFFFFF 706 #define EFUSE_BLK2_DOUT5_S 0 707 708 #define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070) 709 /* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 710 /*description: read for BLOCK2*/ 711 #define EFUSE_BLK2_DOUT6 0xFFFFFFFF 712 #define EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V)<<(EFUSE_BLK2_DOUT6_S)) 713 #define EFUSE_BLK2_DOUT6_V 0xFFFFFFFF 714 #define EFUSE_BLK2_DOUT6_S 0 715 716 #define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074) 717 /* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 718 /*description: read for BLOCK2*/ 719 #define EFUSE_BLK2_DOUT7 0xFFFFFFFF 720 #define EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V)<<(EFUSE_BLK2_DOUT7_S)) 721 #define EFUSE_BLK2_DOUT7_V 0xFFFFFFFF 722 #define EFUSE_BLK2_DOUT7_S 0 723 724 #define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078) 725 /* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 726 /*description: read for BLOCK3*/ 727 #define EFUSE_BLK3_DOUT0 0xFFFFFFFF 728 #define EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V)<<(EFUSE_BLK3_DOUT0_S)) 729 #define EFUSE_BLK3_DOUT0_V 0xFFFFFFFF 730 #define EFUSE_BLK3_DOUT0_S 0 731 732 #define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c) 733 /* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 734 /*description: read for BLOCK3*/ 735 #define EFUSE_BLK3_DOUT1 0xFFFFFFFF 736 #define EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V)<<(EFUSE_BLK3_DOUT1_S)) 737 #define EFUSE_BLK3_DOUT1_V 0xFFFFFFFF 738 #define EFUSE_BLK3_DOUT1_S 0 739 740 #define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080) 741 /* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 742 /*description: read for BLOCK3*/ 743 #define EFUSE_BLK3_DOUT2 0xFFFFFFFF 744 #define EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V)<<(EFUSE_BLK3_DOUT2_S)) 745 #define EFUSE_BLK3_DOUT2_V 0xFFFFFFFF 746 #define EFUSE_BLK3_DOUT2_S 0 747 748 /* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration 749 * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/ 750 #define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084) 751 /* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 752 /*description: read for BLOCK3*/ 753 #define EFUSE_BLK3_DOUT3 0xFFFFFFFF 754 #define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V)<<(EFUSE_BLK3_DOUT3_S)) 755 #define EFUSE_BLK3_DOUT3_V 0xFFFFFFFF 756 #define EFUSE_BLK3_DOUT3_S 0 757 /* EFUSE_RD_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */ 758 /*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 759 #define EFUSE_RD_ADC2_TP_HIGH 0x1FF 760 #define EFUSE_RD_ADC2_TP_HIGH_M ((EFUSE_RD_ADC2_TP_HIGH_V)<<(EFUSE_RD_ADC2_TP_HIGH_S)) 761 #define EFUSE_RD_ADC2_TP_HIGH_V 0x1FF 762 #define EFUSE_RD_ADC2_TP_HIGH_S 23 763 /* EFUSE_RD_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */ 764 /*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 765 #define EFUSE_RD_ADC2_TP_LOW 0x7F 766 #define EFUSE_RD_ADC2_TP_LOW_M ((EFUSE_RD_ADC2_TP_LOW_V)<<(EFUSE_RD_ADC2_TP_LOW_S)) 767 #define EFUSE_RD_ADC2_TP_LOW_V 0x7F 768 #define EFUSE_RD_ADC2_TP_LOW_S 16 769 /* EFUSE_RD_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */ 770 /*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 771 #define EFUSE_RD_ADC1_TP_HIGH 0x1FF 772 #define EFUSE_RD_ADC1_TP_HIGH_M ((EFUSE_RD_ADC1_TP_HIGH_V)<<(EFUSE_RD_ADC1_TP_HIGH_S)) 773 #define EFUSE_RD_ADC1_TP_HIGH_V 0x1FF 774 #define EFUSE_RD_ADC1_TP_HIGH_S 7 775 /* EFUSE_RD_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ 776 /*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 777 #define EFUSE_RD_ADC1_TP_LOW 0x7F 778 #define EFUSE_RD_ADC1_TP_LOW_M ((EFUSE_RD_ADC1_TP_LOW_V)<<(EFUSE_RD_ADC1_TP_LOW_S)) 779 #define EFUSE_RD_ADC1_TP_LOW_V 0x7F 780 #define EFUSE_RD_ADC1_TP_LOW_S 0 781 782 #define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088) 783 /* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 784 /*description: read for BLOCK3*/ 785 #define EFUSE_BLK3_DOUT4 0xFFFFFFFF 786 #define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V)<<(EFUSE_BLK3_DOUT4_S)) 787 #define EFUSE_BLK3_DOUT4_V 0xFFFFFFFF 788 #define EFUSE_BLK3_DOUT4_S 0 789 /* EFUSE_RD_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */ 790 /*description: Reserved for future calibration use. Indicated by EFUSE_RD_BLK3_PART_RESERVE */ 791 #define EFUSE_RD_CAL_RESERVED 0x0000FFFF 792 #define EFUSE_RD_CAL_RESERVED_M ((EFUSE_RD_CAL_RESERVED_V)<<(EFUSE_RD_CAL_RESERVED_S)) 793 #define EFUSE_RD_CAL_RESERVED_V 0xFFFF 794 #define EFUSE_RD_CAL_RESERVED_S 0 795 796 #define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c) 797 /* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 798 /*description: read for BLOCK3*/ 799 #define EFUSE_BLK3_DOUT5 0xFFFFFFFF 800 #define EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V)<<(EFUSE_BLK3_DOUT5_S)) 801 #define EFUSE_BLK3_DOUT5_V 0xFFFFFFFF 802 #define EFUSE_BLK3_DOUT5_S 0 803 804 #define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090) 805 /* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 806 /*description: read for BLOCK3*/ 807 #define EFUSE_BLK3_DOUT6 0xFFFFFFFF 808 #define EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V)<<(EFUSE_BLK3_DOUT6_S)) 809 #define EFUSE_BLK3_DOUT6_V 0xFFFFFFFF 810 #define EFUSE_BLK3_DOUT6_S 0 811 812 #define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094) 813 /* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 814 /*description: read for BLOCK3*/ 815 #define EFUSE_BLK3_DOUT7 0xFFFFFFFF 816 #define EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V)<<(EFUSE_BLK3_DOUT7_S)) 817 #define EFUSE_BLK3_DOUT7_V 0xFFFFFFFF 818 #define EFUSE_BLK3_DOUT7_S 0 819 820 #define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098) 821 /* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 822 /*description: program for BLOCK1*/ 823 #define EFUSE_BLK1_DIN0 0xFFFFFFFF 824 #define EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V)<<(EFUSE_BLK1_DIN0_S)) 825 #define EFUSE_BLK1_DIN0_V 0xFFFFFFFF 826 #define EFUSE_BLK1_DIN0_S 0 827 828 #define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c) 829 /* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 830 /*description: program for BLOCK1*/ 831 #define EFUSE_BLK1_DIN1 0xFFFFFFFF 832 #define EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V)<<(EFUSE_BLK1_DIN1_S)) 833 #define EFUSE_BLK1_DIN1_V 0xFFFFFFFF 834 #define EFUSE_BLK1_DIN1_S 0 835 836 #define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0) 837 /* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 838 /*description: program for BLOCK1*/ 839 #define EFUSE_BLK1_DIN2 0xFFFFFFFF 840 #define EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V)<<(EFUSE_BLK1_DIN2_S)) 841 #define EFUSE_BLK1_DIN2_V 0xFFFFFFFF 842 #define EFUSE_BLK1_DIN2_S 0 843 844 #define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4) 845 /* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 846 /*description: program for BLOCK1*/ 847 #define EFUSE_BLK1_DIN3 0xFFFFFFFF 848 #define EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V)<<(EFUSE_BLK1_DIN3_S)) 849 #define EFUSE_BLK1_DIN3_V 0xFFFFFFFF 850 #define EFUSE_BLK1_DIN3_S 0 851 852 #define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8) 853 /* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 854 /*description: program for BLOCK1*/ 855 #define EFUSE_BLK1_DIN4 0xFFFFFFFF 856 #define EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V)<<(EFUSE_BLK1_DIN4_S)) 857 #define EFUSE_BLK1_DIN4_V 0xFFFFFFFF 858 #define EFUSE_BLK1_DIN4_S 0 859 860 #define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac) 861 /* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 862 /*description: program for BLOCK1*/ 863 #define EFUSE_BLK1_DIN5 0xFFFFFFFF 864 #define EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V)<<(EFUSE_BLK1_DIN5_S)) 865 #define EFUSE_BLK1_DIN5_V 0xFFFFFFFF 866 #define EFUSE_BLK1_DIN5_S 0 867 868 #define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0) 869 /* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 870 /*description: program for BLOCK1*/ 871 #define EFUSE_BLK1_DIN6 0xFFFFFFFF 872 #define EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V)<<(EFUSE_BLK1_DIN6_S)) 873 #define EFUSE_BLK1_DIN6_V 0xFFFFFFFF 874 #define EFUSE_BLK1_DIN6_S 0 875 876 #define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4) 877 /* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 878 /*description: program for BLOCK1*/ 879 #define EFUSE_BLK1_DIN7 0xFFFFFFFF 880 #define EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V)<<(EFUSE_BLK1_DIN7_S)) 881 #define EFUSE_BLK1_DIN7_V 0xFFFFFFFF 882 #define EFUSE_BLK1_DIN7_S 0 883 884 #define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8) 885 /* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 886 /*description: program for BLOCK2*/ 887 #define EFUSE_BLK2_DIN0 0xFFFFFFFF 888 #define EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V)<<(EFUSE_BLK2_DIN0_S)) 889 #define EFUSE_BLK2_DIN0_V 0xFFFFFFFF 890 #define EFUSE_BLK2_DIN0_S 0 891 892 #define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc) 893 /* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 894 /*description: program for BLOCK2*/ 895 #define EFUSE_BLK2_DIN1 0xFFFFFFFF 896 #define EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V)<<(EFUSE_BLK2_DIN1_S)) 897 #define EFUSE_BLK2_DIN1_V 0xFFFFFFFF 898 #define EFUSE_BLK2_DIN1_S 0 899 900 #define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0) 901 /* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 902 /*description: program for BLOCK2*/ 903 #define EFUSE_BLK2_DIN2 0xFFFFFFFF 904 #define EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V)<<(EFUSE_BLK2_DIN2_S)) 905 #define EFUSE_BLK2_DIN2_V 0xFFFFFFFF 906 #define EFUSE_BLK2_DIN2_S 0 907 908 #define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4) 909 /* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 910 /*description: program for BLOCK2*/ 911 #define EFUSE_BLK2_DIN3 0xFFFFFFFF 912 #define EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V)<<(EFUSE_BLK2_DIN3_S)) 913 #define EFUSE_BLK2_DIN3_V 0xFFFFFFFF 914 #define EFUSE_BLK2_DIN3_S 0 915 916 #define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8) 917 /* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 918 /*description: program for BLOCK2*/ 919 #define EFUSE_BLK2_DIN4 0xFFFFFFFF 920 #define EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V)<<(EFUSE_BLK2_DIN4_S)) 921 #define EFUSE_BLK2_DIN4_V 0xFFFFFFFF 922 #define EFUSE_BLK2_DIN4_S 0 923 924 #define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc) 925 /* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 926 /*description: program for BLOCK2*/ 927 #define EFUSE_BLK2_DIN5 0xFFFFFFFF 928 #define EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V)<<(EFUSE_BLK2_DIN5_S)) 929 #define EFUSE_BLK2_DIN5_V 0xFFFFFFFF 930 #define EFUSE_BLK2_DIN5_S 0 931 932 #define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0) 933 /* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 934 /*description: program for BLOCK2*/ 935 #define EFUSE_BLK2_DIN6 0xFFFFFFFF 936 #define EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V)<<(EFUSE_BLK2_DIN6_S)) 937 #define EFUSE_BLK2_DIN6_V 0xFFFFFFFF 938 #define EFUSE_BLK2_DIN6_S 0 939 940 #define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4) 941 /* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 942 /*description: program for BLOCK2*/ 943 #define EFUSE_BLK2_DIN7 0xFFFFFFFF 944 #define EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V)<<(EFUSE_BLK2_DIN7_S)) 945 #define EFUSE_BLK2_DIN7_V 0xFFFFFFFF 946 #define EFUSE_BLK2_DIN7_S 0 947 948 #define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8) 949 /* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 950 /*description: program for BLOCK3*/ 951 #define EFUSE_BLK3_DIN0 0xFFFFFFFF 952 #define EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V)<<(EFUSE_BLK3_DIN0_S)) 953 #define EFUSE_BLK3_DIN0_V 0xFFFFFFFF 954 #define EFUSE_BLK3_DIN0_S 0 955 956 #define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc) 957 /* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 958 /*description: program for BLOCK3*/ 959 #define EFUSE_BLK3_DIN1 0xFFFFFFFF 960 #define EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V)<<(EFUSE_BLK3_DIN1_S)) 961 #define EFUSE_BLK3_DIN1_V 0xFFFFFFFF 962 #define EFUSE_BLK3_DIN1_S 0 963 964 #define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0) 965 /* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 966 /*description: program for BLOCK3*/ 967 #define EFUSE_BLK3_DIN2 0xFFFFFFFF 968 #define EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V)<<(EFUSE_BLK3_DIN2_S)) 969 #define EFUSE_BLK3_DIN2_V 0xFFFFFFFF 970 #define EFUSE_BLK3_DIN2_S 0 971 972 /* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for calibration 973 * purposes. This usage is indicated by the EFUSE_RD_BLK3_PART_RESERVE bit.*/ 974 #define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4) 975 /* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 976 /*description: program for BLOCK3*/ 977 #define EFUSE_BLK3_DIN3 0xFFFFFFFF 978 #define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V)<<(EFUSE_BLK3_DIN3_S)) 979 #define EFUSE_BLK3_DIN3_V 0xFFFFFFFF 980 #define EFUSE_BLK3_DIN3_S 0 981 /* EFUSE_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; */ 982 /*description: ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 983 #define EFUSE_ADC2_TP_HIGH 0x1FF 984 #define EFUSE_ADC2_TP_HIGH_M ((EFUSE_ADC2_TP_HIGH_V)<<(EFUSE_ADC2_TP_HIGH_S)) 985 #define EFUSE_ADC2_TP_HIGH_V 0x1FF 986 #define EFUSE_ADC2_TP_HIGH_S 23 987 /* EFUSE_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; */ 988 /*description: ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 989 #define EFUSE_ADC2_TP_LOW 0x7F 990 #define EFUSE_ADC2_TP_LOW_M ((EFUSE_ADC2_TP_LOW_V)<<(EFUSE_ADC2_TP_LOW_S)) 991 #define EFUSE_ADC2_TP_LOW_V 0x7F 992 #define EFUSE_ADC2_TP_LOW_S 16 993 /* EFUSE_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; */ 994 /*description: ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 995 #define EFUSE_ADC1_TP_HIGH 0x1FF 996 #define EFUSE_ADC1_TP_HIGH_M ((EFUSE_ADC1_TP_HIGH_V)<<(EFUSE_ADC1_TP_HIGH_S)) 997 #define EFUSE_ADC1_TP_HIGH_V 0x1FF 998 #define EFUSE_ADC1_TP_HIGH_S 7 999 /* EFUSE_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ 1000 /*description: ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE */ 1001 #define EFUSE_ADC1_TP_LOW 0x7F 1002 #define EFUSE_ADC1_TP_LOW_M ((EFUSE_ADC1_TP_LOW_V)<<(EFUSE_ADC1_TP_LOW_S)) 1003 #define EFUSE_ADC1_TP_LOW_V 0x7F 1004 #define EFUSE_ADC1_TP_LOW_S 0 1005 1006 #define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8) 1007 /* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1008 /*description: program for BLOCK3*/ 1009 #define EFUSE_BLK3_DIN4 0xFFFFFFFF 1010 #define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V)<<(EFUSE_BLK3_DIN4_S)) 1011 #define EFUSE_BLK3_DIN4_V 0xFFFFFFFF 1012 #define EFUSE_BLK3_DIN4_S 0 1013 /* EFUSE_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; */ 1014 /*description: Reserved for future calibration use. Indicated by EFUSE_BLK3_PART_RESERVE */ 1015 #define EFUSE_CAL_RESERVED 0x0000FFFF 1016 #define EFUSE_CAL_RESERVED_M ((EFUSE_CAL_RESERVED_V)<<(EFUSE_CAL_RESERVED_S)) 1017 #define EFUSE_CAL_RESERVED_V 0xFFFF 1018 #define EFUSE_CAL_RESERVED_S 0 1019 1020 #define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec) 1021 /* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1022 /*description: program for BLOCK3*/ 1023 #define EFUSE_BLK3_DIN5 0xFFFFFFFF 1024 #define EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V)<<(EFUSE_BLK3_DIN5_S)) 1025 #define EFUSE_BLK3_DIN5_V 0xFFFFFFFF 1026 #define EFUSE_BLK3_DIN5_S 0 1027 1028 #define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0) 1029 /* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1030 /*description: program for BLOCK3*/ 1031 #define EFUSE_BLK3_DIN6 0xFFFFFFFF 1032 #define EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V)<<(EFUSE_BLK3_DIN6_S)) 1033 #define EFUSE_BLK3_DIN6_V 0xFFFFFFFF 1034 #define EFUSE_BLK3_DIN6_S 0 1035 1036 #define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4) 1037 /* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 1038 /*description: program for BLOCK3*/ 1039 #define EFUSE_BLK3_DIN7 0xFFFFFFFF 1040 #define EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V)<<(EFUSE_BLK3_DIN7_S)) 1041 #define EFUSE_BLK3_DIN7_V 0xFFFFFFFF 1042 #define EFUSE_BLK3_DIN7_S 0 1043 1044 #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8) 1045 /* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ 1046 /*description: */ 1047 #define EFUSE_CLK_EN (BIT(16)) 1048 #define EFUSE_CLK_EN_M (BIT(16)) 1049 #define EFUSE_CLK_EN_V 0x1 1050 #define EFUSE_CLK_EN_S 16 1051 /* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; */ 1052 /*description: efuse timing configure*/ 1053 #define EFUSE_CLK_SEL1 0x000000FF 1054 #define EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V)<<(EFUSE_CLK_SEL1_S)) 1055 #define EFUSE_CLK_SEL1_V 0xFF 1056 #define EFUSE_CLK_SEL1_S 8 1057 /* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; */ 1058 /*description: efuse timing configure*/ 1059 #define EFUSE_CLK_SEL0 0x000000FF 1060 #define EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V)<<(EFUSE_CLK_SEL0_S)) 1061 #define EFUSE_CLK_SEL0_V 0xFF 1062 #define EFUSE_CLK_SEL0_S 0 1063 1064 #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) 1065 /* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; */ 1066 /*description: */ 1067 #define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) 1068 #define EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16)) 1069 #define EFUSE_FORCE_NO_WR_RD_DIS_V 0x1 1070 #define EFUSE_FORCE_NO_WR_RD_DIS_S 16 1071 /* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ 1072 /*description: efuse operation code*/ 1073 #define EFUSE_OP_CODE 0x0000FFFF 1074 #define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S)) 1075 #define EFUSE_OP_CODE_V 0xFFFF 1076 #define EFUSE_OP_CODE_S 0 1077 1078 #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) 1079 /* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 1080 /*description: */ 1081 #define EFUSE_DEBUG 0xFFFFFFFF 1082 #define EFUSE_DEBUG_M ((EFUSE_DEBUG_V)<<(EFUSE_DEBUG_S)) 1083 #define EFUSE_DEBUG_V 0xFFFFFFFF 1084 #define EFUSE_DEBUG_S 0 1085 1086 #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) 1087 /* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1088 /*description: command for program*/ 1089 #define EFUSE_PGM_CMD (BIT(1)) 1090 #define EFUSE_PGM_CMD_M (BIT(1)) 1091 #define EFUSE_PGM_CMD_V 0x1 1092 #define EFUSE_PGM_CMD_S 1 1093 /* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1094 /*description: command for read*/ 1095 #define EFUSE_READ_CMD (BIT(0)) 1096 #define EFUSE_READ_CMD_M (BIT(0)) 1097 #define EFUSE_READ_CMD_V 0x1 1098 #define EFUSE_READ_CMD_S 0 1099 1100 #define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) 1101 /* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 1102 /*description: program done interrupt raw status*/ 1103 #define EFUSE_PGM_DONE_INT_RAW (BIT(1)) 1104 #define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) 1105 #define EFUSE_PGM_DONE_INT_RAW_V 0x1 1106 #define EFUSE_PGM_DONE_INT_RAW_S 1 1107 /* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 1108 /*description: read done interrupt raw status*/ 1109 #define EFUSE_READ_DONE_INT_RAW (BIT(0)) 1110 #define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) 1111 #define EFUSE_READ_DONE_INT_RAW_V 0x1 1112 #define EFUSE_READ_DONE_INT_RAW_S 0 1113 1114 #define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) 1115 /* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 1116 /*description: program done interrupt status*/ 1117 #define EFUSE_PGM_DONE_INT_ST (BIT(1)) 1118 #define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) 1119 #define EFUSE_PGM_DONE_INT_ST_V 0x1 1120 #define EFUSE_PGM_DONE_INT_ST_S 1 1121 /* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 1122 /*description: read done interrupt status*/ 1123 #define EFUSE_READ_DONE_INT_ST (BIT(0)) 1124 #define EFUSE_READ_DONE_INT_ST_M (BIT(0)) 1125 #define EFUSE_READ_DONE_INT_ST_V 0x1 1126 #define EFUSE_READ_DONE_INT_ST_S 0 1127 1128 #define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) 1129 /* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 1130 /*description: program done interrupt enable*/ 1131 #define EFUSE_PGM_DONE_INT_ENA (BIT(1)) 1132 #define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) 1133 #define EFUSE_PGM_DONE_INT_ENA_V 0x1 1134 #define EFUSE_PGM_DONE_INT_ENA_S 1 1135 /* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1136 /*description: read done interrupt enable*/ 1137 #define EFUSE_READ_DONE_INT_ENA (BIT(0)) 1138 #define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) 1139 #define EFUSE_READ_DONE_INT_ENA_V 0x1 1140 #define EFUSE_READ_DONE_INT_ENA_S 0 1141 1142 #define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) 1143 /* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 1144 /*description: program done interrupt clear*/ 1145 #define EFUSE_PGM_DONE_INT_CLR (BIT(1)) 1146 #define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) 1147 #define EFUSE_PGM_DONE_INT_CLR_V 0x1 1148 #define EFUSE_PGM_DONE_INT_CLR_S 1 1149 /* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 1150 /*description: read done interrupt clear*/ 1151 #define EFUSE_READ_DONE_INT_CLR (BIT(0)) 1152 #define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) 1153 #define EFUSE_READ_DONE_INT_CLR_V 0x1 1154 #define EFUSE_READ_DONE_INT_CLR_S 0 1155 1156 #define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) 1157 /* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ 1158 /*description: */ 1159 #define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) 1160 #define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) 1161 #define EFUSE_DAC_CLK_PAD_SEL_V 0x1 1162 #define EFUSE_DAC_CLK_PAD_SEL_S 8 1163 /* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; */ 1164 /*description: efuse timing configure*/ 1165 #define EFUSE_DAC_CLK_DIV 0x000000FF 1166 #define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S)) 1167 #define EFUSE_DAC_CLK_DIV_V 0xFF 1168 #define EFUSE_DAC_CLK_DIV_S 0 1169 1170 #define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) 1171 /* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; */ 1172 /*description: the decode result of 3/4 coding scheme has warning*/ 1173 #define EFUSE_DEC_WARNINGS 0x00000FFF 1174 #define EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V)<<(EFUSE_DEC_WARNINGS_S)) 1175 #define EFUSE_DEC_WARNINGS_V 0xFFF 1176 #define EFUSE_DEC_WARNINGS_S 0 1177 1178 #define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) 1179 /* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; */ 1180 /*description: */ 1181 #define EFUSE_DATE 0xFFFFFFFF 1182 #define EFUSE_DATE_M ((EFUSE_DATE_V)<<(EFUSE_DATE_S)) 1183 #define EFUSE_DATE_V 0xFFFFFFFF 1184 #define EFUSE_DATE_S 0 1185 1186 1187 1188 1189 #endif /*_SOC_EFUSE_REG_H_ */ 1190