1 /* 2 * linux-5.4/drivers/media/platform/sunxi-vin/vin-video/dma_reg_i.h 3 * 4 * Copyright (c) 2007-2017 Allwinnertech Co., Ltd. 5 * 6 * Authors: Zhao Wei <zhaowei@allwinnertech.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef __CSIC__DMA__REG__I__H__ 20 #define __CSIC__DMA__REG__I__H__ 21 22 /* 23 * Detail information of registers 24 */ 25 #define CSIC_DMA_EN_REG_OFF 0X000 26 #define CSIC_DMA_TOP_EN 0 27 #define CSIC_DMA_TOP_EN_MASK (0X1 << CSIC_DMA_TOP_EN) 28 #define CSIC_CLK_CNT_EN 1 29 #define CSIC_CLK_CNT_EN_MASK (0X1 << CSIC_CLK_CNT_EN) 30 #define CSIC_CLK_CNT_SPL 2 31 #define CSIC_CLK_CNT_SPL_MASK (0X1 << CSIC_CLK_CNT_SPL) 32 #define CSIC_FBC_EN 3 33 #define CSIC_FBC_EN_MASK (0X1 << CSIC_FBC_EN) 34 #define CSIC_DMA_EN 4 35 #define CSIC_DMA_EN_MASK (0X1 << CSIC_DMA_EN) 36 #define CSIC_FRAME_CNT_EN 5 37 #define CSIC_FRAME_CNT_EN_MASK (0X1 << CSIC_FRAME_CNT_EN) 38 #define CSIC_BUF_ADDR_MODE 7 39 #define CSIC_BUF_ADDR_MODE_MASK (0X1 << CSIC_BUF_ADDR_MODE) 40 #define CSIC_LBC_EN 8 41 #define CSIC_LBC_EN_MASK (0X1 << CSIC_LBC_EN) 42 #define CSIC_FLIP_SIZE_CFG_MODE 28 43 #define CSIC_FLIP_SIZE_CFG_MODE_MASK (0X1 << CSIC_FLIP_SIZE_CFG_MODE) 44 #define CSIC_BUF_LENGTH_CFG_MODE 29 45 #define CSIC_BUF_LENGTH_CFG_MODE_MASK (0X1 << CSIC_BUF_LENGTH_CFG_MODE) 46 #define CSIC_VFLIP_BUF_ADDR_CFG_MODE 30 47 #define CSIC_VFLIP_BUF_ADDR_CFG_MODE_MASK (0X1 << CSIC_VFLIP_BUF_ADDR_CFG_MODE) 48 49 #define CSIC_DMA_CFG_REG_OFF 0X004 50 #define MIN_SDR_WR_SIZE 0 51 #define MIN_SDR_WR_SIZE_MASK (0X3 << MIN_SDR_WR_SIZE) 52 #define FPS_DS 6 53 #define FPS_DS_MASK (0XFF << FPS_DS) 54 #define FIELD_SEL 10 55 #define FIELD_SEL_MASK (0X3 << FIELD_SEL) 56 #define HFLIP_EN 12 57 #define HFLIP_EN_MASK (0X1 << HFLIP_EN) 58 #define VFLIP_EN 13 59 #define VFLIP_EN_MASK (0X1 << VFLIP_EN) 60 #define OUTPUT_FMT 16 61 #define OUTPUT_FMT_MASK (0XF << OUTPUT_FMT) 62 #define ENABLE_10BIT_CUT2_8BIT 21 63 #define ENABLE_10BIT_CUT2_8BIT_MASK (0X1 << ENABLE_10BIT_CUT2_8BIT) 64 #define PAD_VAL 24 65 #define PAD_VAL_MASK (0XFF << PAD_VAL) 66 67 #define CSIC_DMA_HSIZE_REG_OFF 0X010 68 #define HOR_START 0 69 #define HOR_START_MASK (0X3FFF << HOR_START) 70 #define HOR_LEN 16 71 #define HOR_LEN_MASK (0X3FFF << HOR_LEN) 72 73 #define CSIC_DMA_VSIZE_REG_OFF 0X014 74 #define VER_START 0 75 #define VER_START_MASK (0X3FFF << VER_START) 76 #define VER_LEN 16 77 #define VER_LEN_MASK (0X3FFF << VER_LEN) 78 79 #define CSIC_DMA_F0_BUFA_REG_OFF 0X020 80 #define F0_BUFA 0 81 #define F0_BUFA_MASK (0XFFFFFFFF << F0_BUFA) 82 83 #define CSIC_DMA_F1_BUFA_REG_OFF 0X028 84 #define F1_BUFA 0 85 #define F1_BUFA_MASK (0XFFFFFFFF << F1_BUFA) 86 87 #define CSIC_DMA_F2_BUFA_REG_OFF 0X030 88 #define F2_BUFA 0 89 #define F2_BUFA_MASK (0XFFFFFFFF << F2_BUFA) 90 91 #define CSIC_DMA_BUF_LEN_REG_OFF 0X038 92 #define BUF_LEN 0 93 #define BUF_LEN_MASK (0X3FFF << BUF_LEN) 94 #define BUF_LEN_C 16 95 #define BUF_LEN_C_MASK (0X3FFF << BUF_LEN_C) 96 97 #define CSIC_DMA_FLIP_SIZE_REG_OFF 0X03C 98 #define VALID_LEN 0 99 #define VALID_LEN_MASK (0X3FFF << VALID_LEN) 100 #define VER_LEN 16 101 #define VER_LEN_MASK (0X3FFF << VER_LEN) 102 103 #define CSIC_DMA_CAP_STA_REG_OFF 0X04C 104 #define SCAP_STA 0 105 #define SCAP_STA_MASK (0X1 << SCAP_STA) 106 #define VCAP_STA 1 107 #define VCAP_STA_MASK (0X1 << VCAP_STA) 108 #define FIELD_STA 2 109 #define FIELD_STA_MASK (0X1 << FIELD_STA) 110 111 #define CSIC_DMA_INT_EN_REG_OFF 0X050 112 #define CD_INT_EN 0 113 #define CD_INT_EN_MASK (0X1 << CD_INT_EN) 114 #define FD_INT_EN 1 115 #define FD_INT_EN_MASK (0X1 << FD_INT_EN) 116 #define FIFO0_OF_INT_EN 2 117 #define FIFO0_OF_INT_EN_MASK (0X1 << FIFO0_OF_INT_EN) 118 #define FIFO1_OF_INT_EN 3 119 #define FIFO1_OF_INT_EN_MASK (0X1 << FIFO1_OF_INT_EN) 120 #define FIFO2_OF_INT_EN 4 121 #define FIFO2_OF_INT_EN_MASK (0X1 << FIFO2_OF_INT_EN) 122 #define LC_INT_EN 5 123 #define LC_INT_EN_MASK (0X1 << LC_INT_EN) 124 #define HB_OF_INT_EN 6 125 #define HB_OF_INT_EN_MASK (0X1 << HB_OF_INT_EN) 126 #define VS_INT_EN 7 127 #define VS_INT_EN_MASK (0X1 << VS_INT_EN) 128 #define FBC_OVHD_WRDDR_FULL_INT_EN 8 129 #define FBC_OVHD_WRDDR_FULL_INT_EN_MASK (0X1 << FBC_OVHD_WRDDR_FULL_INT_EN) 130 #define FBC_DATA_WRDDR_FULL_INT_EN 9 131 #define FBC_DATA_WRDDR_FULL_INT_EN_MASK (0X1 << FBC_DATA_WRDDR_FULL_INT_EN) 132 #define BUF_ADDR_FIFO_INT_EN 13 133 #define BUF_ADDR_FIFO_INT_EN_MASK (0X1 << BUF_ADDR_FIFO_INT_EN) 134 #define STORED_FRM_CNT_INT_EN 14 135 #define STORED_FRM_CNT_INT_EN_MASK (0X1 << STORED_FRM_CNT_INT_EN) 136 #define FRM_LOST_INT_EN 15 137 #define FRM_LOST_INT_EN_MASK (0X1 << FRM_LOST_INT_EN) 138 139 #define CSIC_DMA_INT_STA_REG_OFF 0X054 140 #define CD_PD 0 141 #define CD_PD_MASK (0X1 << CD_PD) 142 #define FD_PD 1 143 #define FD_PD_MASK (0X1 << FD_PD) 144 #define FIFO0_OF_PD 2 145 #define FIFO0_OF_PD_MASK (0X1 << FIFO0_OF_PD) 146 #define FIFO1_OF_PD 3 147 #define FIFO1_OF_PD_MASK (0X1 << FIFO1_OF_PD) 148 #define FIFO2_OF_PD 4 149 #define FIFO2_OF_PD_MASK (0X1 << FIFO2_OF_PD) 150 #define LC_PD 5 151 #define LC_PD_MASK (0X1 << LC_PD) 152 #define HB_OF_PD 6 153 #define HB_OF_PD_MASK (0X1 << HB_OF_PD) 154 #define VS_PD 7 155 #define VS_PD_MASK (0X1 << VS_PD) 156 #define BUF_ADDR_FIFO_INT_PD 13 157 #define BUF_ADDR_FIFO_INT_PD_MASK (0X1 << BUF_ADDR_FIFO_INT_PD) 158 #define STORED_FRM_CNT_INT_PD 14 159 #define STORED_FRM_CNT_INT_PD_MASK (0X1 << STORED_FRM_CNT_INT_PD) 160 #define FRM_LOST_INT_PD 15 161 #define FRM_LOST_INT_PD_MASK (0X1 << FRM_LOST_INT_PD) 162 #define LBC_HB_INT_PD 16 163 #define LBC_HB_INT_PD_MASK (0X1 << LBC_HB_INT_PD) 164 165 #define CSIC_DMA_LINE_CNT_REG_OFF 0X058 166 #define LINE_CNT_NUM 0 167 #define LINE_CNT_NUM_MASK (0X1FFF << LINE_CNT_NUM) 168 169 #define CSIC_DMA_FRM_CNT_REG_OFF 0X05C 170 #define CSIC_DMA_CLR_DIS 16 171 #define CSIC_DMA_CLR_DIS_MASK (0X7FFF << CSIC_DMA_CLR_DIS) 172 #define CSIC_DMA_FRM_CNT 0 173 #define CSIC_DMA_FRM_CNT_MASK (0XFFFF << CSIC_DMA_FRM_CNT) 174 175 #define CSIC_DMA_FRM_CLK_CNT_REG_OFF 0X060 176 #define FRM_CLK_CNT 0 177 #define FRM_CLK_CNT_MASK (0XFFFFFF << FRM_CLK_CNT) 178 179 #define CSIC_DMA_ACC_ITNL_CLK_CNT_REG_OFF 0X064 180 #define ITNL_CLK_CNT 0 181 #define ITNL_CLK_CNT_MASK (0XFFFFFF << ITNL_CLK_CNT) 182 #define ACC_CLK_CNT 24 183 #define ACC_CLK_CNT_MASK (0XFF << ACC_CLK_CNT) 184 185 #define CSIC_DMA_FIFO_STAT_REG_OFF 0X068 186 #define FIFO_FRM_MAX 0 187 #define FIFO_FRM_MAX_MASK (0XFFF << FIFO_FRM_MAX) 188 189 #define CSIC_DMA_FIFO_THRS_REG_OFF 0X06C 190 #define FIFO_THRS 0 191 #define FIFO_THRS_MASK (0XFFF << FIFO_THRS) 192 #define FIFO_NEARLY_FULL_TH 13 193 #define FIFO_NEARLY_FULL_TH_MASK (0XFF << FIFO_NEARLY_FULL_TH) 194 195 #define CSIC_DMA_PCLK_STAT_REG_OFF 0X070 196 #define PCLK_CNT_LINE_MIN 0 197 #define PCLK_CNT_LINE_MIN_MASK (0XFFF << PCLK_CNT_LINE_MIN) 198 #define PCLK_CNT_LINE_MAX 16 199 #define PCLK_CNT_LINE_MAX_MASK (0XFF << PCLK_CNT_LINE_MAX) 200 201 #define CSIC_DMA_BUFA_F0_ENTRY_REG_OFF 0X080 202 #define BUFA_F0_ENTRY 0 203 #define BUFA_F0_ENTRY_MASK (0XFFFFFFFF << BUFA_F0_ENTRY) 204 205 #define CSIC_DMA_BUFA_F1_ENTRY_REG_OFF 0X084 206 #define BUFA_F1_ENTRY 0 207 #define BUFA_F1_ENTRY_MASK (0XFFFFFFFF << BUFA_F1_ENTRY) 208 209 #define CSIC_DMA_BUFA_F2_ENTRY_REG_OFF 0X088 210 #define BUFA_F1_ENTRY 0 211 #define BUFA_F1_ENTRY_MASK (0XFFFFFFFF << BUFA_F1_ENTRY) 212 213 #define CSIC_DMA_BUF_THRESHOLD_REG_OFF 0X08c 214 #define DMA_BUFA_FIFO_THRESHOLD 0 215 #define DMA_BUFA_FIFO_THRESHOLD_MASK (0x3F << DMA_BUFA_FIFO_THRESHOLD) 216 #define DMA_STORED_FRM_THRESHOLD 16 217 #define DMA_STORED_FRM_THRESHOLD_MASK (0x3F << DMA_STORED_FRM_THRESHOLD) 218 219 #define CSIC_DMA_STORED_FRM_CNT_REG_OFF 0X094 220 #define DMA_STORED_FRM_CNT 0 221 #define DMA_STORED_FRM_CNT_MASK (0xFF << DMA_STORED_FRM_CNT) 222 223 #define CSIC_LBC_CONFIGURE_REG_OFF 0X100 224 #define LIMIT_QP_MIM 0 225 #define LIMIT_QP_MIM_MASK (0X7 << LIMIT_QP_MIM) 226 #define LIMIT_QP_ENABLE 3 227 #define LIMIT_QP_ENABLE_MASK (0X1 << LIMIT_QP_ENABLE) 228 #define UPDATE_ADVANTURE_RATIO 16 229 #define UPDATE_ADVANTURE_RATIO_MASK (0X1F << UPDATE_ADVANTURE_RATIO) 230 #define UPDATE_ADVANTURE_ENABLE 21 231 #define UPDATE_ADVANTURE_ENABLE_MASK (0X1 << UPDATE_ADVANTURE_ENABLE) 232 #define MSQ_ENABLE 24 233 #define MSQ_ENABLE_MASK (0X1 << MSQ_ENABLE) 234 #define OTS_ENABLE 25 235 #define OTS_ENABLE_MASK (0X1 << OTS_ENABLE) 236 #define DTS_ENABLE 26 237 #define DTS_ENABLE_MASK (0X1 << DTS_ENABLE) 238 #define GLB_ENABLE 27 239 #define GLB_ENABLE_MASK (0X1 << GLB_ENABLE) 240 #define WHETHER_LOSSY_ENABLE 31 241 #define WHETHER_LOSSY_ENABLE_MASK (0X1 << WHETHER_LOSSY_ENABLE) 242 243 #define CSIC_LBC_LINE_TARGET_BIT0_REG_OFF 0X104 244 #define CMP_TRG_BIT_FOR_EVEN_LINE 0 245 #define CMP_TRG_BIT_FOR_EVEN_LINE_MASK (0XFFFFF << CMP_TRG_BIT_FOR_EVEN_LINE) 246 247 #define CSIC_LBC_LINE_TARGET_BIT1_REG_OFF 0X108 248 #define CMP_TRG_BIT_FOR_ODD_LINE 0 249 #define CMP_TRG_BIT_FOR_ODD_LINE_MASK (0XFFFFF << CMP_TRG_BIT_FOR_ODD_LINE) 250 251 #define CSIC_LBC_RC_ADV_REG_OFF 0X10C 252 #define RATE_CONTROL_ADVANTURE_0 0 253 #define RATE_CONTROL_ADVANTURE_0_MASK (0XFF << RATE_CONTROL_ADVANTURE_0) 254 #define RATE_CONTROL_ADVANTURE_1 8 255 #define RATE_CONTROL_ADVANTURE_1_MASK (0XFF << RATE_CONTROL_ADVANTURE_1) 256 #define RATE_CONTROL_ADVANTURE_2 16 257 #define RATE_CONTROL_ADVANTURE_2_MASK (0XFF << RATE_CONTROL_ADVANTURE_2) 258 #define RATE_CONTROL_ADVANTURE_3 24 259 #define RATE_CONTROL_ADVANTURE_3_MASK (0XFF << RATE_CONTROL_ADVANTURE_3) 260 261 #define CSIC_LBC_MB_MIN_REG_OFF 0X110 262 #define MACROBLOCK_MIN_BITS0 0 263 #define MACROBLOCK_MIN_BITS0_MASK (0XFF << MACROBLOCK_MIN_BITS0) 264 #define MACROBLOCK_MIN_BITS1 16 265 #define MACROBLOCK_MIN_BITS1_MASK (0XFF << MACROBLOCK_MIN_BITS1) 266 267 #endif /*__CSIC__DMA__REG__I__H__*/ 268