1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef GPIO_REG_H_ 19 #define GPIO_REG_H_ 20 #include "../sys.h" 21 /******************************* gpio registers: 0x140300 ******************************/ 22 // PA 23 #define reg_gpio_pa_setting1 REG_ADDR32(0x140300) 24 #define reg_gpio_pa_in REG_ADDR8(0x140300) 25 #define reg_gpio_pa_ie REG_ADDR8(0x140301) 26 #define reg_gpio_pa_oen REG_ADDR8(0x140302) 27 #define reg_gpio_pa_out REG_ADDR8(0x140303) 28 29 #define reg_gpio_pa_setting2 REG_ADDR32(0x140304) 30 #define reg_gpio_pa_pol REG_ADDR8(0x140304) 31 #define reg_gpio_pa_ds REG_ADDR8(0x140305) 32 #define reg_gpio_pa_gpio REG_ADDR8(0x140306) 33 #define reg_gpio_pa_irq_en REG_ADDR8(0x140307) 34 35 #define reg_gpio_pa_fs REG_ADDR16(0x140330) 36 #define reg_gpio_pa_fuc_l REG_ADDR8(0x140330) 37 #define reg_gpio_pa_fuc_h REG_ADDR8(0x140331) 38 39 // PB 40 #define reg_gpio_pb_setting1 REG_ADDR32(0x140308) 41 #define reg_gpio_pb_in REG_ADDR8(0x140308) 42 #define reg_gpio_pb_ie REG_ADDR8(0x140309) 43 #define reg_gpio_pb_oen REG_ADDR8(0x14030a) 44 #define reg_gpio_pb_out REG_ADDR8(0x14030b) 45 46 #define reg_gpio_pb_setting2 REG_ADDR32(0x14030c) 47 #define reg_gpio_pb_pol REG_ADDR8(0x14030c) 48 #define reg_gpio_pb_ds REG_ADDR8(0x14030d) 49 #define reg_gpio_pb_gpio REG_ADDR8(0x14030e) 50 #define reg_gpio_pb_irq_en REG_ADDR8(0x14030f) 51 52 #define reg_gpio_pb_fs REG_ADDR16(0x140332) 53 #define reg_gpio_pb_fuc_l REG_ADDR8(0x140332) 54 #define reg_gpio_pb_fuc_h REG_ADDR8(0x140333) 55 56 // PC 57 #define reg_gpio_pc_setting1 REG_ADDR32(0x140310) 58 #define reg_gpio_pc_in REG_ADDR8(0x140310) 59 #define areg_gpio_pc_ie 0xbd 60 #define areg_gpio_pc_pe 0xbe 61 #define reg_gpio_pc_oen REG_ADDR8(0x140312) 62 #define reg_gpio_pc_out REG_ADDR8(0x140313) 63 64 #define reg_gpio_pc_setting2 REG_ADDR32(0x140314) 65 #define reg_gpio_pc_pol REG_ADDR8(0x140314) 66 #define areg_gpio_pc_ds 0xbf 67 #define reg_gpio_pc_gpio REG_ADDR8(0x140316) 68 #define reg_gpio_pc_irq_en REG_ADDR8(0x140317) 69 70 #define reg_gpio_pc_fs REG_ADDR16(0x140334) 71 #define reg_gpio_pc_fuc_l REG_ADDR8(0x140334) 72 #define reg_gpio_pc_fuc_h REG_ADDR8(0x140335) 73 74 // PD 75 #define reg_gpio_pd_setting1 REG_ADDR32(0x140318) 76 #define reg_gpio_pd_in REG_ADDR8(0x140318) 77 #define areg_gpio_pd_ie 0xc0 78 #define areg_gpio_pd_pe 0xc1 79 #define reg_gpio_pd_oen REG_ADDR8(0x14031a) 80 #define reg_gpio_pd_out REG_ADDR8(0x14031b) 81 82 #define reg_gpio_pd_setting2 REG_ADDR32(0x14031c) 83 #define reg_gpio_pd_pol REG_ADDR8(0x14031c) 84 #define areg_gpio_pd_ds 0xc2 85 #define reg_gpio_pd_gpio REG_ADDR8(0x14031e) 86 #define reg_gpio_pd_irq_en REG_ADDR8(0x14031f) 87 88 #define reg_gpio_pd_fs REG_ADDR16(0x140336) 89 #define reg_gpio_pd_fuc_l REG_ADDR8(0x140336) // default 0xf0 90 #define reg_gpio_pd_fuc_h REG_ADDR8(0x140337) 91 92 // PE 93 #define reg_gpio_pe_setting1 REG_ADDR32(0x140320) 94 #define reg_gpio_pe_in REG_ADDR8(0x140320) 95 #define reg_gpio_pe_ie REG_ADDR8(0x140321) 96 #define reg_gpio_pe_oen REG_ADDR8(0x140322) 97 #define reg_gpio_pe_out REG_ADDR8(0x140323) 98 99 #define reg_gpio_pe_setting2 REG_ADDR32(0x140324) 100 #define reg_gpio_pe_pol REG_ADDR8(0x140324) 101 #define reg_gpio_pe_ds REG_ADDR8(0x140325) 102 #define reg_gpio_pe_gpio REG_ADDR8(0x140326) 103 #define reg_gpio_pe_irq_en REG_ADDR8(0x140327) 104 105 #define reg_gpio_pe_fs REG_ADDR16(0x140350) 106 #define reg_gpio_pe_fuc_l REG_ADDR8(0x140350) 107 #define reg_gpio_pe_fuc_h REG_ADDR8(0x140351) 108 109 // PF 110 #define reg_gpio_pf_setting1 REG_ADDR32(0x140328) 111 #define reg_gpio_pf_in REG_ADDR8(0x140328) 112 #define reg_gpio_pf_ie REG_ADDR8(0x140329) 113 #define reg_gpio_pf_oen REG_ADDR8(0x14032a) 114 #define reg_gpio_pf_out REG_ADDR8(0x14032b) 115 116 #define reg_gpio_pf_setting2 REG_ADDR32(0x14032c) 117 #define reg_gpio_pf_ds REG_ADDR8(0x14032d) 118 #define reg_gpio_pf_gpio REG_ADDR8(0x14032e) 119 120 #define reg_gpio_pf_fs REG_ADDR16(0x140356) 121 #define reg_gpio_pf_fuc_l REG_ADDR8(0x140356) 122 #define reg_gpio_pf_fuc_h REG_ADDR8(0x140357) 123 124 #define reg_gpio_in(i) REG_ADDR8(0x140300 + (((i) >> 8) << 3)) 125 #define reg_gpio_ie(i) REG_ADDR8(0x140301 + (((i) >> 8) << 3)) 126 #define reg_gpio_oen(i) REG_ADDR8(0x140302 + (((i) >> 8) << 3)) 127 #define reg_gpio_out(i) REG_ADDR8(0x140303 + (((i) >> 8) << 3)) 128 #define reg_gpio_pol(i) REG_ADDR8(0x140304 + (((i) >> 8) << 3)) 129 #define reg_gpio_ds(i) REG_ADDR8(0x140305 + (((i) >> 8) << 3)) 130 131 #define reg_gpio_func(i) REG_ADDR8(0x140306 + (((i) >> 8) << 3)) 132 #define reg_gpio_irq_en(i) REG_ADDR8(0x140307 + (((i) >> 8) << 3)) // reg_irq_mask: FLD_IRQ_GPIO_EN 133 #define reg_gpio_irq_risc0_en(i) REG_ADDR8(0x140338 + ((i) >> 8)) // reg_irq_mask: FLD_IRQ_GPIO_RISC0_EN 134 #define reg_gpio_irq_risc1_en(i) REG_ADDR8(0x140340 + ((i) >> 8)) // reg_irq_mask: FLD_IRQ_GPIO_RISC1_EN 135 136 #define reg_gpio_func_mux(i) REG_ADDR8(0x140330 + ((((i) >> 8) > 3) ? 0x20 : (((i) >> 8) << 1)) + (((i) & 0x0f0) ? 1 : 0)) 137 138 #define reg_gpio_irq_risc_mask REG_ADDR8(0x140352) 139 enum { 140 FLD_GPIO_IRQ_MASK_GPIO = BIT(0), 141 FLD_GPIO_IRQ_MASK_GPIO2RISC0 = BIT(1), 142 FLD_GPIO_IRQ_MASK_GPIO2RISC1 = BIT(2), 143 144 FLD_GPIO_IRQ_LVL_GPIO = BIT(4), 145 FLD_GPIO_IRQ_LVL_GPIO2RISC0 = BIT(5), 146 FLD_GPIO_IRQ_LVL_GPIO2RISC1 = BIT(6), 147 }; 148 #define reg_gpio_irq_ctrl REG_ADDR8(0x140353) 149 enum { 150 FLD_GPIO_CORE_WAKEUP_EN = BIT(2), 151 FLD_GPIO_CORE_INTERRUPT_EN = BIT(3), 152 }; 153 #define reg_gpio_pad_mul_sel REG_ADDR8(0x140355) 154 155 #define reg_gpio_irq_clr REG_ADDR8(0x140358) 156 typedef enum { 157 FLD_GPIO_IRQ_CLR = BIT(0), 158 FLD_GPIO_IRQ_GPIO2RISC0_CLR = BIT(1), 159 FLD_GPIO_IRQ_GPIO2RISC1_CLR = BIT(2), 160 } gpio_irq_status_e; 161 162 #endif 163