1 // Copyright 2018 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #include "soc/gpio_periph.h" 16 17 const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = { 18 IO_MUX_GPIO0_REG, 19 IO_MUX_GPIO1_REG, 20 IO_MUX_GPIO2_REG, 21 IO_MUX_GPIO3_REG, 22 IO_MUX_GPIO4_REG, 23 IO_MUX_GPIO5_REG, 24 IO_MUX_GPIO6_REG, 25 IO_MUX_GPIO7_REG, 26 IO_MUX_GPIO8_REG, 27 IO_MUX_GPIO9_REG, 28 IO_MUX_GPIO10_REG, 29 IO_MUX_GPIO11_REG, 30 IO_MUX_GPIO12_REG, 31 IO_MUX_GPIO13_REG, 32 IO_MUX_GPIO14_REG, 33 IO_MUX_GPIO15_REG, 34 IO_MUX_GPIO16_REG, 35 IO_MUX_GPIO17_REG, 36 IO_MUX_GPIO18_REG, 37 IO_MUX_GPIO19_REG, 38 0, 39 IO_MUX_GPIO21_REG, 40 IO_MUX_GPIO22_REG, 41 IO_MUX_GPIO23_REG, 42 0, 43 IO_MUX_GPIO25_REG, 44 IO_MUX_GPIO26_REG, 45 IO_MUX_GPIO27_REG, 46 0, 47 0, 48 0, 49 0, 50 IO_MUX_GPIO32_REG, 51 IO_MUX_GPIO33_REG, 52 IO_MUX_GPIO34_REG, 53 IO_MUX_GPIO35_REG, 54 IO_MUX_GPIO36_REG, 55 IO_MUX_GPIO37_REG, 56 IO_MUX_GPIO38_REG, 57 IO_MUX_GPIO39_REG, 58 }; 59 60 const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = { 61 0, 62 BIT(1), 63 0, 64 BIT(0), 65 0, 66 BIT(8), 67 BIT(2), 68 BIT(3), 69 BIT(4), 70 BIT(5), 71 BIT(6), 72 BIT(7), 73 0, 74 0, 75 0, 76 0, 77 BIT(9), 78 BIT(10), 79 BIT(11), 80 BIT(12), 81 0, 82 BIT(14), 83 BIT(15), 84 BIT(16), 85 0, 86 0, 87 0, 88 0, 89 0, 90 0, 91 0, 92 0, 93 0, 94 0, 95 0, 96 0, 97 0, 98 0, 99 0, 100 0, 101 }; 102