1 /*
2 * hardware interfaces for XRadio drivers
3 *
4 * Copyright (c) 2013
5 * Xradio Technology Co., Ltd. <www.xradiotech.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #ifndef XRADIO_HWIO_H_INCLUDED
13 #define XRADIO_HWIO_H_INCLUDED
14
15 /* extern */ struct xradio_common;
16
17 /* DPLL initial values */
18 #define DPLL_INIT_VAL_XRADIO (0x0EC4F121)
19
20 /* Hardware Type Definitions */
21 #define HIF_HW_TYPE_XRADIO (1)
22
23 #define CHECK_ADDR_LEN 1
24
25 #define NEW_VERSION 1
26
27 /* Sdio addr is 4*spi_addr */
28 #define SPI_REG_ADDR_TO_SDIO(spi_reg_addr) ((spi_reg_addr) << 2)
29 #define SDIO_ADDR17BIT(buf_id, mpf, rfu, reg_id_ofs) \
30 ((((buf_id) & 0x1F) << 7) \
31 | (((mpf) & 1) << 6) \
32 | (((rfu) & 1) << 5) \
33 | (((reg_id_ofs) & 0x1F) << 0))
34 #define MAX_RETRY 3
35
36 /* boot loader start address in SRAM */
37 #define DOWNLOAD_BOOT_LOADER_OFFSET (0x00000000)
38 /* 32K, 0x4000 to 0xDFFF */
39 #define DOWNLOAD_FIFO_OFFSET (0x00004000)
40 /* 32K */
41 #define DOWNLOAD_FIFO_SIZE (0x00008000)
42 /* 128 bytes, 0xFF80 to 0xFFFF */
43 #define DOWNLOAD_CTRL_OFFSET (0x0000FF80)
44 #define DOWNLOAD_CTRL_DATA_DWORDS (32-6)
45
46 /* Download control area */
47 struct download_cntl_t {
48 /* size of whole firmware file (including Cheksum), host init */
49 u32 ImageSize;
50 /* downloading flags */
51 u32 Flags;
52 /* No. of bytes put into the download, init & updated by host */
53 u32 Put;
54 /* last traced program counter, last ARM reg_pc */
55 u32 TracePc;
56 /* No. of bytes read from the download, host init, device updates */
57 u32 Get;
58 /* r0, boot losader status, host init to pending, device updates */
59 u32 Status;
60 /* Extra debug info, r1 to r14 if status=r0=DOWNLOAD_EXCEPTION */
61 u32 DebugData[DOWNLOAD_CTRL_DATA_DWORDS];
62 };
63
64 #define DOWNLOAD_IMAGE_SIZE_REG \
65 (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, ImageSize))
66 #define DOWNLOAD_FLAGS_REG \
67 (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, Flags))
68 #define DOWNLOAD_PUT_REG \
69 (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, Put))
70 #define DOWNLOAD_TRACE_PC_REG \
71 (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, TracePc))
72 #define DOWNLOAD_GET_REG \
73 (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, Get))
74 #define DOWNLOAD_STATUS_REG \
75 (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, Status))
76 #define DOWNLOAD_DEBUG_DATA_REG \
77 (DOWNLOAD_CTRL_OFFSET + offsetof(struct download_cntl_t, DebugData))
78
79 #define DOWNLOAD_DEBUG_DATA_LEN (108)
80 #define DOWNLOAD_BLOCK_SIZE (1024)
81
82 /* For boot loader detection */
83 #define DOWNLOAD_ARE_YOU_HERE (0x87654321)
84 #define DOWNLOAD_I_AM_HERE (0x12345678)
85
86 /* Download error code */
87 #define DOWNLOAD_PENDING (0xFFFFFFFF)
88 #define DOWNLOAD_SUCCESS (0)
89 #define DOWNLOAD_EXCEPTION (1)
90 #define DOWNLOAD_ERR_MEM_1 (2)
91 #define DOWNLOAD_ERR_MEM_2 (3)
92 #define DOWNLOAD_ERR_SOFTWARE (4)
93 #define DOWNLOAD_ERR_FILE_SIZE (5)
94 #define DOWNLOAD_ERR_CHECKSUM (6)
95 #define DOWNLOAD_ERR_OVERFLOW (7)
96 #define DOWNLOAD_ERR_IMAGE (8)
97 #define DOWNLOAD_ERR_HOST (9)
98 #define DOWNLOAD_ERR_ABORT (10)
99
100 #define SYS_BASE_ADDR_SILICON (0)
101 #define AHB_MEMORY_ADDRESS (SYS_BASE_ADDR_SILICON + 0x08000000)
102 #define PAC_BASE_ADDRESS_SILICON (SYS_BASE_ADDR_SILICON + 0x09000000)
103 #define PAC_BASE_ADDRESS_SILICON (SYS_BASE_ADDR_SILICON + 0x09000000)
104 #define PAC_SHARED_MEMORY_SILICON (PAC_BASE_ADDRESS_SILICON)
105 #define APB_ADDR(addr) (PAC_SHARED_MEMORY_SILICON + (addr))
106
107 #if (NEW_VERSION)
108 #define PWRCTRL_WLAN_ADDRESS (SYS_BASE_ADDR_SILICON + 0x0AC80000)
109 #define PWRCTRL_WLAN_START_CFG (PWRCTRL_WLAN_ADDRESS + 0x18)
110 #define PWRCTRL_WLAN_COMMON_CFG (PWRCTRL_WLAN_ADDRESS + 0x178)
111 #define PWRCTRL_COMMON_REG_DONE (0x1)
112 #define PWRCTRL_COMMON_REG_BT (0x4)
113 #define PWRCTRL_COMMON_REG_ARBT (0x8)
114 #define PWRCTRL_WLAN_DPLL_CTRL (PWRCTRL_WLAN_ADDRESS + 0x154)
115
116 #else
117 #define PWRCTRL_WLAN_ADDRESS (SYS_BASE_ADDR_SILICON + 0x0AC80000)
118 #define PWRCTRL_WLAN_START_CFG (PWRCTRL_WLAN_ADDRESS + 0x18)
119 #define PWRCTRL_WLAN_COMMON_CFG (PWRCTRL_WLAN_ADDRESS + 0x78)
120 #define PWRCTRL_COMMON_REG_DONE (0x1)
121 #define PWRCTRL_COMMON_REG_BT (0x4)
122 #define PWRCTRL_COMMON_REG_ARBT (0x8)
123 #define PWRCTRL_WLAN_DPLL_CTRL (PWRCTRL_WLAN_ADDRESS + 0x54)
124 #endif
125
126
127 /* ***************************************************************
128 *Device register definitions
129 *************************************************************** */
130 /* WBF - SPI Register Addresses */
131 #define HIF_ADDR_ID_BASE (0x0000)
132 /* 16/32 bits */
133 #define HIF_CONFIG_REG_ID (0x0000)
134 /* 16/32 bits */
135 #define HIF_CONTROL_REG_ID (0x0001)
136 /* 16 bits, Q mode W/R */
137 #define HIF_IN_OUT_QUEUE_REG_ID (0x0002)
138 /* 32 bits, AHB bus R/W */
139 #define HIF_AHB_DPORT_REG_ID (0x0003)
140 /* 16/32 bits */
141 #define HIF_SRAM_BASE_ADDR_REG_ID (0x0004)
142 /* 32 bits, APB bus R/W */
143 #define HIF_SRAM_DPORT_REG_ID (0x0005)
144 /* 32 bits, t_settle/general */
145 #define HIF_TSET_GEN_R_W_REG_ID (0x0006)
146 /* 16 bits, Q mode read, no length */
147 #define HIF_FRAME_OUT_REG_ID (0x0007)
148 #define HIF_ADDR_ID_MAX (HIF_FRAME_OUT_REG_ID)
149
150 /* WBF - Control register bit set */
151 /* next o/p length, bit 11 to 0 */
152 #define HIF_CTRL_NEXT_LEN_MASK (0x0FFF)
153 #define HIF_CTRL_WUP_BIT (BIT(12))
154 #define HIF_CTRL_RDY_BIT (BIT(13))
155 #define HIF_CTRL_IRQ_ENABLE (BIT(14))
156 #define HIF_CTRL_RDY_ENABLE (BIT(15))
157 #define HIF_CTRL_IRQ_RDY_ENABLE (BIT(14)|BIT(15))
158
159 /* SPI Config register bit set */
160 #define HIF_CONFIG_FRAME_BIT (BIT(2))
161 #define HIF_CONFIG_WORD_MODE_BITS (BIT(3)|BIT(4))
162 #define HIF_CONFIG_WORD_MODE_1 (BIT(3))
163 #define HIF_CONFIG_WORD_MODE_2 (BIT(4))
164 #define HIF_CONFIG_ERROR_0_BIT (BIT(5))
165 #define HIF_CONFIG_ERROR_1_BIT (BIT(6))
166 #define HIF_CONFIG_ERROR_2_BIT (BIT(7))
167 /* TBD: Sure??? */
168 #define HIF_CONFIG_CSN_FRAME_BIT (BIT(7))
169 #define HIF_CONFIG_ERROR_3_BIT (BIT(8))
170 #define HIF_CONFIG_ERROR_4_BIT (BIT(9))
171 /* QueueM */
172 #define HIF_CONFIG_ACCESS_MODE_BIT (BIT(10))
173 /* AHB bus */
174 #define HIF_CONFIG_AHB_PFETCH_BIT (BIT(11))
175 #define HIF_CONFIG_CPU_CLK_DIS_BIT (BIT(12))
176 /* APB bus */
177 #define HIF_CONFIG_PFETCH_BIT (BIT(13))
178 /* cpu reset */
179 #define HIF_CONFIG_CPU_RESET_BIT (BIT(14))
180 #define HIF_CONFIG_CLEAR_INT_BIT (BIT(15))
181
182 /* For XRADIO the IRQ Enable and Ready Bits are in CONFIG register */
183 #define HIF_CONF_IRQ_RDY_ENABLE (BIT(16)|BIT(17))
184
185 int xradio_data_read(struct xradio_common *hw_priv, void *buf,
186 size_t buf_len);
187 int xradio_data_write(struct xradio_common *hw_priv, const void *buf,
188 size_t buf_len);
189 int xradio_reg_read(struct xradio_common *hw_priv, u16 addr, void *buf,
190 size_t buf_len);
191 int xradio_reg_write(struct xradio_common *hw_priv, u16 addr,
192 const void *buf, size_t buf_len);
193 int xradio_reg_bit_operate(struct xradio_common *hw_priv, u16 addr, u32 set, u32 clr);
194 int xradio_indirect_read(struct xradio_common *hw_priv, u32 addr, void *buf,
195 size_t buf_len, u32 prefetch, u16 port_addr);
196 int xradio_apb_write(struct xradio_common *hw_priv, u32 addr,
197 const void *buf, size_t buf_len);
198 int xradio_ahb_write(struct xradio_common *hw_priv, u32 addr,
199 const void *buf, size_t buf_len);
200
201
xradio_reg_read_16(struct xradio_common * hw_priv,u16 addr,u16 * val)202 static inline int xradio_reg_read_16(struct xradio_common *hw_priv,
203 u16 addr, u16 *val)
204 {
205 int ret = 0;
206 u32 bigVal = 0;
207 ret = xradio_reg_read(hw_priv, addr, &bigVal, sizeof(bigVal));
208 *val = (u16)bigVal;
209 return ret;
210 }
211
xradio_reg_write_16(struct xradio_common * hw_priv,u16 addr,u16 val)212 static inline int xradio_reg_write_16(struct xradio_common *hw_priv,
213 u16 addr, u16 val)
214 {
215 u32 bigVal = (u32)val;
216 return xradio_reg_write(hw_priv, addr, &bigVal, sizeof(bigVal));
217 }
218
xradio_reg_read_32(struct xradio_common * hw_priv,u16 addr,u32 * val)219 static inline int xradio_reg_read_32(struct xradio_common *hw_priv,
220 u16 addr, u32 *val)
221 {
222 return xradio_reg_read(hw_priv, addr, val, sizeof(*val));
223 }
224
xradio_reg_write_32(struct xradio_common * hw_priv,u16 addr,u32 val)225 static inline int xradio_reg_write_32(struct xradio_common *hw_priv,
226 u16 addr, u32 val)
227 {
228 return xradio_reg_write(hw_priv, addr, &val, sizeof(val));
229 }
230
xradio_apb_read(struct xradio_common * hw_priv,u32 addr,void * buf,size_t buf_len)231 static inline int xradio_apb_read(struct xradio_common *hw_priv, u32 addr,
232 void *buf, size_t buf_len)
233 {
234 return xradio_indirect_read(hw_priv, addr, buf, buf_len,
235 HIF_CONFIG_PFETCH_BIT,
236 HIF_SRAM_DPORT_REG_ID);
237 }
238
xradio_ahb_read(struct xradio_common * hw_priv,u32 addr,void * buf,size_t buf_len)239 static inline int xradio_ahb_read(struct xradio_common *hw_priv, u32 addr,
240 void *buf, size_t buf_len)
241 {
242 return xradio_indirect_read(hw_priv, addr, buf, buf_len,
243 HIF_CONFIG_AHB_PFETCH_BIT,
244 HIF_AHB_DPORT_REG_ID);
245 }
246
xradio_apb_read_32(struct xradio_common * hw_priv,u32 addr,u32 * val)247 static inline int xradio_apb_read_32(struct xradio_common *hw_priv,
248 u32 addr, u32 *val)
249 {
250 return xradio_apb_read(hw_priv, addr, val, sizeof(*val));
251 }
252
xradio_apb_write_32(struct xradio_common * hw_priv,u32 addr,u32 val)253 static inline int xradio_apb_write_32(struct xradio_common *hw_priv,
254 u32 addr, u32 val)
255 {
256 return xradio_apb_write(hw_priv, addr, &val, sizeof(val));
257 }
258
xradio_ahb_read_32(struct xradio_common * hw_priv,u32 addr,u32 * val)259 static inline int xradio_ahb_read_32(struct xradio_common *hw_priv,
260 u32 addr, u32 *val)
261 {
262 return xradio_ahb_read(hw_priv, addr, val, sizeof(*val));
263 }
264
xradio_ahb_write_32(struct xradio_common * hw_priv,u32 addr,u32 val)265 static inline int xradio_ahb_write_32(struct xradio_common *hw_priv,
266 u32 addr, u32 val)
267 {
268 return xradio_ahb_write(hw_priv, addr, &val, sizeof(val));
269 }
270
xradio_dllctrl_convert(u32 dpll)271 static inline u32 xradio_dllctrl_convert(u32 dpll)
272 {
273 return ((((dpll>>31)&0x1) << 0) | /*config*/
274 (((dpll>>29)&0x3) << 1) | /*dither*/
275 (((dpll>>12)&0x1) << 3) | /*frac ctrl*/
276 (((dpll>>13)&0xffff) << 4) | /*frac*/
277 (((dpll>>4)&0xff) << 20)); /*divn*/
278 }
279
280 #endif /* XRADIO_HWIO_H_INCLUDED */
281