1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef HIMCI_H 17 #define HIMCI_H 18 19 #include "asm/dma.h" 20 #include "asm/io.h" 21 #include "asm/platform.h" 22 #include "device_resource_if.h" 23 #include "linux/scatterlist.h" 24 #include "los_event.h" 25 #include "los_vm_iomap.h" 26 #include "los_vm_zone.h" 27 #include "mmc_corex.h" 28 #include "osal_io.h" 29 #include "osal_irq.h" 30 #include "osal_time.h" 31 32 #ifdef __cplusplus 33 #if __cplusplus 34 extern "C" { 35 #endif /* __cplusplus */ 36 #endif /* __cplusplus */ 37 38 #define HIMCI_MAX_RETRY_COUNT 100 39 #define HIMCI_PAGE_SIZE 4096 40 #define HIMCI_DMA_MAX_BUFF_SIZE 0x1000 41 42 #define HIMCI_MMC_FREQ_150M 150000000 43 #define HIMCI_MMC_FREQ_100M 100000000 44 #define HIMCI_MMC_FREQ_50M 50000000 45 #define HIMCI_MMC_FREQ_25M 25000000 46 47 /* register mapping */ 48 #define PERI_CRG49 (CRG_REG_BASE + 0xC4) 49 #define PERI_CRG50 (CRG_REG_BASE + 0xC8) 50 #define PERI_CRG82 (CRG_REG_BASE + 0x0148) 51 #define PERI_CRG83 (CRG_REG_BASE + 0x014C) 52 #define PERI_CRG84 (CRG_REG_BASE + 0x0150) 53 #define PERI_CRG85 (CRG_REG_BASE + 0x0154) 54 #define PERI_CRG86 (CRG_REG_BASE + 0x0158) 55 #define PERI_CRG87 (CRG_REG_BASE + 0x015C) 56 #define PERI_CRG88 (CRG_REG_BASE + 0x0160) 57 #define PERI_CRG89 (CRG_REG_BASE + 0x0164) 58 #define PERI_CRG90 (CRG_REG_BASE + 0x0168) 59 60 /* 61 * PERI_CRG82/PERI_CRG88/PERI_CRG85 details. 62 * [3:2]Working clock selection. 01: 100MHz; 10: 50MHz; 11: 25MHz. 63 * [1]Clock gating. 0: disabled; 1: enabled. 64 * [0]Soft reset request. 0: reset deasserted; 1: reset. 65 */ 66 #define HIMCI_CLK_SEL_MASK (3U << 2) 67 #define HIMCI_CLK_SEL_100M (1U << 2) 68 #define HIMCI_CLK_SEL_50M (2U << 2) 69 #define HIMCI_CLK_SEL_25M (3U << 2) 70 #define HIMCI_CKEN (1U << 1) 71 #define HIMCI_RESET (1U << 0) 72 73 /* 74 * PERI_CRG83/PERI_CRG89/PERI_CRG86 details. 75 * [19]SAP_DLL device delay line enable. 0: The device stops working. 1: The device starts to work. 76 * [18]SAP_DLL host calculation clock cycle disable signal. 0: enabled; 1: Disable clock detection. 77 * [17]SAP_DLL device LINE bypass. 0: normal mode; 1: device line bypass. 78 * [16]SAP_DLL mode select. 0: normal mode; 1: The device line is controlled by the SAP_DLL_dllssel. 79 * [15:8]SAP_DLL device LINE delay level select, valid when SAP_DLL_dllmode is high. 80 * [7:4]SAP_DLL device tap calibration. 81 * [1]SAP_DLL soft reset. 0: reset deasserted; 1: reset. [0]SAP_DLL clock gating. 0: disabled; 1: enabled. 82 */ 83 #define HIMCI_SAP_DLL_DEVICE_DELAY_ENABLE (1U << 19) 84 #define HIMCI_SAP_DLL_MODE_DLLSSEL (1U << 16) 85 #define HIMCI_SAP_DLL_SOFT_RESET (1U << 0) 86 #define HIMCI_SAP_DLL_ELEMENT_SHIFT 8 87 88 /* HI MCI CONFIGS */ 89 #define HIMCI_REQUEST_TIMEOUT (10 * LOSCFG_BASE_CORE_TICK_PER_SECOND) /* 10s */ 90 #define HIMCI_TUNINT_REQ_TIMEOUT (LOSCFG_BASE_CORE_TICK_PER_SECOND / 5) /* 0.2s */ 91 #define HIMCI_CARD_COMPLETE_TIMEOUT (5 * LOSCFG_BASE_CORE_TICK_PER_SECOND) /* 5s */ 92 93 #define HIMCI_READL(addr) OSAL_READL((uintptr_t)(addr)) 94 95 #define HIMCI_WRITEL(v, addr) OSAL_WRITEL((v), (uintptr_t)(addr)) 96 97 #define HIMCI_CLEARL(host, reg, v) OSAL_WRITEL(OSAL_READL((uintptr_t)(host)->base + (reg)) & (~(v)), \ 98 (uintptr_t)(host)->base + (reg)); 99 100 #define HIMCI_SETL(host, reg, v) OSAL_WRITEL(OSAL_READL((uintptr_t)(host)->base + (reg)) | (v), \ 101 (uintptr_t)(host)->base + (reg)); 102 103 /* define event lock */ 104 typedef EVENT_CB_S HIMCI_EVENT; 105 #define HIMCI_EVENT_INIT(event) LOS_EventInit(event) 106 #define HIMCI_EVENT_SIGNAL(event, bit) LOS_EventWrite(event, bit) 107 #define HIMCI_EVENT_WAIT(event, bit, timeout) LOS_EventRead(event, bit, (LOS_WAITMODE_OR + LOS_WAITMODE_CLR), timeout) 108 #define HIMCI_EVENT_DELETE(event) LOS_EventDestroy(event) 109 110 /* define task/irq lock */ 111 #define HIMCI_TASK_LOCK(lock) do { LOS_TaskLock(); } while (0) 112 #define HIMCI_TASK_UNLOCK(lock) do { LOS_TaskUnlock(); } while (0) 113 #define HIMCI_IRQ_LOCK(flags) do { (*(flags)) = LOS_IntLock(); } while (0) 114 #define HIMCI_IRQ_UNLOCK(flags) do { LOS_IntRestore(flags); } while (0) 115 116 #define HIMCI_SG_DMA_ADDRESS(sg) ((sg)->dma_address) 117 #ifdef CONFIG_NEED_SG_DMA_LENGTH 118 #define HIMCI_SG_DMA_LEN(sg) ((sg)->dma_length) 119 #else 120 #define HIMCI_SG_DMA_LEN(sg) ((sg)->length) 121 #endif 122 123 #define REG_CTRL_NUM 4 124 #define REG_CTRL_EMMC_START IO_DEVICE_ADDR(0x10ff0000 + 0x0) /* eMMC pad ctrl reg */ 125 #define REG_CTRL_SD_START IO_DEVICE_ADDR(0x10ff0000 + 0x24) /* sd pad ctrl reg */ 126 #define REG_CTRL_SDIO_START IO_DEVICE_ADDR(0x112f0000 + 0x8) /* sdio pad ctrl reg */ 127 128 enum HimciPowerStatus { 129 HOST_POWER_OFF, 130 HOST_POWER_ON, 131 }; 132 133 enum HimciDmaDataDirection { 134 DMA_BIDIRECTIONAL = 0, 135 DMA_TO_DEVICE = 1, 136 DMA_FROM_DEVICE = 2, 137 DMA_NONE = 3, 138 }; 139 140 enum HimciHostRegister { 141 MMC_CTRL = 0x0000, 142 MMC_PWREN = 0x0004, 143 MMC_CLKDIV = 0x0008, 144 MMC_CLKENA = 0x0010, 145 MMC_TMOUT = 0x0014, 146 MMC_CTYPE = 0x0018, 147 MMC_BLKSIZ = 0x001c, 148 MMC_BYTCNT = 0x0020, 149 MMC_INTMASK = 0x0024, 150 MMC_CMDARG = 0x0028, 151 MMC_CMD = 0x002C, 152 MMC_RESP0 = 0x0030, 153 MMC_RESP1 = 0x0034, 154 MMC_RESP2 = 0x0038, 155 MMC_RESP3 = 0x003C, 156 MMC_MINTSTS = 0x0040, 157 MMC_RINTSTS = 0x0044, 158 MMC_STATUS = 0x0048, 159 MMC_FIFOTH = 0x004C, 160 MMC_CDETECT = 0x0050, 161 MMC_WRTPRT = 0x0054, 162 MMC_GPIO = 0x0058, 163 MMC_TCBCNT = 0x005C, 164 MMC_TBBCNT = 0x0060, 165 MMC_DEBNCE = 0x0064, 166 MMC_UHS_REG = 0x0074, 167 MMC_CARD_RSTN = 0x0078, 168 MMC_BMOD = 0x0080, 169 MMC_DBADDR = 0x0088, 170 MMC_IDSTS = 0x008C, 171 MMC_IDINTEN = 0x0090, 172 MMC_DSCADDR = 0x0094, 173 MMC_BUFADDR = 0x0098, 174 MMC_CARDTHRCTL = 0x0100, 175 MMC_UHS_REG_EXT = 0x0108, 176 MMC_EMMC_DDR_REG = 0x010c, 177 MMC_ENABLE_SHIFT = 0x0110, 178 MMC_TUNING_CTRL = 0x0118, 179 MMC_DATA = 0x0200 180 }; 181 182 /* 183 * MMC_CTRL(0x0000) details. 184 * [25]Whether to use the built-in DMA to transfer data. 185 * 0: The CPU uses the device interface to transfer data. 1: The internal DMA is used to transfer data. 186 * [4]Global interrupt enable. 0: disabled; 1: enabled. 187 * The interrupt output is valid only when this bit is valid and an interrupt source is enabled. 188 * [2]Soft reset control for the internal DMAC. 0: invalid; 1: Reset the internal DMA interface. 189 * This bit is automatically reset after two AHB clock cycles. 190 * [1]Soft reset control for the internal FIFO. 0: invalid; 1: Reset the FIFO pointer. 191 * This bit is automatically reset after the reset operation is complete. 192 * [0]Soft reset control for the controller. 0: invalid; 1: Reset the eMMC/SD/SDIO host module. 193 */ 194 #define CTRL_RESET (1U << 0) 195 #define FIFO_RESET (1U << 1) 196 #define DMA_RESET (1U << 2) 197 #define INTR_EN (1U << 4) 198 #define USE_INTERNAL_DMA (1U << 25) 199 200 /* 201 * MMC_PWREN(0x0004) details. 202 * [0]POWER control. 0: power off; 1: The power supply is turned on. 203 */ 204 #define POWER_ENABLE (1U << 0) 205 206 /* 207 * MMC_CLKDIV(0x0008) details. 208 * [7:0]Clock divider. The clock frequency division coefficient is 2 * n. 209 * For example, 0 indicates no frequency division, 1 indicates frequency division by 2, 210 * and ff indicates frequency division by 510. 211 */ 212 #define CLK_DIVIDER (0xff * 2) 213 #define MAX_CLKDIV_VAL 0xff 214 215 /* 216 * MMC_CLKENA(0x0010) details. 217 * [16]Low-power control of the card, used to disable the card clock. 0: no low-power mode; 1: low-power mode. 218 * When the card is in the idle state, the card clock is stopped. This function applies only to the SD card and eMMC. 219 * For the SDIO, the clock cannot be stopped to detect interrupts. 220 * [0]Card clock enable. 0: disabled; 1: enabled. 221 */ 222 #define CCLK_LOW_POWER (1U << 16) 223 #define CCLK_ENABLE (1U << 0) 224 225 /* 226 * MMC_TMOUT(0x14) details. 227 * [31:8]data read timeout param. 228 * [7:0]response timeout param. 229 */ 230 #define DATA_TIMEOUT (0xffffffU << 8) 231 #define RESPONSE_TIMEOUT 0xff 232 233 /* 234 * MCI_CTYPE(0x0018) details. 235 * [16]Bus width of the card. 0: non-8-bit mode, depending on the configuration of bit[0]; 236 * 1: 8-bit mode, the value of bit[0] is ignored. 237 * [0]Bus width of the card. 0: 1-bit mode; 1: 4-bit mode. 238 */ 239 #define CARD_WIDTH_1 (1U << 0) 240 #define CARD_WIDTH_0 (1U << 16) 241 242 /* MCI_INTMASK(0x24) details. 243 * [16:0]mask MMC host controller each interrupt. 0: disable; 1: enabled. 244 * [16]SDIO interrupt; [3]data transfer over(DTO). 245 */ 246 #define ALL_INT_MASK 0x1ffff 247 #define DTO_INT_MASK (1 << 3) 248 #define SDIO_INT_MASK (1 << 16) 249 250 /* 251 * MCI_CMD(0x2c) details: 252 * [31]cmd execute or load start param of interface clk bit. 253 */ 254 #define START_CMD (1U << 31) 255 256 /* 257 * MCI_INTSTS(0x44) details. 258 * [16]sdio interrupt status; [15]end-bit error (read)/write no CRC interrupt status; 259 * [14]auto command done interrupt status; [13]start bit error interrupt status; 260 * [12]hardware locked write error interrupt status; [11]FIFO underrun/overrun error interrupt status; 261 * [10]data starvation-by-host timeout/volt_switch to 1.8v for sdxc interrupt status; 262 * [9]data read timeout interrupt status; [8]response timeout interrupt status; [7]data CRC error interrupt status; 263 * [6]response CRC error interrupt status; [5]receive FIFO data request interrupt status; 264 * [4]transmit FIFO data request interrupt status; [3]data transfer Over interrupt status; 265 * [2]command done interrupt status; [1]response error interrupt status; [0]card detect interrupt status. 266 */ 267 #define SDIO_INT_STATUS (1U << 16) 268 #define EBE_INT_STATUS (1U << 15) 269 #define ACD_INT_STATUS (1U << 14) 270 #define SBE_INT_STATUS (1U << 13) 271 #define HLE_INT_STATUS (1U << 12) 272 #define FRUN_INT_STATUS (1U << 11) 273 #define HTO_INT_STATUS (1U << 10) 274 #define VOLT_SWITCH_INT_STATUS (1U << 10) 275 #define DRTO_INT_STATUS (1U << 9) 276 #define RTO_INT_STATUS (1U << 8) 277 #define DCRC_INT_STATUS (1U << 7) 278 #define RCRC_INT_STATUS (1U << 6) 279 #define RXDR_INT_STATUS (1U << 5) 280 #define TXDR_INT_STATUS (1U << 4) 281 #define DTO_INT_STATUS (1U << 3) 282 #define CD_INT_STATUS (1U << 2) 283 #define RE_INT_STATUS (1U << 1) 284 #define CARD_DETECT_INT_STATUS (1U << 0) 285 #define DATA_INT_MASK (DTO_INT_STATUS | DCRC_INT_STATUS | SBE_INT_STATUS | EBE_INT_STATUS) 286 #define CMD_INT_MASK (RTO_INT_STATUS | RCRC_INT_STATUS | RE_INT_STATUS | CD_INT_STATUS | VOLT_SWITCH_INT_STATUS) 287 #define ALL_INT_CLR 0x1efff 288 289 /* 290 * MMC_STATUS(0x48) details. 291 * [9]Status of data_busy indicated by DAT[0]. 0: idle; 1: The card is busy. 292 */ 293 #define DATA_BUSY (1U << 9) 294 295 /* MMC_FIFOTH(0x4c) details. 296 * [30:28]Indicates the transmission burst length. 297 * 000: 1; 001: 4; 010: 8; 011: 16; 100: 32; 101: 64; 110: 128; 111:256. 298 * [27:16]FIFO threshold watermarklevel when data is read. 299 * When the FIFO count is greater than the value of this parameter, the DMA request is enabled. 300 * To complete the remaining data after data transfer, a DMA request is generated. 301 * [11:0]FIFO threshold watermark level when data is transmitted. 302 * When the FIFO count is less than the value of this parameter, the DMA request is enabled. 303 * To complete the remaining data after data transfer, a DMA request is generated. 304 */ 305 #define BURST_SIZE (0x6 << 28) 306 #define RX_WMARK (0x7f << 16) 307 #define TX_WMARK 0x80 308 309 /* 310 * MMC_CDETECT(0x0050) details. 311 * [0]Card detection signal. 0: The card is detected; 1: The card is not detected. 312 */ 313 #define CARD_UNPLUGED (1U << 0) 314 315 /* 316 * MMC_WRTPRT(0x0054) details. 317 * [0] 0: card read/write; 1: card readonly. 318 */ 319 #define CARD_READONLY (1U << 0) 320 321 /* 322 * MMC_GPIO(0x0058) details. 323 * [23] 0: dto fix bypass; 1: dto fix enable. 324 */ 325 #define DTO_FIX_ENABLE (1U << 23) 326 327 /* 328 * MMC_DEBNCE(0x0064) details. 329 * [23:0]Number of bus clock cycles used by the dejitter filter logic. The dejitter time is 5ms to 25ms. 330 */ 331 #define DEBNCE_MS 25 332 #define DEBOUNCE_E (DEBNCE_MS * 150000) 333 #define DEBOUNCE_H (DEBNCE_MS * 100000) 334 #define DEBOUNCE_M (DEBNCE_MS * 50000) 335 #define DEBOUNCE_L (DEBNCE_MS * 25000) 336 337 /* 338 * MMC_UHS_REG(0x0074) details. 339 * [16] DDR Mode control register, 0: non-DDR mode, 1: DDR mode. 340 * [0] Voltage mode control register, 0: 3.3V, 1: 1.8V. 341 */ 342 #define HI_SDXC_CTRL_DDR_REG (1U << 16) 343 #define HI_SDXC_CTRL_VDD_180 (1U << 0) 344 345 /* 346 * MMC_CARD_RSTN(0x0078) details. 347 * [16] eMMC reset controller. 0: reset; 1: reset deasserted. 348 */ 349 #define CARD_RESET (1U << 0) 350 351 /* MMC_BMOD(0x80) details. 352 * [10:8]Indicates the length of the IDMAC burst transmission. 353 * 000: 1; 001: 4; 010: 8; 011: 16; 100: 32; 101: 64; 110: 128; 111:256. 354 * [7]IDMAC enable. 0: disabled; 1: enabled. 355 * [1]Fixed burst length. 356 * 0: SINGLE and INCR burst types are used; 1: SINGLE, INCR4, INCR8, and INCR16 burst types are used. 357 * [0]Soft reset control for IDMAC internal registers. 0: not reset; 1: reset. 358 * This bit is automatically cleared one clock cycle after this bit is set. 359 * 360 */ 361 #define BMOD_SWR (1U << 0) 362 #define BURST_INCR (1U << 1) 363 #define BMOD_DMA_EN (1U << 7) 364 #define BURST_8 (1U << 8) 365 #define BURST_16 (3U << 8) 366 367 /* MMC_CARDTHRCTL(0x0100) details. 368 * [27:16]Read threshold. The maximum value is 512. 369 * [1]Busy clear interrupt enable. 0: disabled; 1: enabled. 370 * [0]Read threshold enable. 0: disabled; 1: enabled. 371 */ 372 #define READ_THRESHOLD_SIZE 0x2000005 373 #define BUSY_CLEAR_INT_ENABLE (1U << 1) 374 375 /* MMC_UHS_REG_EXT(0x0108) details. 376 * [25:23]Clock phase of clk_in_drv, in degrees. 377 * [18:16]Clock phase of clk_in_sample, in degrees. 378 * 000: 0; 001: 45; 010: 90; 011: 135; 100: 180; 101: 225; 110: 270; 111: 315. 379 */ 380 #define CLK_SMPL_PHS_OFFSET 16 381 #define CLK_SMPL_PHS_MASK (0x7 << CLK_SMPL_PHS_OFFSET) 382 #define CLK_DRV_PHS_OFFSET 23 383 #define CLK_DRV_PHS_MASK (0x7 << CLK_DRV_PHS_OFFSET) 384 #define DRV_PHASE_180 (0x4 << 23) 385 #define DRV_PHASE_135 (0x3 << 23) 386 #define DRV_PHASE_90 (0x2 << 23) 387 #define SMP_PHASE_45 (0x1 << 16) 388 #define SMP_PHASE_0 (0x0 << 16) 389 #define DRV_PHASE_SHIFT 0x4 390 #define SMPL_PHASE_SHIFT 0x1 391 392 #define TUNING_START_PHASE 0 393 #define TUNING_END_PHASE 7 394 #define HIMCI_PHASE_SCALE 8 395 #define DRV_PHASE_DFLT DRV_PHASE_180 396 #define SMPL_PHASE_DFLT SMP_PHASE_0 397 398 /* 399 * MMC_TUNING_CTRL(0x118) details. 400 */ 401 #define HW_TUNING_EN (1U << 0) 402 #define EDGE_CTRL (1U << 1) 403 #define FOUND_EDGE (1U << 5) 404 405 /* IDMAC DEST0 details */ 406 #define DMA_DES_OWN (1U << 31) 407 #define DMA_DES_NEXT_DES (1U << 4) 408 #define DMA_DES_FIRST_DES (1U << 3) 409 #define DMA_DES_LAST_DES (1U << 2) 410 411 /* MMC_CMD(0x002C) register bits define. */ 412 union HimciCmdRegArg { 413 uint32_t arg; 414 struct CmdBits { 415 uint32_t cmdIndex : 6; /* [5:0]Command sequence number. */ 416 uint32_t rspExpect : 1; /* 417 * Indicates whether a response exists. 418 * 0: No response is output from the card. 419 * 1: A response is output from the card. 420 */ 421 uint32_t rspLen : 1; /* 422 * Response length. 0: The short response is output from the card. 423 * 1: The long response is output from the card. 424 * The long response is 128 bits, and the short response is 32 bits. 425 */ 426 uint32_t checkRspCrc : 1; /* 427 * Indicates whether the CRC check is performed. 428 * 0: The CRC response is not checked. 1: Check the CRC response. 429 */ 430 uint32_t dataTransferExpected : 1; /* 431 * Data transfer indicator. 432 * 0: No data is output from the card. 1: Data is output from the card. 433 */ 434 uint32_t readWrite : 1; /* 435 * Read/write control. 0: Read data from the card. 1: Write data to the card. 436 * This bit is ignored in non-data transmission. 437 */ 438 uint32_t transferMode : 1; /* 439 * 0: block transfer command; 1: stream transmission command. 440 * This bit is ignored in non-data transmission. 441 */ 442 uint32_t sendAutoStop : 1; /* 443 * Indicates whether to send the stop command. 444 * 0: The stop command is not sent after the data transfer is complete. 445 * 1: The stop command is sent after data transfer is complete. 446 * This bit is ignored in non-data transmission. 447 */ 448 uint32_t waitDataComplete : 1; /* 449 * Indicates whether to send an instruction immediately. 450 * 0: Send the command immediately; 451 * 1: Send the command after the previous data transfer is complete. 452 * 0 is a typical value, which is used to read the status or interrupt the 453 * transfer during data transfer. 454 */ 455 uint32_t stopAbortCmd : 1; /* 456 * When the data transfer operation is in progress, the values are as follows: 457 * 0: The stop/abort command is not sent. 458 * 1: The stop/abort command is sent to stop the ongoing data transfer. 459 */ 460 uint32_t sendInitialization : 1; /* 461 * Indicates whether to send the initial sequence. 462 * 0: The initial sequence is not sent before the Send_initialization is sent. 463 * 1: The initial sequence is sent before the Send_initialization is sent. 464 * When the card is powered on, the initial sequence must be sent for 465 * initialization before any command is sent. That is, this bit is set to 1. 466 */ 467 uint32_t cardNumber : 5; /* Sequence number of the card in use. */ 468 uint32_t updateClkRegOnly : 1; /* 469 * Indicates whether to automatically update. 470 * 0: normal command sequence; 1: No command is sent. Only the clock register 471 * value of the card clock domain is updated. 472 * Set this bit to 1 each time the card clock is changed. In this case, 473 * no command is transmitted to the card, 474 * and no command-done interrupt is generated. 475 */ 476 uint32_t reserved1 : 2; 477 uint32_t enableBoot : 1; /* 478 * Enable the boot function. This bit can be used only in forcible boot mode. 479 * When software enables this bit and Start_cmd at the same time, 480 * the controller pulls down the CMD signal to start the boot process. 481 * Enable_boot and Disable_boot cannot be enabled at the same time. 482 */ 483 uint32_t expectBootAck : 1; /* 484 * Enables the boot response. When the software enables this bit and Enable_boot at 485 * the same time, the controller detects the boot response signal, 486 * that is, the 0-1-0 sequence. 487 */ 488 uint32_t disableBoot : 1; /* 489 * Disable the boot. When the software enables this bit and Start_cmd at the same 490 * time, the controller stops the boot operation. 491 * Enable_boot and Disable_boot cannot be enabled at the same time. 492 */ 493 uint32_t bootMode : 1; /* Boot mode. 0: forcible boot mode; 1: alternate boot mode. */ 494 uint32_t voltSwitch : 1; /* Voltage switching control. 0: The voltage switching is disabled. 1: enabled. */ 495 uint32_t useHoldReg : 1; /* 496 * 0: The CMD and DATA signals sent to the card do not pass through the HOLD register. 497 * 1: The CMD and DATA signals sent to the card pass through the HOLD register. 498 */ 499 uint32_t reserved2 : 1; 500 uint32_t startCmd : 1; /* 501 * Start control. 0: not enabled; 1: start command. 502 * This bit is cleared when the command has been sent to the CIU. 503 * The CPU cannot modify this register. 504 * If the value is changed, a hardware lock error interrupt is generated. 505 * After sending a command, the CPU needs to query this bit. 506 * After the bit becomes 0, the CPU sends the next command. 507 */ 508 } bits; 509 }; 510 511 struct HimciDes { 512 unsigned long dmaDesCtrl; 513 unsigned long dmaDesBufSize; 514 unsigned long dmaDesBufAddr; 515 unsigned long dmaDesNextAddr; 516 }; 517 518 #define HIMCI_PEND_DTO_M (1U << 0) 519 #define HIMCI_PEND_ACCIDENT (1U << 1) 520 #define HIMCI_HOST_INIT_DONE (1U << 2) 521 struct HimciHost { 522 struct MmcCntlr *mmc; 523 struct MmcCmd *cmd; 524 void *base; 525 enum HimciPowerStatus powerStatus; 526 uint8_t *alignedBuff; 527 uint32_t buffLen; 528 struct scatterlist dmaSg; 529 struct scatterlist *sg; 530 uint32_t dmaSgNum; 531 DMA_ADDR_T dmaPaddr; 532 uint32_t *dmaVaddr; 533 uint32_t irqNum; 534 bool isTuning; 535 uint32_t id; 536 struct OsalMutex mutex; 537 bool waitForEvent; 538 HIMCI_EVENT himciEvent; 539 }; 540 541 struct HimciTuneParam { 542 uint32_t cmdCode; 543 uint32_t edgeP2f; 544 uint32_t edgeF2p; 545 uint32_t startp; 546 uint32_t endp; 547 uint32_t endpInit; 548 }; 549 550 #ifdef __cplusplus 551 #if __cplusplus 552 } 553 #endif /* __cplusplus */ 554 #endif /* __cplusplus */ 555 556 #endif /* HIMCI_H */ 557