1 /*
2 * Copyright 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file
26 * @brief Intel Surface Layout
27 *
28 * Header Layout
29 * -------------
30 * The header is ordered as:
31 * - forward declarations
32 * - macros that may be overridden at compile-time for specific gens
33 * - enums and constants
34 * - structs and unions
35 * - functions
36 */
37
38 #ifndef ISL_H
39 #define ISL_H
40
41 #include <assert.h>
42 #include <stdbool.h>
43 #include <stdint.h>
44
45 #include "util/compiler.h"
46 #include "util/macros.h"
47 #include "util/format/u_format.h"
48
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52
53 struct intel_device_info;
54 struct brw_image_param;
55
56 #ifndef ISL_GFX_VER
57 /**
58 * @brief Get the hardware generation of isl_device.
59 *
60 * You can define this as a compile-time constant in the CFLAGS. For example,
61 * `gcc -DISL_GFX_VER(dev)=9 ...`.
62 */
63 #define ISL_GFX_VER(__dev) ((__dev)->info->ver)
64 #define ISL_GFX_VERX10(__dev) ((__dev)->info->verx10)
65 #define ISL_GFX_VER_SANITIZE(__dev)
66 #else
67 #define ISL_GFX_VER_SANITIZE(__dev) \
68 (assert(ISL_GFX_VER(__dev) == (__dev)->info->ver) && \
69 ISL_GFX_VERX10(__dev) == (__dev)->info->verx10))
70 #endif
71
72 #ifndef ISL_DEV_IS_G4X
73 #define ISL_DEV_IS_G4X(__dev) ((__dev)->info->platform == INTEL_PLATFORM_G4X)
74 #endif
75
76 #ifndef ISL_DEV_IS_HASWELL
77 /**
78 * @brief Get the hardware generation of isl_device.
79 *
80 * You can define this as a compile-time constant in the CFLAGS. For example,
81 * `gcc -DISL_GFX_VER(dev)=9 ...`.
82 */
83 #define ISL_DEV_IS_HASWELL(__dev) ((__dev)->info->platform == INTEL_PLATFORM_HSW)
84 #endif
85
86 #ifndef ISL_DEV_IS_BAYTRAIL
87 #define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->platform == INTEL_PLATFORM_BYT)
88 #endif
89
90 #ifndef ISL_DEV_USE_SEPARATE_STENCIL
91 /**
92 * You can define this as a compile-time constant in the CFLAGS. For example,
93 * `gcc -DISL_DEV_USE_SEPARATE_STENCIL(dev)=1 ...`.
94 */
95 #define ISL_DEV_USE_SEPARATE_STENCIL(__dev) ((__dev)->use_separate_stencil)
96 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev)
97 #else
98 #define ISL_DEV_USE_SEPARATE_STENCIL_SANITIZE(__dev) \
99 (assert(ISL_DEV_USE_SEPARATE_STENCIL(__dev) == (__dev)->use_separate_stencil))
100 #endif
101
102 /**
103 * Hardware enumeration SURFACE_FORMAT.
104 *
105 * For the official list, see Broadwell PRM: Volume 2b: Command Reference:
106 * Enumerations: SURFACE_FORMAT.
107 */
108 enum isl_format {
109 ISL_FORMAT_R32G32B32A32_FLOAT = 0,
110 ISL_FORMAT_R32G32B32A32_SINT = 1,
111 ISL_FORMAT_R32G32B32A32_UINT = 2,
112 ISL_FORMAT_R32G32B32A32_UNORM = 3,
113 ISL_FORMAT_R32G32B32A32_SNORM = 4,
114 ISL_FORMAT_R64G64_FLOAT = 5,
115 ISL_FORMAT_R32G32B32X32_FLOAT = 6,
116 ISL_FORMAT_R32G32B32A32_SSCALED = 7,
117 ISL_FORMAT_R32G32B32A32_USCALED = 8,
118 ISL_FORMAT_R32G32B32A32_SFIXED = 32,
119 ISL_FORMAT_R64G64_PASSTHRU = 33,
120 ISL_FORMAT_R32G32B32_FLOAT = 64,
121 ISL_FORMAT_R32G32B32_SINT = 65,
122 ISL_FORMAT_R32G32B32_UINT = 66,
123 ISL_FORMAT_R32G32B32_UNORM = 67,
124 ISL_FORMAT_R32G32B32_SNORM = 68,
125 ISL_FORMAT_R32G32B32_SSCALED = 69,
126 ISL_FORMAT_R32G32B32_USCALED = 70,
127 ISL_FORMAT_R32G32B32_SFIXED = 80,
128 ISL_FORMAT_R16G16B16A16_UNORM = 128,
129 ISL_FORMAT_R16G16B16A16_SNORM = 129,
130 ISL_FORMAT_R16G16B16A16_SINT = 130,
131 ISL_FORMAT_R16G16B16A16_UINT = 131,
132 ISL_FORMAT_R16G16B16A16_FLOAT = 132,
133 ISL_FORMAT_R32G32_FLOAT = 133,
134 ISL_FORMAT_R32G32_SINT = 134,
135 ISL_FORMAT_R32G32_UINT = 135,
136 ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS = 136,
137 ISL_FORMAT_X32_TYPELESS_G8X24_UINT = 137,
138 ISL_FORMAT_L32A32_FLOAT = 138,
139 ISL_FORMAT_R32G32_UNORM = 139,
140 ISL_FORMAT_R32G32_SNORM = 140,
141 ISL_FORMAT_R64_FLOAT = 141,
142 ISL_FORMAT_R16G16B16X16_UNORM = 142,
143 ISL_FORMAT_R16G16B16X16_FLOAT = 143,
144 ISL_FORMAT_A32X32_FLOAT = 144,
145 ISL_FORMAT_L32X32_FLOAT = 145,
146 ISL_FORMAT_I32X32_FLOAT = 146,
147 ISL_FORMAT_R16G16B16A16_SSCALED = 147,
148 ISL_FORMAT_R16G16B16A16_USCALED = 148,
149 ISL_FORMAT_R32G32_SSCALED = 149,
150 ISL_FORMAT_R32G32_USCALED = 150,
151 ISL_FORMAT_R32G32_FLOAT_LD = 151,
152 ISL_FORMAT_R32G32_SFIXED = 160,
153 ISL_FORMAT_R64_PASSTHRU = 161,
154 ISL_FORMAT_B8G8R8A8_UNORM = 192,
155 ISL_FORMAT_B8G8R8A8_UNORM_SRGB = 193,
156 ISL_FORMAT_R10G10B10A2_UNORM = 194,
157 ISL_FORMAT_R10G10B10A2_UNORM_SRGB = 195,
158 ISL_FORMAT_R10G10B10A2_UINT = 196,
159 ISL_FORMAT_R10G10B10_SNORM_A2_UNORM = 197,
160 ISL_FORMAT_R8G8B8A8_UNORM = 199,
161 ISL_FORMAT_R8G8B8A8_UNORM_SRGB = 200,
162 ISL_FORMAT_R8G8B8A8_SNORM = 201,
163 ISL_FORMAT_R8G8B8A8_SINT = 202,
164 ISL_FORMAT_R8G8B8A8_UINT = 203,
165 ISL_FORMAT_R16G16_UNORM = 204,
166 ISL_FORMAT_R16G16_SNORM = 205,
167 ISL_FORMAT_R16G16_SINT = 206,
168 ISL_FORMAT_R16G16_UINT = 207,
169 ISL_FORMAT_R16G16_FLOAT = 208,
170 ISL_FORMAT_B10G10R10A2_UNORM = 209,
171 ISL_FORMAT_B10G10R10A2_UNORM_SRGB = 210,
172 ISL_FORMAT_R11G11B10_FLOAT = 211,
173 ISL_FORMAT_R10G10B10_FLOAT_A2_UNORM = 213,
174 ISL_FORMAT_R32_SINT = 214,
175 ISL_FORMAT_R32_UINT = 215,
176 ISL_FORMAT_R32_FLOAT = 216,
177 ISL_FORMAT_R24_UNORM_X8_TYPELESS = 217,
178 ISL_FORMAT_X24_TYPELESS_G8_UINT = 218,
179 ISL_FORMAT_L32_UNORM = 221,
180 ISL_FORMAT_A32_UNORM = 222,
181 ISL_FORMAT_L16A16_UNORM = 223,
182 ISL_FORMAT_I24X8_UNORM = 224,
183 ISL_FORMAT_L24X8_UNORM = 225,
184 ISL_FORMAT_A24X8_UNORM = 226,
185 ISL_FORMAT_I32_FLOAT = 227,
186 ISL_FORMAT_L32_FLOAT = 228,
187 ISL_FORMAT_A32_FLOAT = 229,
188 ISL_FORMAT_X8B8_UNORM_G8R8_SNORM = 230,
189 ISL_FORMAT_A8X8_UNORM_G8R8_SNORM = 231,
190 ISL_FORMAT_B8X8_UNORM_G8R8_SNORM = 232,
191 ISL_FORMAT_B8G8R8X8_UNORM = 233,
192 ISL_FORMAT_B8G8R8X8_UNORM_SRGB = 234,
193 ISL_FORMAT_R8G8B8X8_UNORM = 235,
194 ISL_FORMAT_R8G8B8X8_UNORM_SRGB = 236,
195 ISL_FORMAT_R9G9B9E5_SHAREDEXP = 237,
196 ISL_FORMAT_B10G10R10X2_UNORM = 238,
197 ISL_FORMAT_L16A16_FLOAT = 240,
198 ISL_FORMAT_R32_UNORM = 241,
199 ISL_FORMAT_R32_SNORM = 242,
200 ISL_FORMAT_R10G10B10X2_USCALED = 243,
201 ISL_FORMAT_R8G8B8A8_SSCALED = 244,
202 ISL_FORMAT_R8G8B8A8_USCALED = 245,
203 ISL_FORMAT_R16G16_SSCALED = 246,
204 ISL_FORMAT_R16G16_USCALED = 247,
205 ISL_FORMAT_R32_SSCALED = 248,
206 ISL_FORMAT_R32_USCALED = 249,
207 ISL_FORMAT_B5G6R5_UNORM = 256,
208 ISL_FORMAT_B5G6R5_UNORM_SRGB = 257,
209 ISL_FORMAT_B5G5R5A1_UNORM = 258,
210 ISL_FORMAT_B5G5R5A1_UNORM_SRGB = 259,
211 ISL_FORMAT_B4G4R4A4_UNORM = 260,
212 ISL_FORMAT_B4G4R4A4_UNORM_SRGB = 261,
213 ISL_FORMAT_R8G8_UNORM = 262,
214 ISL_FORMAT_R8G8_SNORM = 263,
215 ISL_FORMAT_R8G8_SINT = 264,
216 ISL_FORMAT_R8G8_UINT = 265,
217 ISL_FORMAT_R16_UNORM = 266,
218 ISL_FORMAT_R16_SNORM = 267,
219 ISL_FORMAT_R16_SINT = 268,
220 ISL_FORMAT_R16_UINT = 269,
221 ISL_FORMAT_R16_FLOAT = 270,
222 ISL_FORMAT_A8P8_UNORM_PALETTE0 = 271,
223 ISL_FORMAT_A8P8_UNORM_PALETTE1 = 272,
224 ISL_FORMAT_I16_UNORM = 273,
225 ISL_FORMAT_L16_UNORM = 274,
226 ISL_FORMAT_A16_UNORM = 275,
227 ISL_FORMAT_L8A8_UNORM = 276,
228 ISL_FORMAT_I16_FLOAT = 277,
229 ISL_FORMAT_L16_FLOAT = 278,
230 ISL_FORMAT_A16_FLOAT = 279,
231 ISL_FORMAT_L8A8_UNORM_SRGB = 280,
232 ISL_FORMAT_R5G5_SNORM_B6_UNORM = 281,
233 ISL_FORMAT_B5G5R5X1_UNORM = 282,
234 ISL_FORMAT_B5G5R5X1_UNORM_SRGB = 283,
235 ISL_FORMAT_R8G8_SSCALED = 284,
236 ISL_FORMAT_R8G8_USCALED = 285,
237 ISL_FORMAT_R16_SSCALED = 286,
238 ISL_FORMAT_R16_USCALED = 287,
239 ISL_FORMAT_P8A8_UNORM_PALETTE0 = 290,
240 ISL_FORMAT_P8A8_UNORM_PALETTE1 = 291,
241 ISL_FORMAT_A1B5G5R5_UNORM = 292,
242 ISL_FORMAT_A4B4G4R4_UNORM = 293,
243 ISL_FORMAT_L8A8_UINT = 294,
244 ISL_FORMAT_L8A8_SINT = 295,
245 ISL_FORMAT_R8_UNORM = 320,
246 ISL_FORMAT_R8_SNORM = 321,
247 ISL_FORMAT_R8_SINT = 322,
248 ISL_FORMAT_R8_UINT = 323,
249 ISL_FORMAT_A8_UNORM = 324,
250 ISL_FORMAT_I8_UNORM = 325,
251 ISL_FORMAT_L8_UNORM = 326,
252 ISL_FORMAT_P4A4_UNORM_PALETTE0 = 327,
253 ISL_FORMAT_A4P4_UNORM_PALETTE0 = 328,
254 ISL_FORMAT_R8_SSCALED = 329,
255 ISL_FORMAT_R8_USCALED = 330,
256 ISL_FORMAT_P8_UNORM_PALETTE0 = 331,
257 ISL_FORMAT_L8_UNORM_SRGB = 332,
258 ISL_FORMAT_P8_UNORM_PALETTE1 = 333,
259 ISL_FORMAT_P4A4_UNORM_PALETTE1 = 334,
260 ISL_FORMAT_A4P4_UNORM_PALETTE1 = 335,
261 ISL_FORMAT_Y8_UNORM = 336,
262 ISL_FORMAT_L8_UINT = 338,
263 ISL_FORMAT_L8_SINT = 339,
264 ISL_FORMAT_I8_UINT = 340,
265 ISL_FORMAT_I8_SINT = 341,
266 ISL_FORMAT_DXT1_RGB_SRGB = 384,
267 ISL_FORMAT_R1_UNORM = 385,
268 ISL_FORMAT_YCRCB_NORMAL = 386,
269 ISL_FORMAT_YCRCB_SWAPUVY = 387,
270 ISL_FORMAT_P2_UNORM_PALETTE0 = 388,
271 ISL_FORMAT_P2_UNORM_PALETTE1 = 389,
272 ISL_FORMAT_BC1_UNORM = 390,
273 ISL_FORMAT_BC2_UNORM = 391,
274 ISL_FORMAT_BC3_UNORM = 392,
275 ISL_FORMAT_BC4_UNORM = 393,
276 ISL_FORMAT_BC5_UNORM = 394,
277 ISL_FORMAT_BC1_UNORM_SRGB = 395,
278 ISL_FORMAT_BC2_UNORM_SRGB = 396,
279 ISL_FORMAT_BC3_UNORM_SRGB = 397,
280 ISL_FORMAT_MONO8 = 398,
281 ISL_FORMAT_YCRCB_SWAPUV = 399,
282 ISL_FORMAT_YCRCB_SWAPY = 400,
283 ISL_FORMAT_DXT1_RGB = 401,
284 ISL_FORMAT_FXT1 = 402,
285 ISL_FORMAT_R8G8B8_UNORM = 403,
286 ISL_FORMAT_R8G8B8_SNORM = 404,
287 ISL_FORMAT_R8G8B8_SSCALED = 405,
288 ISL_FORMAT_R8G8B8_USCALED = 406,
289 ISL_FORMAT_R64G64B64A64_FLOAT = 407,
290 ISL_FORMAT_R64G64B64_FLOAT = 408,
291 ISL_FORMAT_BC4_SNORM = 409,
292 ISL_FORMAT_BC5_SNORM = 410,
293 ISL_FORMAT_R16G16B16_FLOAT = 411,
294 ISL_FORMAT_R16G16B16_UNORM = 412,
295 ISL_FORMAT_R16G16B16_SNORM = 413,
296 ISL_FORMAT_R16G16B16_SSCALED = 414,
297 ISL_FORMAT_R16G16B16_USCALED = 415,
298 ISL_FORMAT_BC6H_SF16 = 417,
299 ISL_FORMAT_BC7_UNORM = 418,
300 ISL_FORMAT_BC7_UNORM_SRGB = 419,
301 ISL_FORMAT_BC6H_UF16 = 420,
302 ISL_FORMAT_PLANAR_420_8 = 421,
303 ISL_FORMAT_PLANAR_420_16 = 422,
304 ISL_FORMAT_R8G8B8_UNORM_SRGB = 424,
305 ISL_FORMAT_ETC1_RGB8 = 425,
306 ISL_FORMAT_ETC2_RGB8 = 426,
307 ISL_FORMAT_EAC_R11 = 427,
308 ISL_FORMAT_EAC_RG11 = 428,
309 ISL_FORMAT_EAC_SIGNED_R11 = 429,
310 ISL_FORMAT_EAC_SIGNED_RG11 = 430,
311 ISL_FORMAT_ETC2_SRGB8 = 431,
312 ISL_FORMAT_R16G16B16_UINT = 432,
313 ISL_FORMAT_R16G16B16_SINT = 433,
314 ISL_FORMAT_R32_SFIXED = 434,
315 ISL_FORMAT_R10G10B10A2_SNORM = 435,
316 ISL_FORMAT_R10G10B10A2_USCALED = 436,
317 ISL_FORMAT_R10G10B10A2_SSCALED = 437,
318 ISL_FORMAT_R10G10B10A2_SINT = 438,
319 ISL_FORMAT_B10G10R10A2_SNORM = 439,
320 ISL_FORMAT_B10G10R10A2_USCALED = 440,
321 ISL_FORMAT_B10G10R10A2_SSCALED = 441,
322 ISL_FORMAT_B10G10R10A2_UINT = 442,
323 ISL_FORMAT_B10G10R10A2_SINT = 443,
324 ISL_FORMAT_R64G64B64A64_PASSTHRU = 444,
325 ISL_FORMAT_R64G64B64_PASSTHRU = 445,
326 ISL_FORMAT_ETC2_RGB8_PTA = 448,
327 ISL_FORMAT_ETC2_SRGB8_PTA = 449,
328 ISL_FORMAT_ETC2_EAC_RGBA8 = 450,
329 ISL_FORMAT_ETC2_EAC_SRGB8_A8 = 451,
330 ISL_FORMAT_R8G8B8_UINT = 456,
331 ISL_FORMAT_R8G8B8_SINT = 457,
332 ISL_FORMAT_RAW = 511,
333 ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB = 512,
334 ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB = 520,
335 ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB = 521,
336 ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB = 529,
337 ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB = 530,
338 ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB = 545,
339 ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB = 546,
340 ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB = 548,
341 ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB = 561,
342 ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB = 562,
343 ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB = 564,
344 ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB = 566,
345 ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB = 574,
346 ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB = 575,
347 ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16 = 576,
348 ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16 = 584,
349 ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16 = 585,
350 ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16 = 593,
351 ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16 = 594,
352 ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16 = 609,
353 ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16 = 610,
354 ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16 = 612,
355 ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16 = 625,
356 ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16 = 626,
357 ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16 = 628,
358 ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16 = 630,
359 ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16 = 638,
360 ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16 = 639,
361 ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16 = 832,
362 ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16 = 840,
363 ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16 = 841,
364 ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16 = 849,
365 ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16 = 850,
366 ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16 = 865,
367 ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16 = 866,
368 ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16 = 868,
369 ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16 = 881,
370 ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16 = 882,
371 ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16 = 884,
372 ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16 = 886,
373 ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16 = 894,
374 ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16 = 895,
375
376 /* The formats that follow are internal to ISL and as such don't have an
377 * explicit number. We'll just let the C compiler assign it for us. Any
378 * actual hardware formats *must* come before these in the list.
379 */
380
381 /* Formats for the aux-map */
382 ISL_FORMAT_PLANAR_420_10,
383 ISL_FORMAT_PLANAR_420_12,
384
385 /* Formats for auxiliary surfaces */
386 ISL_FORMAT_HIZ,
387 ISL_FORMAT_GFX125_HIZ,
388 ISL_FORMAT_MCS_2X,
389 ISL_FORMAT_MCS_4X,
390 ISL_FORMAT_MCS_8X,
391 ISL_FORMAT_MCS_16X,
392 ISL_FORMAT_GFX7_CCS_32BPP_X,
393 ISL_FORMAT_GFX7_CCS_64BPP_X,
394 ISL_FORMAT_GFX7_CCS_128BPP_X,
395 ISL_FORMAT_GFX7_CCS_32BPP_Y,
396 ISL_FORMAT_GFX7_CCS_64BPP_Y,
397 ISL_FORMAT_GFX7_CCS_128BPP_Y,
398 ISL_FORMAT_GFX9_CCS_32BPP,
399 ISL_FORMAT_GFX9_CCS_64BPP,
400 ISL_FORMAT_GFX9_CCS_128BPP,
401 ISL_FORMAT_GFX12_CCS_8BPP_Y0,
402 ISL_FORMAT_GFX12_CCS_16BPP_Y0,
403 ISL_FORMAT_GFX12_CCS_32BPP_Y0,
404 ISL_FORMAT_GFX12_CCS_64BPP_Y0,
405 ISL_FORMAT_GFX12_CCS_128BPP_Y0,
406
407 /* An upper bound on the supported format enumerations */
408 ISL_NUM_FORMATS,
409
410 /* Hardware doesn't understand this out-of-band value */
411 ISL_FORMAT_UNSUPPORTED = UINT16_MAX,
412 };
413
414 /**
415 * Numerical base type for channels of isl_format.
416 */
417 enum PACKED isl_base_type {
418 /** Data which takes up space but is ignored */
419 ISL_VOID,
420
421 /** Data in a "raw" form and cannot be easily interpreted */
422 ISL_RAW,
423
424 /**
425 * Unsigned normalized data
426 *
427 * Though stored as an integer, the data is interpreted as a floating-point
428 * number in the range [0, 1] where the conversion from the in-memory
429 * representation to float is given by \f$\frac{x}{2^{bits} - 1}\f$.
430 */
431 ISL_UNORM,
432
433 /**
434 * Signed normalized data
435 *
436 * Though stored as an integer, the data is interpreted as a floating-point
437 * number in the range [-1, 1] where the conversion from the in-memory
438 * representation to float is given by
439 * \f$max\left(\frac{x}{2^{bits - 1} - 1}, -1\right)\f$.
440 */
441 ISL_SNORM,
442
443 /**
444 * Unsigned floating-point data
445 *
446 * Unlike the standard IEEE floating-point representation, unsigned
447 * floating-point data has no sign bit. This saves a bit of space which is
448 * important if more than one float is required to represent a color value.
449 * As with IEEE floats, the high bits are the exponent and the low bits are
450 * the mantissa. The available bit sizes for unsigned floats are as
451 * follows:
452 *
453 * \rst
454 * ===== ========= =========
455 * Bits Mantissa Exponent
456 * ===== ========= =========
457 * 11 6 5
458 * 10 5 5
459 * ===== ========= =========
460 * \endrst
461 *
462 * In particular, both unsigned floating-point formats are identical to
463 * IEEE float16 except that the sign bit and the bottom mantissa bits are
464 * removed.
465 */
466 ISL_UFLOAT,
467
468 /** Signed floating-point data
469 *
470 * Signed floating-point data is represented as standard IEEE floats with
471 * the usual number of mantissa and exponent bits
472 *
473 * \rst
474 * ===== ========= =========
475 * Bits Mantissa Exponent
476 * ===== ========= =========
477 * 64 52 11
478 * 32 23 8
479 * 16 10 5
480 * ===== ========= =========
481 * \endrst
482 */
483 ISL_SFLOAT,
484
485 /**
486 * Unsigned fixed-point data
487 *
488 * This is a 32-bit unsigned integer that is interpreted as a 16.16
489 * fixed-point value.
490 */
491 ISL_UFIXED,
492
493 /**
494 * Signed fixed-point data
495 *
496 * This is a 32-bit signed integer that is interpreted as a 16.16
497 * fixed-point value.
498 */
499 ISL_SFIXED,
500
501 /** Unsigned integer data */
502 ISL_UINT,
503
504 /** Signed integer data */
505 ISL_SINT,
506
507 /**
508 * Unsigned scaled data
509 *
510 * This is data which is stored as an unsigned integer but interpreted as a
511 * floating-point value by the hardware. The re-interpretation is done via
512 * a simple unsigned integer to float cast. This is typically used as a
513 * vertex format.
514 */
515 ISL_USCALED,
516
517 /**
518 * Signed scaled data
519 *
520 * This is data which is stored as a signed integer but interpreted as a
521 * floating-point value by the hardware. The re-interpretation is done via
522 * a simple signed integer to float cast. This is typically used as a
523 * vertex format.
524 */
525 ISL_SSCALED,
526 };
527
528 /**
529 * Colorspace of isl_format.
530 */
531 enum isl_colorspace {
532 ISL_COLORSPACE_NONE = 0,
533 ISL_COLORSPACE_LINEAR,
534 ISL_COLORSPACE_SRGB,
535 ISL_COLORSPACE_YUV,
536 };
537
538 /**
539 * Texture compression mode of isl_format.
540 */
541 enum isl_txc {
542 ISL_TXC_NONE = 0,
543 ISL_TXC_DXT1,
544 ISL_TXC_DXT3,
545 ISL_TXC_DXT5,
546 ISL_TXC_FXT1,
547 ISL_TXC_RGTC1,
548 ISL_TXC_RGTC2,
549 ISL_TXC_BPTC,
550 ISL_TXC_ETC1,
551 ISL_TXC_ETC2,
552 ISL_TXC_ASTC,
553
554 /* Used for auxiliary surface formats */
555 ISL_TXC_HIZ,
556 ISL_TXC_MCS,
557 ISL_TXC_CCS,
558 };
559
560 /**
561 * Describes the memory tiling of a surface
562 *
563 * This differs from the HW enum values used to represent tiling. The bits
564 * used by hardware have varried significantly over the years from the
565 * "Tile Walk" bit on old pre-Broadwell parts to the "Tile Mode" enum on
566 * Broadwell to the combination of "Tile Mode" and "Tiled Resource Mode" on
567 * Skylake. This enum represents them all in a consistent manner and in one
568 * place.
569 *
570 * Note that legacy Y tiling is ISL_TILING_Y0 instead of ISL_TILING_Y, to
571 * clearly distinguish it from Yf and Ys.
572 */
573 enum isl_tiling {
574 ISL_TILING_LINEAR = 0, /**< Linear, or no tiling */
575 ISL_TILING_W, /**< W tiling */
576 ISL_TILING_X, /**< X tiling */
577 ISL_TILING_Y0, /**< Legacy Y tiling */
578 ISL_TILING_Yf, /**< Standard 4K tiling. The 'f' means "four". */
579 ISL_TILING_Ys, /**< Standard 64K tiling. The 's' means "sixty-four". */
580 ISL_TILING_4, /**< 4K tiling. */
581 ISL_TILING_64, /**< 64K tiling.*/
582 ISL_TILING_HIZ, /**< Tiling format for HiZ surfaces */
583 ISL_TILING_CCS, /**< Tiling format for CCS surfaces */
584 ISL_TILING_GFX12_CCS, /**< Tiling format for Gfx12 CCS surfaces */
585 };
586
587 /**
588 * @defgroup Tiling Flags
589 * @{
590 */
591 typedef uint32_t isl_tiling_flags_t;
592 #define ISL_TILING_LINEAR_BIT (1u << ISL_TILING_LINEAR)
593 #define ISL_TILING_W_BIT (1u << ISL_TILING_W)
594 #define ISL_TILING_X_BIT (1u << ISL_TILING_X)
595 #define ISL_TILING_Y0_BIT (1u << ISL_TILING_Y0)
596 #define ISL_TILING_Yf_BIT (1u << ISL_TILING_Yf)
597 #define ISL_TILING_Ys_BIT (1u << ISL_TILING_Ys)
598 #define ISL_TILING_4_BIT (1u << ISL_TILING_4)
599 #define ISL_TILING_64_BIT (1u << ISL_TILING_64)
600 #define ISL_TILING_HIZ_BIT (1u << ISL_TILING_HIZ)
601 #define ISL_TILING_CCS_BIT (1u << ISL_TILING_CCS)
602 #define ISL_TILING_GFX12_CCS_BIT (1u << ISL_TILING_GFX12_CCS)
603 #define ISL_TILING_ANY_MASK (~0u)
604 #define ISL_TILING_NON_LINEAR_MASK (~ISL_TILING_LINEAR_BIT)
605
606 /** Any Y tiling, including legacy Y tiling. */
607 #define ISL_TILING_ANY_Y_MASK (ISL_TILING_Y0_BIT | \
608 ISL_TILING_Yf_BIT | \
609 ISL_TILING_Ys_BIT)
610
611 /** The Skylake BSpec refers to Yf and Ys as "standard tiling formats". */
612 #define ISL_TILING_STD_Y_MASK (ISL_TILING_Yf_BIT | \
613 ISL_TILING_Ys_BIT)
614 /** @} */
615
616 /**
617 * @brief Logical dimension of surface.
618 *
619 * Note: There is no dimension for cube map surfaces. ISL interprets cube maps
620 * as 2D array surfaces.
621 */
622 enum isl_surf_dim {
623 ISL_SURF_DIM_1D,
624 ISL_SURF_DIM_2D,
625 ISL_SURF_DIM_3D,
626 };
627
628 /**
629 * @brief Physical layout of the surface's dimensions.
630 */
631 enum isl_dim_layout {
632 /**
633 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
634 * 6.17.3: 2D Surfaces.
635 *
636 * On many gens, 1D surfaces share the same layout as 2D surfaces. From
637 * the G35 PRM >> Volume 1: Graphics Core >> Section 6.17.2: 1D Surfaces:
638 *
639 * One-dimensional surfaces are identical to 2D surfaces with height of
640 * one.
641 *
642 * @invariant isl_surf::phys_level0_sa::depth == 1
643 */
644 ISL_DIM_LAYOUT_GFX4_2D,
645
646 /**
647 * For details, see the G35 PRM >> Volume 1: Graphics Core >> Section
648 * 6.17.5: 3D Surfaces.
649 *
650 * @invariant isl_surf::phys_level0_sa::array_len == 1
651 */
652 ISL_DIM_LAYOUT_GFX4_3D,
653
654 /**
655 * Special layout used for HiZ and stencil on Sandy Bridge to work around
656 * the hardware's lack of mipmap support. On gfx6, HiZ and stencil buffers
657 * work the same as on gfx7+ except that they don't technically support
658 * mipmapping. That does not, however, stop us from doing it. As far as
659 * Sandy Bridge hardware is concerned, HiZ and stencil always operates on a
660 * single miplevel 2D (possibly array) image. The dimensions of that image
661 * are NOT minified.
662 *
663 * In order to implement HiZ and stencil on Sandy Bridge, we create one
664 * full-sized 2D (possibly array) image for every LOD with every image
665 * aligned to a page boundary. When the surface is used with the stencil
666 * or HiZ hardware, we manually offset to the image for the given LOD.
667 *
668 * As a memory saving measure, we pretend that the width of each miplevel
669 * is minified and we place LOD1 and above below LOD0 but horizontally
670 * adjacent to each other. When considered as full-sized images, LOD1 and
671 * above technically overlap. However, since we only write to part of that
672 * image, the hardware will never notice the overlap.
673 *
674 * This layout looks something like this:
675 *
676 * +---------+
677 * | |
678 * | |
679 * +---------+
680 * | |
681 * | |
682 * +---------+
683 *
684 * +----+ +-+ .
685 * | | +-+
686 * +----+
687 *
688 * +----+ +-+ .
689 * | | +-+
690 * +----+
691 */
692 ISL_DIM_LAYOUT_GFX6_STENCIL_HIZ,
693
694 /**
695 * For details, see the Skylake BSpec >> Memory Views >> Common Surface
696 * Formats >> Surface Layout and Tiling >> » 1D Surfaces.
697 */
698 ISL_DIM_LAYOUT_GFX9_1D,
699 };
700
701 /**
702 * Enumerates the different forms of auxiliary surface compression
703 */
704 enum isl_aux_usage {
705 /** No Auxiliary surface is used */
706 ISL_AUX_USAGE_NONE,
707
708 /** Hierarchical depth compression
709 *
710 * First introduced on Iron Lake, this compression scheme compresses depth
711 * surfaces by storing alternate forms of the depth value in a HiZ surface.
712 * Possible (not all) compressed forms include:
713 *
714 * - An uncompressed "look at the main surface" value
715 *
716 * - A special value indicating that the main surface data should be
717 * ignored and considered to contain the clear value.
718 *
719 * - The depth for the entire main-surface block as a plane equation
720 *
721 * - The minimum/maximum depth for the main-surface block
722 *
723 * This second one isn't helpful for getting exact depth values but can
724 * still substantially accelerate depth testing if the specified range is
725 * sufficiently small.
726 */
727 ISL_AUX_USAGE_HIZ,
728
729 /** Multisampled color compression
730 *
731 * Introduced on Ivy Bridge, this compression scheme compresses
732 * multisampled color surfaces by storing a mapping from samples to planes
733 * in the MCS surface, allowing for de-duplication of identical samples.
734 * The MCS value of all 1's is reserved to indicate that the pixel contains
735 * the clear color. Exact details about the data stored in the MCS and how
736 * it maps samples to slices is documented in the PRMs.
737 *
738 * @invariant isl_surf::samples > 1
739 */
740 ISL_AUX_USAGE_MCS,
741
742 /** Single-sampled fast-clear-only color compression
743 *
744 * Introduced on Ivy Bridge, this compression scheme compresses
745 * single-sampled color surfaces by storing a bit for each cache line pair
746 * in the main surface in the CCS which indicates that the corresponding
747 * pair of cache lines in the main surface only contains the clear color.
748 * On Skylake, this is increased to two bits per cache line pair with 0x0
749 * meaning resolved and 0x3 meaning clear.
750 *
751 * @invariant The surface is a color surface
752 * @invariant isl_surf::samples == 1
753 */
754 ISL_AUX_USAGE_CCS_D,
755
756 /** Single-sample lossless color compression
757 *
758 * Introduced on Skylake, this compression scheme compresses single-sampled
759 * color surfaces by storing a 2-bit value for each cache line pair in the
760 * main surface which says how the corresponding pair of cache lines in the
761 * main surface are to be interpreted. Valid CCS values include:
762 *
763 * - `0x0`: Indicates that the corresponding pair of cache lines in the
764 * main surface contain valid color data
765 *
766 * - `0x1`: Indicates that the corresponding pair of cache lines in the
767 * main surface contain compressed color data. Typically, the
768 * compressed data fits in one of the two cache lines.
769 *
770 * - `0x3`: Indicates that the corresponding pair of cache lines in the
771 * main surface should be ignored. Those cache lines should be
772 * considered to contain the clear color.
773 *
774 * Starting with Tigerlake, each CCS value is 4 bits per cache line pair in
775 * the main surface.
776 *
777 * @invariant The surface is a color surface
778 * @invariant isl_surf::samples == 1
779 */
780 ISL_AUX_USAGE_CCS_E,
781
782 /** Single-sample lossless color compression on Tigerlake
783 *
784 * This is identical to ISL_AUX_USAGE_CCS_E except it also encodes the
785 * Tigerlake quirk about regular render writes possibly fast-clearing
786 * blocks in the surface.
787 *
788 * @invariant The surface is a color surface
789 * @invariant isl_surf::samples == 1
790 */
791 ISL_AUX_USAGE_GFX12_CCS_E,
792
793 /** Media color compression
794 *
795 * Used by the media engine on Tigerlake and above. This compression form
796 * is typically not produced by 3D drivers but they need to be able to
797 * consume it in order to get end-to-end compression when the image comes
798 * from media decode.
799 *
800 * @invariant The surface is a color surface
801 * @invariant isl_surf::samples == 1
802 */
803 ISL_AUX_USAGE_MC,
804
805 /** Combined HiZ+CCS in write-through mode
806 *
807 * In this mode, introduced on Tigerlake, the HiZ and CCS surfaces act as a
808 * single fused compression surface where resolves (but not ambiguates)
809 * operate on both surfaces at the same time. In this mode, the HiZ
810 * surface operates in write-through mode where it is only used for
811 * accelerating depth testing and not for actual compression. The
812 * CCS-compressed surface contains valid data at all times.
813 *
814 * @invariant The surface is a color surface
815 * @invariant isl_surf::samples == 1
816 */
817 ISL_AUX_USAGE_HIZ_CCS_WT,
818
819 /** Combined HiZ+CCS without write-through
820 *
821 * In this mode, introduced on Tigerlake, the HiZ and CCS surfaces act as a
822 * single fused compression surface where resolves (but not ambiguates)
823 * operate on both surfaces at the same time. In this mode, full HiZ
824 * compression is enabled and the CCS-compressed main surface may not
825 * contain valid data. The only way to read the surface outside of the
826 * depth hardware is to do a full resolve which resolves both HiZ and CCS
827 * so the surface is in the pass-through state.
828 *
829 * @invariant The surface is a depth surface
830 */
831 ISL_AUX_USAGE_HIZ_CCS,
832
833 /** Combined MCS+CCS without write-through
834 *
835 * In this mode, introduced on Tigerlake, we have fused MCS+CCS compression
836 * where the MCS is used for fast-clears and "identical samples"
837 * compression just like on Gfx7-11 but each plane is then CCS compressed.
838 *
839 * @invariant The surface is a depth surface
840 * @invariant isl_surf::samples > 1
841 */
842 ISL_AUX_USAGE_MCS_CCS,
843
844 /** Stencil compression
845 *
846 * Introduced on Tigerlake, this is similar to CCS_E only used to compress
847 * stencil surfaces.
848 *
849 * @invariant The surface is a stencil surface
850 * @invariant isl_surf::samples == 1
851 */
852 ISL_AUX_USAGE_STC_CCS,
853 };
854
855 /**
856 * Enum for keeping track of the state an auxiliary compressed surface.
857 *
858 * For any given auxiliary surface compression format (HiZ, CCS, or MCS), any
859 * given slice (lod + array layer) can be in one of the seven states described
860 * by this enum. Drawing with or without aux enabled may implicitly cause the
861 * surface to transition between these states. There are also four types of
862 * auxiliary compression operations which cause an explicit transition which
863 * are described by the isl_aux_op enum below.
864 *
865 * Not all operations are valid or useful in all states. The diagram below
866 * contains a complete description of the states and all valid and useful
867 * transitions except clear.
868 *
869 * Draw w/ Aux
870 * +----------+
871 * | |
872 * | +-------------+ Draw w/ Aux +-------------+
873 * +------>| Compressed |<-------------------| Clear |
874 * | w/ Clear |----->----+ | |
875 * +-------------+ | +-------------+
876 * | /|\ | | |
877 * | | | | |
878 * | | +------<-----+ | Draw w/
879 * | | | | Clear Only
880 * | | Full | | +----------+
881 * Partial | | Resolve | \|/ | |
882 * Resolve | | | +-------------+ |
883 * | | | | Partial |<------+
884 * | | | | Clear |<----------+
885 * | | | +-------------+ |
886 * | | | | |
887 * | | +------>---------+ Full |
888 * | | | Resolve |
889 * Draw w/ aux | | Partial Fast Clear | |
890 * +----------+ | +--------------------------+ | |
891 * | | \|/ | \|/ |
892 * | +-------------+ Full Resolve +-------------+ |
893 * +------>| Compressed |------------------->| Resolved | |
894 * | w/o Clear |<-------------------| | |
895 * +-------------+ Draw w/ Aux +-------------+ |
896 * /|\ | | |
897 * | Draw | | Draw |
898 * | w/ Aux | | w/o Aux |
899 * | Ambiguate | | |
900 * | +--------------------------+ | |
901 * Draw w/o Aux | | | Draw w/o Aux |
902 * +----------+ | | | +----------+ |
903 * | | | \|/ \|/ | | |
904 * | +-------------+ Ambiguate +-------------+ | |
905 * +------>| Pass- |<-------------------| Aux |<------+ |
906 * +------>| through | | Invalid | |
907 * | +-------------+ +-------------+ |
908 * | | | |
909 * +----------+ +-----------------------------------------------------+
910 * Draw w/ Partial Fast Clear
911 * Clear Only
912 *
913 *
914 * While the above general theory applies to all forms of auxiliary
915 * compression on Intel hardware, not all states and operations are available
916 * on all compression types. However, each of the auxiliary states and
917 * operations can be fairly easily mapped onto the above diagram:
918 *
919 * **HiZ:** Hierarchical depth compression is capable of being in any of
920 * the states above. Hardware provides three HiZ operations: "Depth
921 * Clear", "Depth Resolve", and "HiZ Resolve" which map to "Fast Clear",
922 * "Full Resolve", and "Ambiguate" respectively. The hardware provides no
923 * HiZ partial resolve operation so the only way to get into the
924 * "Compressed w/o Clear" state is to render with HiZ when the surface is
925 * in the resolved or pass-through states.
926 *
927 * **MCS:** Multisample compression is technically capable of being in any of
928 * the states above except that most of them aren't useful. Both the render
929 * engine and the sampler support MCS compression and, apart from clear color,
930 * MCS is format-unaware so we leave the surface compressed 100% of the time.
931 * The hardware provides no MCS operations.
932 *
933 * **CCS_D:** Single-sample fast-clears (also called CCS_D in ISL) are one of
934 * the simplest forms of compression since they don't do anything beyond clear
935 * color tracking. They really only support three of the six states: Clear,
936 * Partial Clear, and Pass-through. The only CCS_D operation is "Resolve"
937 * which maps to a full resolve followed by an ambiguate.
938 *
939 * **CCS_E:** Single-sample render target compression (also called CCS_E in
940 * ISL) is capable of being in almost all of the above states. THe only
941 * exception is that it does not have separate resolved and pass- through
942 * states. Instead, the CCS_E full resolve operation does both a resolve and
943 * an ambiguate so it goes directly into the pass-through state. CCS_E also
944 * provides fast clear and partial resolve operations which work as described
945 * above.
946 *
947 * @note
948 * The state machine above isn't quite correct for CCS on TGL. There is a HW
949 * bug (or feature, depending on who you ask) which can cause blocks to enter
950 * the fast-clear state as a side-effect of a regular draw call. This means
951 * that a draw in the resolved or compressed without clear states takes you to
952 * the compressed with clear state, not the compressed without clear state.
953 */
954 enum isl_aux_state {
955 #ifdef IN_UNIT_TEST
956 ISL_AUX_STATE_ASSERT,
957 #endif
958 /** Clear
959 *
960 * In this state, each block in the auxiliary surface contains a magic
961 * value that indicates that the block is in the clear state. If a block
962 * is in the clear state, its values in the primary surface are ignored
963 * and the color of the samples in the block is taken either the
964 * RENDER_SURFACE_STATE packet for color or 3DSTATE_CLEAR_PARAMS for depth.
965 * Since neither the primary surface nor the auxiliary surface contains the
966 * clear value, the surface can be cleared to a different color by simply
967 * changing the clear color without modifying either surface.
968 */
969 ISL_AUX_STATE_CLEAR,
970
971 /** Partial Clear
972 *
973 * In this state, each block in the auxiliary surface contains either the
974 * magic clear or pass-through value. See Clear and Pass-through for more
975 * details.
976 */
977 ISL_AUX_STATE_PARTIAL_CLEAR,
978
979 /** Compressed with clear color
980 *
981 * In this state, neither the auxiliary surface nor the primary surface has
982 * a complete representation of the data. Instead, both surfaces must be
983 * used together or else rendering corruption may occur. Depending on the
984 * auxiliary compression format and the data, any given block in the
985 * primary surface may contain all, some, or none of the data required to
986 * reconstruct the actual sample values. Blocks may also be in the clear
987 * state (see Clear) and have their value taken from outside the surface.
988 */
989 ISL_AUX_STATE_COMPRESSED_CLEAR,
990
991 /** Compressed without clear color
992 *
993 * This state is identical to the state above except that no blocks are in
994 * the clear state. In this state, all of the data required to reconstruct
995 * the final sample values is contained in the auxiliary and primary
996 * surface and the clear value is not considered.
997 */
998 ISL_AUX_STATE_COMPRESSED_NO_CLEAR,
999
1000 /** Resolved
1001 *
1002 * In this state, the primary surface contains 100% of the data. The
1003 * auxiliary surface is also valid so the surface can be validly used with
1004 * or without aux enabled. The auxiliary surface may, however, contain
1005 * non-trivial data and any update to the primary surface with aux disabled
1006 * will cause the two to get out of sync.
1007 */
1008 ISL_AUX_STATE_RESOLVED,
1009
1010 /** Pass-through
1011 *
1012 * In this state, the primary surface contains 100% of the data and every
1013 * block in the auxiliary surface contains a magic value which indicates
1014 * that the auxiliary surface should be ignored and only the primary
1015 * surface should be considered. In this mode, the primary surface can
1016 * safely be written with ISL_AUX_USAGE_NONE or by something that ignores
1017 * compression such as the blit/copy engine or a CPU map and it will stay
1018 * in the pass-through state. Writing to a surface in pass-through mode
1019 * with aux enabled may cause the auxiliary to be updated to contain
1020 * non-trivial data and it will no longer be in the pass-through state.
1021 * Likely, it will end up compressed, with or without clear color.
1022 */
1023 ISL_AUX_STATE_PASS_THROUGH,
1024
1025 /** Aux Invalid
1026 *
1027 * In this state, the primary surface contains 100% of the data and the
1028 * auxiliary surface is completely bogus. Any attempt to use the auxiliary
1029 * surface is liable to result in rendering corruption. The only thing
1030 * that one can do to re-enable aux once this state is reached is to use an
1031 * ambiguate pass to transition into the pass-through state.
1032 */
1033 ISL_AUX_STATE_AUX_INVALID,
1034 };
1035
1036 /** Enum describing explicit aux transition operations
1037 *
1038 * These operations are used to transition from one isl_aux_state to another.
1039 * Even though a draw does transition the state machine, it's not included in
1040 * this enum as it's something of a special case.
1041 */
1042 enum isl_aux_op {
1043 #ifdef IN_UNIT_TEST
1044 ISL_AUX_OP_ASSERT,
1045 #endif
1046
1047 /** Do nothing */
1048 ISL_AUX_OP_NONE,
1049
1050 /** Fast Clear
1051 *
1052 * This operation writes the magic "clear" value to the auxiliary surface.
1053 * This operation will safely transition any slice of a surface from any
1054 * state to the clear state so long as the entire slice is fast cleared at
1055 * once. A fast clear that only covers part of a slice of a surface is
1056 * called a partial fast clear.
1057 */
1058 ISL_AUX_OP_FAST_CLEAR,
1059
1060 /** Full Resolve
1061 *
1062 * This operation combines the auxiliary surface data with the primary
1063 * surface data and writes the result to the primary. For HiZ, the docs
1064 * call this a depth resolve. For CCS, the hardware full resolve operation
1065 * does both a full resolve and an ambiguate so it actually takes you all
1066 * the way to the pass-through state.
1067 */
1068 ISL_AUX_OP_FULL_RESOLVE,
1069
1070 /** Partial Resolve
1071 *
1072 * This operation considers blocks which are in the "clear" state and
1073 * writes the clear value directly into the primary or auxiliary surface.
1074 * Once this operation completes, the surface is still compressed but no
1075 * longer references the clear color. This operation is only available
1076 * for CCS_E.
1077 */
1078 ISL_AUX_OP_PARTIAL_RESOLVE,
1079
1080 /** Ambiguate
1081 *
1082 * This operation throws away the current auxiliary data and replaces it
1083 * with the magic pass-through value. If an ambiguate operation is
1084 * performed when the primary surface does not contain 100% of the data,
1085 * data will be lost. This operation is only implemented in hardware for
1086 * depth where it is called a HiZ resolve.
1087 */
1088 ISL_AUX_OP_AMBIGUATE,
1089 };
1090
1091 /* TODO(chadv): Explain */
1092 enum isl_array_pitch_span {
1093 ISL_ARRAY_PITCH_SPAN_FULL,
1094 ISL_ARRAY_PITCH_SPAN_COMPACT,
1095 };
1096
1097 /**
1098 * @defgroup Surface Usage
1099 * @{
1100 */
1101 typedef uint64_t isl_surf_usage_flags_t;
1102 #define ISL_SURF_USAGE_RENDER_TARGET_BIT (1u << 0)
1103 #define ISL_SURF_USAGE_DEPTH_BIT (1u << 1)
1104 #define ISL_SURF_USAGE_STENCIL_BIT (1u << 2)
1105 #define ISL_SURF_USAGE_TEXTURE_BIT (1u << 3)
1106 #define ISL_SURF_USAGE_CUBE_BIT (1u << 4)
1107 #define ISL_SURF_USAGE_DISABLE_AUX_BIT (1u << 5)
1108 #define ISL_SURF_USAGE_DISPLAY_BIT (1u << 6)
1109 #define ISL_SURF_USAGE_STORAGE_BIT (1u << 7)
1110 #define ISL_SURF_USAGE_HIZ_BIT (1u << 8)
1111 #define ISL_SURF_USAGE_MCS_BIT (1u << 9)
1112 #define ISL_SURF_USAGE_CCS_BIT (1u << 10)
1113 #define ISL_SURF_USAGE_VERTEX_BUFFER_BIT (1u << 11)
1114 #define ISL_SURF_USAGE_INDEX_BUFFER_BIT (1u << 12)
1115 #define ISL_SURF_USAGE_CONSTANT_BUFFER_BIT (1u << 13)
1116 #define ISL_SURF_USAGE_STAGING_BIT (1u << 14)
1117 #define ISL_SURF_USAGE_CPB_BIT (1u << 15)
1118 /** @} */
1119
1120 /**
1121 * @defgroup Channel Mask
1122 *
1123 * These #define values are chosen to match the values of
1124 * RENDER_SURFACE_STATE::Color Buffer Component Write Disables
1125 *
1126 * @{
1127 */
1128 typedef uint8_t isl_channel_mask_t;
1129 #define ISL_CHANNEL_BLUE_BIT (1 << 0)
1130 #define ISL_CHANNEL_GREEN_BIT (1 << 1)
1131 #define ISL_CHANNEL_RED_BIT (1 << 2)
1132 #define ISL_CHANNEL_ALPHA_BIT (1 << 3)
1133 /** @} */
1134
1135 /**
1136 * @brief A channel select (also known as texture swizzle) value
1137 */
1138 enum PACKED isl_channel_select {
1139 ISL_CHANNEL_SELECT_ZERO = 0,
1140 ISL_CHANNEL_SELECT_ONE = 1,
1141 ISL_CHANNEL_SELECT_RED = 4,
1142 ISL_CHANNEL_SELECT_GREEN = 5,
1143 ISL_CHANNEL_SELECT_BLUE = 6,
1144 ISL_CHANNEL_SELECT_ALPHA = 7,
1145 };
1146
1147 /**
1148 * Identical to VkSampleCountFlagBits.
1149 */
1150 enum isl_sample_count {
1151 ISL_SAMPLE_COUNT_1_BIT = 1u,
1152 ISL_SAMPLE_COUNT_2_BIT = 2u,
1153 ISL_SAMPLE_COUNT_4_BIT = 4u,
1154 ISL_SAMPLE_COUNT_8_BIT = 8u,
1155 ISL_SAMPLE_COUNT_16_BIT = 16u,
1156 };
1157 typedef uint32_t isl_sample_count_mask_t;
1158
1159 /**
1160 * @brief Multisample Format
1161 */
1162 enum isl_msaa_layout {
1163 /**
1164 * @brief Surface is single-sampled.
1165 */
1166 ISL_MSAA_LAYOUT_NONE,
1167
1168 /**
1169 * @brief [SNB+] Interleaved Multisample Format
1170 *
1171 * In this format, multiple samples are interleaved into each cacheline.
1172 * In other words, the sample index is swizzled into the low 6 bits of the
1173 * surface's virtual address space.
1174 *
1175 * For example, suppose the surface is legacy Y tiled, is 4x multisampled,
1176 * and its pixel format is 32bpp. Then the first cacheline is arranged
1177 * thus:
1178 *
1179 * (0,0,0) (0,1,0) (0,0,1) (1,0,1)
1180 * (1,0,0) (1,1,0) (0,1,1) (1,1,1)
1181 *
1182 * (0,0,2) (1,0,2) (0,0,3) (1,0,3)
1183 * (0,1,2) (1,1,2) (0,1,3) (1,1,3)
1184 *
1185 * The hardware docs refer to this format with multiple terms. In
1186 * Sandybridge, this is the only multisample format; so no term is used.
1187 * The Ivybridge docs refer to surfaces in this format as IMS (Interleaved
1188 * Multisample Surface). Later hardware docs additionally refer to this
1189 * format as MSFMT_DEPTH_STENCIL (because the format is deprecated for
1190 * color surfaces).
1191 *
1192 * See the Sandybridge PRM, Volume 4, Part 1, Section 2.7 "Multisampled
1193 * Surface Behavior".
1194 *
1195 * See the Ivybridge PRM, Volume 1, Part 1, Section 6.18.4.1 "Interleaved
1196 * Multisampled Surfaces".
1197 */
1198 ISL_MSAA_LAYOUT_INTERLEAVED,
1199
1200 /**
1201 * @brief [IVB+] Array Multisample Format
1202 *
1203 * In this format, the surface's physical layout resembles that of a
1204 * 2D array surface.
1205 *
1206 * Suppose the multisample surface's logical extent is (w, h) and its
1207 * sample count is N. Then surface's physical extent is the same as
1208 * a singlesample 2D surface whose logical extent is (w, h) and array
1209 * length is N. Array slice `i` contains the pixel values for sample
1210 * index `i`.
1211 *
1212 * The Ivybridge docs refer to surfaces in this format as UMS
1213 * (Uncompressed Multsample Layout) and CMS (Compressed Multisample
1214 * Surface). The Broadwell docs additionally refer to this format as
1215 * MSFMT_MSS (MSS=Multisample Surface Storage).
1216 *
1217 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Uncompressed
1218 * Multisample Surfaces".
1219 *
1220 * See the Broadwell PRM, Volume 5 "Memory Views", Section "Compressed
1221 * Multisample Surfaces".
1222 */
1223 ISL_MSAA_LAYOUT_ARRAY,
1224 };
1225
1226 typedef enum {
1227 ISL_MEMCPY = 0,
1228 ISL_MEMCPY_BGRA8,
1229 ISL_MEMCPY_STREAMING_LOAD,
1230 ISL_MEMCPY_INVALID,
1231 } isl_memcpy_type;
1232
1233 struct isl_device {
1234 const struct intel_device_info *info;
1235 bool use_separate_stencil;
1236 bool has_bit6_swizzling;
1237
1238 /**
1239 * Describes the layout of a RENDER_SURFACE_STATE structure for the
1240 * current gen.
1241 */
1242 struct {
1243 uint8_t size;
1244 uint8_t align;
1245 uint8_t addr_offset;
1246 uint8_t aux_addr_offset;
1247
1248 /* Rounded up to the nearest dword to simplify GPU memcpy operations. */
1249
1250 /* size of the state buffer used to store the clear color + extra
1251 * additional space used by the hardware */
1252 uint8_t clear_color_state_size;
1253 uint8_t clear_color_state_offset;
1254 /* size of the clear color itself - used to copy it to/from a BO */
1255 uint8_t clear_value_size;
1256 uint8_t clear_value_offset;
1257 } ss;
1258
1259 uint64_t max_buffer_size;
1260
1261 /**
1262 * Describes the layout of the depth/stencil/hiz commands as emitted by
1263 * isl_emit_depth_stencil_hiz.
1264 */
1265 struct {
1266 uint8_t size;
1267 uint8_t depth_offset;
1268 uint8_t stencil_offset;
1269 uint8_t hiz_offset;
1270 } ds;
1271
1272 /**
1273 * Describes the layout of the coarse pixel control commands as emitted by
1274 * isl_emit_cpb_control.
1275 */
1276 struct {
1277 uint8_t size;
1278 uint8_t offset;
1279 } cpb;
1280
1281 struct {
1282 uint32_t internal;
1283 uint32_t external;
1284 uint32_t l1_hdc_l3_llc;
1285 uint32_t blitter_src;
1286 uint32_t blitter_dst;
1287 } mocs;
1288 };
1289
1290 struct isl_extent2d {
1291 union { uint32_t w, width; };
1292 union { uint32_t h, height; };
1293 };
1294
1295 struct isl_extent3d {
1296 union { uint32_t w, width; };
1297 union { uint32_t h, height; };
1298 union { uint32_t d, depth; };
1299 };
1300
1301 struct isl_extent4d {
1302 union { uint32_t w, width; };
1303 union { uint32_t h, height; };
1304 union { uint32_t d, depth; };
1305 union { uint32_t a, array_len; };
1306 };
1307
1308 /**
1309 * Describes a single channel of an isl_format
1310 */
1311 struct isl_channel_layout {
1312 enum isl_base_type type; /**< Channel data encoding */
1313 uint8_t start_bit; /**< Bit at which this channel starts */
1314 uint8_t bits; /**< Size in bits */
1315 };
1316
1317 /**
1318 * Describes the layout of an isl_format
1319 *
1320 * Each format has 3D block extent (width, height, depth). The block extent of
1321 * compressed formats is that of the format's compression block. For example,
1322 * the block extent of `ISL_FORMAT_ETC2_RGB8` is `(w=4, h=4, d=1)`. The block
1323 * extent of uncompressed pixel formats, such as `ISL_FORMAT_R8G8B8A8_UNORM`,
1324 * is `(w=1, h=1, d=1)`.
1325 */
1326 struct isl_format_layout {
1327 enum isl_format format; /**< Format */
1328
1329 uint16_t bpb; /**< Bits per block */
1330 uint8_t bw; /**< Block width, in pixels */
1331 uint8_t bh; /**< Block height, in pixels */
1332 uint8_t bd; /**< Block depth, in pixels */
1333
1334 union {
1335 struct {
1336 struct isl_channel_layout r; /**< Red channel */
1337 struct isl_channel_layout g; /**< Green channel */
1338 struct isl_channel_layout b; /**< Blue channel */
1339 struct isl_channel_layout a; /**< Alpha channel */
1340 struct isl_channel_layout l; /**< Luminance channel */
1341 struct isl_channel_layout i; /**< Intensity channel */
1342 struct isl_channel_layout p; /**< Palette channel */
1343 } channels;
1344 struct isl_channel_layout channels_array[7];
1345 };
1346
1347 /** Set if all channels have the same isl_base_type. Otherwise, ISL_VOID. */
1348 enum isl_base_type uniform_channel_type;
1349
1350 enum isl_colorspace colorspace;
1351 enum isl_txc txc;
1352 };
1353
1354 struct isl_tile_info {
1355 /** Tiling represented by this isl_tile_info */
1356 enum isl_tiling tiling;
1357
1358 /**
1359 * The size (in bits per block) of a single surface element
1360 *
1361 * For surfaces with power-of-two formats, this is the same as
1362 * isl_format_layout::bpb. For non-power-of-two formats it may be smaller.
1363 * The logical_extent_el field is in terms of elements of this size.
1364 *
1365 * For example, consider ISL_FORMAT_R32G32B32_FLOAT for which
1366 * isl_format_layout::bpb is 96 (a non-power-of-two). In this case, none
1367 * of the tiling formats can actually hold an integer number of 96-bit
1368 * surface elements so isl_tiling_get_info returns an isl_tile_info for a
1369 * 32-bit element size. It is the responsibility of the caller to
1370 * recognize that 32 != 96 ad adjust accordingly. For instance, to compute
1371 * the width of a surface in tiles, you would do:
1372 *
1373 * width_tl = DIV_ROUND_UP(width_el * (format_bpb / tile_info.format_bpb),
1374 * tile_info.logical_extent_el.width);
1375 */
1376 uint32_t format_bpb;
1377
1378 /**
1379 * The logical size of the tile in units of format_bpb size elements
1380 *
1381 * This field determines how a given surface is cut up into tiles. It is
1382 * used to compute the size of a surface in tiles and can be used to
1383 * determine the location of the tile containing any given surface element.
1384 * The exact value of this field depends heavily on the bits-per-block of
1385 * the format being used.
1386 */
1387 struct isl_extent4d logical_extent_el;
1388
1389 /**
1390 * The physical size of the tile in bytes and rows of bytes
1391 *
1392 * This field determines how the tiles of a surface are physically laid
1393 * out in memory. The logical and physical tile extent are frequently the
1394 * same but this is not always the case. For instance, a W-tile (which is
1395 * always used with ISL_FORMAT_R8) has a logical size of 64el x 64el but
1396 * its physical size is 128B x 32rows, the same as a Y-tile.
1397 *
1398 * @see isl_surf::row_pitch_B
1399 */
1400 struct isl_extent2d phys_extent_B;
1401 };
1402
1403 /**
1404 * Metadata about a DRM format modifier.
1405 */
1406 struct isl_drm_modifier_info {
1407 uint64_t modifier;
1408
1409 /** Text name of the modifier */
1410 const char *name;
1411
1412 /** ISL tiling implied by this modifier */
1413 enum isl_tiling tiling;
1414
1415 /** ISL aux usage implied by this modifier */
1416 enum isl_aux_usage aux_usage;
1417
1418 /** Whether or not this modifier supports clear color */
1419 bool supports_clear_color;
1420 };
1421
1422 /**
1423 * @brief Input to surface initialization
1424 *
1425 * @invariant width >= 1
1426 * @invariant height >= 1
1427 * @invariant depth >= 1
1428 * @invariant levels >= 1
1429 * @invariant samples >= 1
1430 * @invariant array_len >= 1
1431 *
1432 * @invariant if 1D then height == 1 and depth == 1 and samples == 1
1433 * @invariant if 2D then depth == 1
1434 * @invariant if 3D then array_len == 1 and samples == 1
1435 */
1436 struct isl_surf_init_info {
1437 enum isl_surf_dim dim;
1438 enum isl_format format;
1439
1440 uint32_t width;
1441 uint32_t height;
1442 uint32_t depth;
1443 uint32_t levels;
1444 uint32_t array_len;
1445 uint32_t samples;
1446
1447 /** Lower bound for isl_surf::alignment, in bytes. */
1448 uint32_t min_alignment_B;
1449
1450 /**
1451 * Exact value for isl_surf::row_pitch. Ignored if zero. isl_surf_init()
1452 * will fail if this is misaligned or out of bounds.
1453 */
1454 uint32_t row_pitch_B;
1455
1456 isl_surf_usage_flags_t usage;
1457
1458 /** Flags that alter how ISL selects isl_surf::tiling. */
1459 isl_tiling_flags_t tiling_flags;
1460 };
1461
1462 struct isl_surf {
1463 /** Dimensionality of the surface */
1464 enum isl_surf_dim dim;
1465
1466 /**
1467 * Spatial layout of the surface in memory
1468 *
1469 * This is dependent on isl_surf::dim and hardware generation.
1470 */
1471 enum isl_dim_layout dim_layout;
1472
1473 /** Spatial layout of the samples if isl_surf::samples > 1 */
1474 enum isl_msaa_layout msaa_layout;
1475
1476 /** Memory tiling used by the surface */
1477 enum isl_tiling tiling;
1478
1479 /**
1480 * Base image format of the surface
1481 *
1482 * This need not be the same as the format specified in isl_view::format
1483 * when a surface state is constructed. It must, however, have the same
1484 * number of bits per pixel or else memory calculations will go wrong.
1485 */
1486 enum isl_format format;
1487
1488 /**
1489 * Alignment of the upper-left sample of each subimage, in units of surface
1490 * elements.
1491 */
1492 struct isl_extent3d image_alignment_el;
1493
1494 /**
1495 * Logical extent of the surface's base level, in units of pixels. This is
1496 * identical to the extent defined in isl_surf_init_info.
1497 */
1498 struct isl_extent4d logical_level0_px;
1499
1500 /**
1501 * Physical extent of the surface's base level, in units of physical
1502 * surface samples.
1503 *
1504 * Consider isl_dim_layout as an operator that transforms a logical surface
1505 * layout to a physical surface layout. Then
1506 *
1507 * logical_layout := (isl_surf::dim, isl_surf::logical_level0_px)
1508 * isl_surf::phys_level0_sa := isl_surf::dim_layout * logical_layout
1509 */
1510 struct isl_extent4d phys_level0_sa;
1511
1512 /** Number of miplevels in the surface */
1513 uint32_t levels;
1514
1515 /**
1516 * Number of samples in the surface
1517 *
1518 * @invariant samples >= 1
1519 */
1520 uint32_t samples;
1521
1522 /** Total size of the surface, in bytes. */
1523 uint64_t size_B;
1524
1525 /** Required alignment for the surface's base address. */
1526 uint32_t alignment_B;
1527
1528 /**
1529 * The interpretation of this field depends on the value of
1530 * isl_tile_info::physical_extent_B. In particular, the width of the
1531 * surface in tiles is row_pitch_B / isl_tile_info::physical_extent_B.width
1532 * and the distance in bytes between vertically adjacent tiles in the image
1533 * is given by row_pitch_B * isl_tile_info::physical_extent_B.height.
1534 *
1535 * For linear images where isl_tile_info::physical_extent_B.height == 1,
1536 * this cleanly reduces to being the distance, in bytes, between vertically
1537 * adjacent surface elements.
1538 *
1539 * @see isl_tile_info::phys_extent_B;
1540 */
1541 uint32_t row_pitch_B;
1542
1543 /**
1544 * Pitch between physical array slices, in rows of surface elements.
1545 */
1546 uint32_t array_pitch_el_rows;
1547
1548 enum isl_array_pitch_span array_pitch_span;
1549
1550 /** Copy of isl_surf_init_info::usage. */
1551 isl_surf_usage_flags_t usage;
1552 };
1553
1554 struct isl_swizzle {
1555 enum isl_channel_select r:4;
1556 enum isl_channel_select g:4;
1557 enum isl_channel_select b:4;
1558 enum isl_channel_select a:4;
1559 };
1560
1561 #define ISL_SWIZZLE(R, G, B, A) ((struct isl_swizzle) { \
1562 .r = ISL_CHANNEL_SELECT_##R, \
1563 .g = ISL_CHANNEL_SELECT_##G, \
1564 .b = ISL_CHANNEL_SELECT_##B, \
1565 .a = ISL_CHANNEL_SELECT_##A, \
1566 })
1567
1568 #define ISL_SWIZZLE_IDENTITY ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
1569
1570 struct isl_view {
1571 /**
1572 * Indicates the usage of the particular view
1573 *
1574 * Normally, this is one bit. However, for a cube map texture, it
1575 * should be ISL_SURF_USAGE_TEXTURE_BIT | ISL_SURF_USAGE_CUBE_BIT.
1576 */
1577 isl_surf_usage_flags_t usage;
1578
1579 /**
1580 * The format to use in the view
1581 *
1582 * This may differ from the format of the actual isl_surf but must have
1583 * the same block size.
1584 */
1585 enum isl_format format;
1586
1587 uint32_t base_level;
1588 uint32_t levels;
1589
1590 /**
1591 * Base array layer
1592 *
1593 * For cube maps, both base_array_layer and array_len should be
1594 * specified in terms of 2-D layers and must be a multiple of 6.
1595 *
1596 * 3-D textures are effectively treated as 2-D arrays when used as a
1597 * storage image or render target. If `usage` contains
1598 * ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
1599 * base_array_layer and array_len are applied. If the surface is only used
1600 * for texturing, they are ignored.
1601 */
1602 uint32_t base_array_layer;
1603
1604 /**
1605 * Array Length
1606 *
1607 * Indicates the number of array elements starting at Base Array Layer.
1608 */
1609 uint32_t array_len;
1610
1611 /**
1612 * Minimum LOD
1613 *
1614 * Similar to sampler minimum LOD, the computed LOD is clamped to be at
1615 * least min_lod_clamp.
1616 */
1617 float min_lod_clamp;
1618
1619 struct isl_swizzle swizzle;
1620 };
1621
1622 union isl_color_value {
1623 float f32[4];
1624 uint32_t u32[4];
1625 int32_t i32[4];
1626 };
1627
1628 struct isl_surf_fill_state_info {
1629 const struct isl_surf *surf;
1630 const struct isl_view *view;
1631
1632 /**
1633 * The address of the surface in GPU memory.
1634 */
1635 uint64_t address;
1636
1637 /**
1638 * The Memory Object Control state for the filled surface state.
1639 *
1640 * The exact format of this value depends on hardware generation.
1641 */
1642 uint32_t mocs;
1643
1644 /**
1645 * The auxiliary surface or NULL if no auxiliary surface is to be used.
1646 */
1647 const struct isl_surf *aux_surf;
1648 enum isl_aux_usage aux_usage;
1649 uint64_t aux_address;
1650
1651 /**
1652 * The format to use for decoding media compression.
1653 *
1654 * Used together with the surface format.
1655 */
1656 enum isl_format mc_format;
1657
1658 /**
1659 * The clear color for this surface
1660 *
1661 * Valid values depend on hardware generation.
1662 */
1663 union isl_color_value clear_color;
1664
1665 /**
1666 * Send only the clear value address
1667 *
1668 * If set, we only pass the clear address to the GPU and it will fetch it
1669 * from wherever it is.
1670 */
1671 bool use_clear_address;
1672 uint64_t clear_address;
1673
1674 /**
1675 * Surface write disables for gfx4-5
1676 */
1677 isl_channel_mask_t write_disables;
1678
1679 /**
1680 * blend enable for gfx4-5
1681 */
1682 bool blend_enable;
1683
1684 /* Intra-tile offset */
1685 uint16_t x_offset_sa, y_offset_sa;
1686 };
1687
1688 struct isl_buffer_fill_state_info {
1689 /**
1690 * The address of the surface in GPU memory.
1691 */
1692 uint64_t address;
1693
1694 /**
1695 * The size of the buffer
1696 */
1697 uint64_t size_B;
1698
1699 /**
1700 * The Memory Object Control state for the filled surface state.
1701 *
1702 * The exact format of this value depends on hardware generation.
1703 */
1704 uint32_t mocs;
1705
1706 /**
1707 * The format to use in the surface state
1708 *
1709 * This may differ from the format of the actual isl_surf but have the
1710 * same block size.
1711 */
1712 enum isl_format format;
1713
1714 /**
1715 * The swizzle to use in the surface state
1716 */
1717 struct isl_swizzle swizzle;
1718
1719 uint32_t stride_B;
1720
1721 bool is_scratch;
1722 };
1723
1724 struct isl_depth_stencil_hiz_emit_info {
1725 /**
1726 * The depth surface
1727 */
1728 const struct isl_surf *depth_surf;
1729
1730 /**
1731 * The stencil surface
1732 *
1733 * If separate stencil is not available, this must point to the same
1734 * isl_surf as depth_surf.
1735 */
1736 const struct isl_surf *stencil_surf;
1737
1738 /**
1739 * The view into the depth and stencil surfaces.
1740 *
1741 * This view applies to both surfaces simultaneously.
1742 */
1743 const struct isl_view *view;
1744
1745 /**
1746 * The address of the depth surface in GPU memory
1747 */
1748 uint64_t depth_address;
1749
1750 /**
1751 * The address of the stencil surface in GPU memory
1752 *
1753 * If separate stencil is not available, this must have the same value as
1754 * depth_address.
1755 */
1756 uint64_t stencil_address;
1757
1758 /**
1759 * The Memory Object Control state for depth and stencil buffers
1760 *
1761 * Both depth and stencil will get the same MOCS value. The exact format
1762 * of this value depends on hardware generation.
1763 */
1764 uint32_t mocs;
1765
1766 /**
1767 * The HiZ surface or NULL if HiZ is disabled.
1768 */
1769 const struct isl_surf *hiz_surf;
1770 enum isl_aux_usage hiz_usage;
1771 uint64_t hiz_address;
1772
1773 /**
1774 * The depth clear value
1775 */
1776 float depth_clear_value;
1777
1778 /**
1779 * Track stencil aux usage for Gen >= 12
1780 */
1781 enum isl_aux_usage stencil_aux_usage;
1782 };
1783
1784 struct isl_null_fill_state_info {
1785 struct isl_extent3d size;
1786 uint32_t levels;
1787 uint32_t minimum_array_element;
1788 };
1789
1790 struct isl_cpb_emit_info {
1791 /**
1792 * The coarse pixel shading control surface.
1793 */
1794 const struct isl_surf *surf;
1795
1796 /**
1797 * The view into the control surface.
1798 */
1799 const struct isl_view *view;
1800
1801 /**
1802 * The address of the control surface in GPU memory.
1803 */
1804 uint64_t address;
1805
1806 /**
1807 * The Memory Object Control state for the surface.
1808 */
1809 uint32_t mocs;
1810 };
1811
1812 extern const struct isl_format_layout isl_format_layouts[];
1813 extern const char isl_format_names[];
1814 extern const uint16_t isl_format_name_offsets[];
1815
1816 void
1817 isl_device_init(struct isl_device *dev,
1818 const struct intel_device_info *info);
1819
1820 isl_sample_count_mask_t ATTRIBUTE_CONST
1821 isl_device_get_sample_counts(struct isl_device *dev);
1822
1823 /**
1824 * \return The isl_format_layout for the given isl_format
1825 */
1826 static inline const struct isl_format_layout * ATTRIBUTE_CONST
isl_format_get_layout(enum isl_format fmt)1827 isl_format_get_layout(enum isl_format fmt)
1828 {
1829 assert(fmt != ISL_FORMAT_UNSUPPORTED);
1830 assert(fmt < ISL_NUM_FORMATS);
1831 return &isl_format_layouts[fmt];
1832 }
1833
1834 bool isl_format_is_valid(enum isl_format);
1835
1836 static inline const char * ATTRIBUTE_CONST
isl_format_get_name(enum isl_format fmt)1837 isl_format_get_name(enum isl_format fmt)
1838 {
1839 assert(fmt != ISL_FORMAT_UNSUPPORTED);
1840 assert(fmt < ISL_NUM_FORMATS);
1841 return isl_format_names + isl_format_name_offsets[fmt];
1842 }
1843
1844 enum isl_format isl_format_for_pipe_format(enum pipe_format pf);
1845
1846 bool isl_format_supports_rendering(const struct intel_device_info *devinfo,
1847 enum isl_format format);
1848 bool isl_format_supports_alpha_blending(const struct intel_device_info *devinfo,
1849 enum isl_format format);
1850 bool isl_format_supports_sampling(const struct intel_device_info *devinfo,
1851 enum isl_format format);
1852 bool isl_format_supports_filtering(const struct intel_device_info *devinfo,
1853 enum isl_format format);
1854 bool isl_format_supports_vertex_fetch(const struct intel_device_info *devinfo,
1855 enum isl_format format);
1856 bool isl_format_supports_typed_writes(const struct intel_device_info *devinfo,
1857 enum isl_format format);
1858 bool isl_format_supports_typed_reads(const struct intel_device_info *devinfo,
1859 enum isl_format format);
1860 bool isl_format_supports_ccs_d(const struct intel_device_info *devinfo,
1861 enum isl_format format);
1862 bool isl_format_supports_ccs_e(const struct intel_device_info *devinfo,
1863 enum isl_format format);
1864 bool isl_format_supports_multisampling(const struct intel_device_info *devinfo,
1865 enum isl_format format);
1866 bool isl_format_supports_typed_atomics(const struct intel_device_info *devinfo,
1867 enum isl_format fmt);
1868
1869 bool isl_formats_are_ccs_e_compatible(const struct intel_device_info *devinfo,
1870 enum isl_format format1,
1871 enum isl_format format2);
1872 uint8_t isl_format_get_aux_map_encoding(enum isl_format format);
1873 uint8_t isl_get_render_compression_format(enum isl_format format);
1874
1875 bool isl_formats_have_same_bits_per_channel(enum isl_format format1,
1876 enum isl_format format2);
1877
1878 bool isl_format_has_unorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1879 bool isl_format_has_snorm_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1880 bool isl_format_has_ufloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1881 bool isl_format_has_sfloat_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1882 bool isl_format_has_uint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1883 bool isl_format_has_sint_channel(enum isl_format fmt) ATTRIBUTE_CONST;
1884
1885 static inline bool
isl_format_has_normalized_channel(enum isl_format fmt)1886 isl_format_has_normalized_channel(enum isl_format fmt)
1887 {
1888 return isl_format_has_unorm_channel(fmt) ||
1889 isl_format_has_snorm_channel(fmt);
1890 }
1891
1892 static inline bool
isl_format_has_float_channel(enum isl_format fmt)1893 isl_format_has_float_channel(enum isl_format fmt)
1894 {
1895 return isl_format_has_ufloat_channel(fmt) ||
1896 isl_format_has_sfloat_channel(fmt);
1897 }
1898
1899 static inline bool
isl_format_has_int_channel(enum isl_format fmt)1900 isl_format_has_int_channel(enum isl_format fmt)
1901 {
1902 return isl_format_has_uint_channel(fmt) ||
1903 isl_format_has_sint_channel(fmt);
1904 }
1905
1906 bool isl_format_has_color_component(enum isl_format fmt,
1907 int component) ATTRIBUTE_CONST;
1908
1909 unsigned isl_format_get_num_channels(enum isl_format fmt);
1910
1911 uint32_t isl_format_get_depth_format(enum isl_format fmt, bool has_stencil);
1912
1913 static inline bool
isl_format_is_compressed(enum isl_format fmt)1914 isl_format_is_compressed(enum isl_format fmt)
1915 {
1916 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1917
1918 return fmtl->txc != ISL_TXC_NONE;
1919 }
1920
1921 static inline bool
isl_format_has_bc_compression(enum isl_format fmt)1922 isl_format_has_bc_compression(enum isl_format fmt)
1923 {
1924 switch (isl_format_get_layout(fmt)->txc) {
1925 case ISL_TXC_DXT1:
1926 case ISL_TXC_DXT3:
1927 case ISL_TXC_DXT5:
1928 return true;
1929 case ISL_TXC_NONE:
1930 case ISL_TXC_FXT1:
1931 case ISL_TXC_RGTC1:
1932 case ISL_TXC_RGTC2:
1933 case ISL_TXC_BPTC:
1934 case ISL_TXC_ETC1:
1935 case ISL_TXC_ETC2:
1936 case ISL_TXC_ASTC:
1937 return false;
1938
1939 case ISL_TXC_HIZ:
1940 case ISL_TXC_MCS:
1941 case ISL_TXC_CCS:
1942 unreachable("Should not be called on an aux surface");
1943 }
1944
1945 unreachable("bad texture compression mode");
1946 return false;
1947 }
1948
1949 static inline bool
isl_format_is_mcs(enum isl_format fmt)1950 isl_format_is_mcs(enum isl_format fmt)
1951 {
1952 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1953
1954 return fmtl->txc == ISL_TXC_MCS;
1955 }
1956
1957 static inline bool
isl_format_is_hiz(enum isl_format fmt)1958 isl_format_is_hiz(enum isl_format fmt)
1959 {
1960 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1961
1962 return fmtl->txc == ISL_TXC_HIZ;
1963 }
1964
1965 static inline bool
isl_format_is_planar(enum isl_format fmt)1966 isl_format_is_planar(enum isl_format fmt)
1967 {
1968 return fmt == ISL_FORMAT_PLANAR_420_8 ||
1969 fmt == ISL_FORMAT_PLANAR_420_10 ||
1970 fmt == ISL_FORMAT_PLANAR_420_12 ||
1971 fmt == ISL_FORMAT_PLANAR_420_16;
1972 }
1973
1974 static inline bool
isl_format_is_yuv(enum isl_format fmt)1975 isl_format_is_yuv(enum isl_format fmt)
1976 {
1977 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1978
1979 return fmtl->colorspace == ISL_COLORSPACE_YUV;
1980 }
1981
1982 static inline bool
isl_format_block_is_1x1x1(enum isl_format fmt)1983 isl_format_block_is_1x1x1(enum isl_format fmt)
1984 {
1985 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
1986
1987 return fmtl->bw == 1 && fmtl->bh == 1 && fmtl->bd == 1;
1988 }
1989
1990 static inline bool
isl_format_is_srgb(enum isl_format fmt)1991 isl_format_is_srgb(enum isl_format fmt)
1992 {
1993 return isl_format_get_layout(fmt)->colorspace == ISL_COLORSPACE_SRGB;
1994 }
1995
1996 enum isl_format isl_format_srgb_to_linear(enum isl_format fmt);
1997
1998 static inline bool
isl_format_is_rgb(enum isl_format fmt)1999 isl_format_is_rgb(enum isl_format fmt)
2000 {
2001 if (isl_format_is_yuv(fmt))
2002 return false;
2003
2004 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2005
2006 return fmtl->channels.r.bits > 0 &&
2007 fmtl->channels.g.bits > 0 &&
2008 fmtl->channels.b.bits > 0 &&
2009 fmtl->channels.a.bits == 0;
2010 }
2011
2012 static inline bool
isl_format_is_rgbx(enum isl_format fmt)2013 isl_format_is_rgbx(enum isl_format fmt)
2014 {
2015 const struct isl_format_layout *fmtl = isl_format_get_layout(fmt);
2016
2017 return fmtl->channels.r.bits > 0 &&
2018 fmtl->channels.g.bits > 0 &&
2019 fmtl->channels.b.bits > 0 &&
2020 fmtl->channels.a.bits > 0 &&
2021 fmtl->channels.a.type == ISL_VOID;
2022 }
2023
2024 enum isl_format isl_format_rgb_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
2025 enum isl_format isl_format_rgb_to_rgbx(enum isl_format rgb) ATTRIBUTE_CONST;
2026 enum isl_format isl_format_rgbx_to_rgba(enum isl_format rgb) ATTRIBUTE_CONST;
2027
2028 union isl_color_value
2029 isl_color_value_swizzle(union isl_color_value src,
2030 struct isl_swizzle swizzle,
2031 bool is_float);
2032
2033 union isl_color_value
2034 isl_color_value_swizzle_inv(union isl_color_value src,
2035 struct isl_swizzle swizzle);
2036
2037 void isl_color_value_pack(const union isl_color_value *value,
2038 enum isl_format format,
2039 uint32_t *data_out);
2040 void isl_color_value_unpack(union isl_color_value *value,
2041 enum isl_format format,
2042 const uint32_t *data_in);
2043
2044 bool isl_is_storage_image_format(enum isl_format fmt);
2045
2046 enum isl_format
2047 isl_lower_storage_image_format(const struct intel_device_info *devinfo,
2048 enum isl_format fmt);
2049
2050 /* Returns true if this hardware supports typed load/store on a format with
2051 * the same size as the given format.
2052 */
2053 bool
2054 isl_has_matching_typed_storage_image_format(const struct intel_device_info *devinfo,
2055 enum isl_format fmt);
2056
2057 void
2058 isl_tiling_get_info(enum isl_tiling tiling,
2059 enum isl_surf_dim dim,
2060 enum isl_msaa_layout msaa_layout,
2061 uint32_t format_bpb,
2062 uint32_t samples,
2063 struct isl_tile_info *tile_info);
2064
2065 static inline enum isl_tiling
isl_tiling_flag_to_enum(isl_tiling_flags_t flag)2066 isl_tiling_flag_to_enum(isl_tiling_flags_t flag)
2067 {
2068 assert(__builtin_popcount(flag) == 1);
2069 return (enum isl_tiling) (__builtin_ffs(flag) - 1);
2070 }
2071
2072 static inline bool
isl_tiling_is_any_y(enum isl_tiling tiling)2073 isl_tiling_is_any_y(enum isl_tiling tiling)
2074 {
2075 return (1u << tiling) & ISL_TILING_ANY_Y_MASK;
2076 }
2077
2078 static inline bool
isl_tiling_is_std_y(enum isl_tiling tiling)2079 isl_tiling_is_std_y(enum isl_tiling tiling)
2080 {
2081 return (1u << tiling) & ISL_TILING_STD_Y_MASK;
2082 }
2083
2084 uint32_t
2085 isl_tiling_to_i915_tiling(enum isl_tiling tiling);
2086
2087 enum isl_tiling
2088 isl_tiling_from_i915_tiling(uint32_t tiling);
2089
2090 /**
2091 * Return an isl_aux_op needed to enable an access to occur in an
2092 * isl_aux_state suitable for the isl_aux_usage.
2093 *
2094 * @note
2095 * If the access will invalidate the main surface, this function should not be
2096 * called and the isl_aux_op of NONE should be used instead. Otherwise, an
2097 * extra (but still lossless) ambiguate may occur.
2098 *
2099 * @invariant initial_state is possible with an isl_aux_usage compatible with
2100 * the given usage. Two usages are compatible if it's possible to
2101 * switch between them (e.g. CCS_E <-> CCS_D).
2102 * @invariant fast_clear is false if the aux doesn't support fast clears.
2103 */
2104 enum isl_aux_op
2105 isl_aux_prepare_access(enum isl_aux_state initial_state,
2106 enum isl_aux_usage usage,
2107 bool fast_clear_supported);
2108
2109 /**
2110 * Return the isl_aux_state entered after performing an isl_aux_op.
2111 *
2112 * @invariant initial_state is possible with the given usage.
2113 * @invariant op is possible with the given usage.
2114 * @invariant op must not cause HW to read from an invalid aux.
2115 */
2116 enum isl_aux_state
2117 isl_aux_state_transition_aux_op(enum isl_aux_state initial_state,
2118 enum isl_aux_usage usage,
2119 enum isl_aux_op op);
2120
2121 /**
2122 * Return the isl_aux_state entered after performing a write.
2123 *
2124 * @note
2125 * full_surface should be true if the write covers the entire slice. Setting
2126 * it to false in this case will still result in a correct (but imprecise) aux
2127 * state.
2128 *
2129 * @invariant if usage is not ISL_AUX_USAGE_NONE, then initial_state is
2130 * possible with the given usage.
2131 * @invariant usage can be ISL_AUX_USAGE_NONE iff:
2132 * * the main surface is valid, or
2133 * * the main surface is being invalidated/replaced.
2134 */
2135 enum isl_aux_state
2136 isl_aux_state_transition_write(enum isl_aux_state initial_state,
2137 enum isl_aux_usage usage,
2138 bool full_surface);
2139
2140 bool
2141 isl_aux_usage_has_fast_clears(enum isl_aux_usage usage);
2142
2143 bool
2144 isl_aux_usage_has_compression(enum isl_aux_usage usage);
2145
2146 static inline bool
isl_aux_usage_has_hiz(enum isl_aux_usage usage)2147 isl_aux_usage_has_hiz(enum isl_aux_usage usage)
2148 {
2149 return usage == ISL_AUX_USAGE_HIZ ||
2150 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
2151 usage == ISL_AUX_USAGE_HIZ_CCS;
2152 }
2153
2154 static inline bool
isl_aux_usage_has_mcs(enum isl_aux_usage usage)2155 isl_aux_usage_has_mcs(enum isl_aux_usage usage)
2156 {
2157 return usage == ISL_AUX_USAGE_MCS ||
2158 usage == ISL_AUX_USAGE_MCS_CCS;
2159 }
2160
2161 static inline bool
isl_aux_usage_has_ccs(enum isl_aux_usage usage)2162 isl_aux_usage_has_ccs(enum isl_aux_usage usage)
2163 {
2164 return usage == ISL_AUX_USAGE_CCS_D ||
2165 usage == ISL_AUX_USAGE_CCS_E ||
2166 usage == ISL_AUX_USAGE_GFX12_CCS_E ||
2167 usage == ISL_AUX_USAGE_MC ||
2168 usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
2169 usage == ISL_AUX_USAGE_HIZ_CCS ||
2170 usage == ISL_AUX_USAGE_MCS_CCS ||
2171 usage == ISL_AUX_USAGE_STC_CCS;
2172 }
2173
2174 static inline bool
isl_aux_state_has_valid_primary(enum isl_aux_state state)2175 isl_aux_state_has_valid_primary(enum isl_aux_state state)
2176 {
2177 return state == ISL_AUX_STATE_RESOLVED ||
2178 state == ISL_AUX_STATE_PASS_THROUGH ||
2179 state == ISL_AUX_STATE_AUX_INVALID;
2180 }
2181
2182 static inline bool
isl_aux_state_has_valid_aux(enum isl_aux_state state)2183 isl_aux_state_has_valid_aux(enum isl_aux_state state)
2184 {
2185 return state != ISL_AUX_STATE_AUX_INVALID;
2186 }
2187
2188 extern const struct isl_drm_modifier_info isl_drm_modifier_info_list[];
2189
2190 #define isl_drm_modifier_info_for_each(__info) \
2191 for (const struct isl_drm_modifier_info *__info = isl_drm_modifier_info_list; \
2192 __info->modifier != DRM_FORMAT_MOD_INVALID; \
2193 ++__info)
2194
2195 const struct isl_drm_modifier_info * ATTRIBUTE_CONST
2196 isl_drm_modifier_get_info(uint64_t modifier);
2197
2198 static inline bool
isl_drm_modifier_has_aux(uint64_t modifier)2199 isl_drm_modifier_has_aux(uint64_t modifier)
2200 {
2201 return isl_drm_modifier_get_info(modifier)->aux_usage != ISL_AUX_USAGE_NONE;
2202 }
2203
2204 /** Returns the default isl_aux_state for the given modifier.
2205 *
2206 * If we have a modifier which supports compression, then the auxiliary data
2207 * could be in state other than ISL_AUX_STATE_AUX_INVALID. In particular, it
2208 * can be in any of the following:
2209 *
2210 * - ISL_AUX_STATE_CLEAR
2211 * - ISL_AUX_STATE_PARTIAL_CLEAR
2212 * - ISL_AUX_STATE_COMPRESSED_CLEAR
2213 * - ISL_AUX_STATE_COMPRESSED_NO_CLEAR
2214 * - ISL_AUX_STATE_RESOLVED
2215 * - ISL_AUX_STATE_PASS_THROUGH
2216 *
2217 * If the modifier does not support fast-clears, then we are guaranteed
2218 * that the surface is at least partially resolved and the first three not
2219 * possible. We return ISL_AUX_STATE_COMPRESSED_CLEAR if the modifier
2220 * supports fast clears and ISL_AUX_STATE_COMPRESSED_NO_CLEAR if it does not
2221 * because they are the least common denominator of the set of possible aux
2222 * states and will yield a valid interpretation of the aux data.
2223 *
2224 * For modifiers with no aux support, ISL_AUX_STATE_AUX_INVALID is returned.
2225 */
2226 static inline enum isl_aux_state
isl_drm_modifier_get_default_aux_state(uint64_t modifier)2227 isl_drm_modifier_get_default_aux_state(uint64_t modifier)
2228 {
2229 const struct isl_drm_modifier_info *mod_info =
2230 isl_drm_modifier_get_info(modifier);
2231
2232 if (!mod_info || mod_info->aux_usage == ISL_AUX_USAGE_NONE)
2233 return ISL_AUX_STATE_AUX_INVALID;
2234
2235 assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E ||
2236 mod_info->aux_usage == ISL_AUX_USAGE_GFX12_CCS_E ||
2237 mod_info->aux_usage == ISL_AUX_USAGE_MC);
2238 return mod_info->supports_clear_color ? ISL_AUX_STATE_COMPRESSED_CLEAR :
2239 ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
2240 }
2241
2242 /**
2243 * Return the modifier's score, which indicates the driver's preference for the
2244 * modifier relative to others. A higher score is better. Zero means
2245 * unsupported.
2246 *
2247 * Intended to assist selection of a modifier from an externally provided list,
2248 * such as VkImageDrmFormatModifierListCreateInfoEXT.
2249 */
2250 uint32_t
2251 isl_drm_modifier_get_score(const struct intel_device_info *devinfo,
2252 uint64_t modifier);
2253
2254 struct isl_extent2d ATTRIBUTE_CONST
2255 isl_get_interleaved_msaa_px_size_sa(uint32_t samples);
2256
2257 static inline bool
isl_surf_usage_is_display(isl_surf_usage_flags_t usage)2258 isl_surf_usage_is_display(isl_surf_usage_flags_t usage)
2259 {
2260 return usage & ISL_SURF_USAGE_DISPLAY_BIT;
2261 }
2262
2263 static inline bool
isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)2264 isl_surf_usage_is_depth(isl_surf_usage_flags_t usage)
2265 {
2266 return usage & ISL_SURF_USAGE_DEPTH_BIT;
2267 }
2268
2269 static inline bool
isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)2270 isl_surf_usage_is_stencil(isl_surf_usage_flags_t usage)
2271 {
2272 return usage & ISL_SURF_USAGE_STENCIL_BIT;
2273 }
2274
2275 static inline bool
isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)2276 isl_surf_usage_is_depth_and_stencil(isl_surf_usage_flags_t usage)
2277 {
2278 return (usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2279 (usage & ISL_SURF_USAGE_STENCIL_BIT);
2280 }
2281
2282 static inline bool
isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)2283 isl_surf_usage_is_depth_or_stencil(isl_surf_usage_flags_t usage)
2284 {
2285 return usage & (ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_STENCIL_BIT);
2286 }
2287
2288 static inline bool
isl_surf_usage_is_cpb(isl_surf_usage_flags_t usage)2289 isl_surf_usage_is_cpb(isl_surf_usage_flags_t usage)
2290 {
2291 return usage & ISL_SURF_USAGE_CPB_BIT;
2292 }
2293
2294 static inline bool
isl_surf_info_is_z16(const struct isl_surf_init_info * info)2295 isl_surf_info_is_z16(const struct isl_surf_init_info *info)
2296 {
2297 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2298 (info->format == ISL_FORMAT_R16_UNORM);
2299 }
2300
2301 static inline bool
isl_surf_info_is_z32_float(const struct isl_surf_init_info * info)2302 isl_surf_info_is_z32_float(const struct isl_surf_init_info *info)
2303 {
2304 return (info->usage & ISL_SURF_USAGE_DEPTH_BIT) &&
2305 (info->format == ISL_FORMAT_R32_FLOAT);
2306 }
2307
2308 static inline struct isl_extent2d
isl_extent2d(uint32_t width,uint32_t height)2309 isl_extent2d(uint32_t width, uint32_t height)
2310 {
2311 struct isl_extent2d e = { { 0 } };
2312
2313 e.width = width;
2314 e.height = height;
2315
2316 return e;
2317 }
2318
2319 static inline struct isl_extent3d
isl_extent3d(uint32_t width,uint32_t height,uint32_t depth)2320 isl_extent3d(uint32_t width, uint32_t height, uint32_t depth)
2321 {
2322 struct isl_extent3d e = { { 0 } };
2323
2324 e.width = width;
2325 e.height = height;
2326 e.depth = depth;
2327
2328 return e;
2329 }
2330
2331 static inline struct isl_extent4d
isl_extent4d(uint32_t width,uint32_t height,uint32_t depth,uint32_t array_len)2332 isl_extent4d(uint32_t width, uint32_t height, uint32_t depth,
2333 uint32_t array_len)
2334 {
2335 struct isl_extent4d e = { { 0 } };
2336
2337 e.width = width;
2338 e.height = height;
2339 e.depth = depth;
2340 e.array_len = array_len;
2341
2342 return e;
2343 }
2344
2345 bool isl_color_value_is_zero(union isl_color_value value,
2346 enum isl_format format);
2347
2348 bool isl_color_value_is_zero_one(union isl_color_value value,
2349 enum isl_format format);
2350
2351 static inline bool
isl_swizzle_is_identity(struct isl_swizzle swizzle)2352 isl_swizzle_is_identity(struct isl_swizzle swizzle)
2353 {
2354 return swizzle.r == ISL_CHANNEL_SELECT_RED &&
2355 swizzle.g == ISL_CHANNEL_SELECT_GREEN &&
2356 swizzle.b == ISL_CHANNEL_SELECT_BLUE &&
2357 swizzle.a == ISL_CHANNEL_SELECT_ALPHA;
2358 }
2359
2360 static inline bool
isl_swizzle_is_identity_for_format(enum isl_format format,struct isl_swizzle swizzle)2361 isl_swizzle_is_identity_for_format(enum isl_format format,
2362 struct isl_swizzle swizzle)
2363 {
2364 const struct isl_format_layout *layout = isl_format_get_layout(format);
2365
2366 #define channel_id_or_zero(name, ID) \
2367 (swizzle.name == ISL_CHANNEL_SELECT_##ID || \
2368 layout->channels.name.bits == 0)
2369 return channel_id_or_zero(r, RED) &&
2370 channel_id_or_zero(g, GREEN) &&
2371 channel_id_or_zero(b, BLUE) &&
2372 channel_id_or_zero(a, ALPHA);
2373 #undef channel_id_or_zero
2374 }
2375
2376 bool
2377 isl_swizzle_supports_rendering(const struct intel_device_info *devinfo,
2378 struct isl_swizzle swizzle);
2379
2380 struct isl_swizzle
2381 isl_swizzle_compose(struct isl_swizzle first, struct isl_swizzle second);
2382 struct isl_swizzle
2383 isl_swizzle_invert(struct isl_swizzle swizzle);
2384
2385 uint32_t isl_mocs(const struct isl_device *dev, isl_surf_usage_flags_t usage,
2386 bool external);
2387
2388 #define isl_surf_init(dev, surf, ...) \
2389 isl_surf_init_s((dev), (surf), \
2390 &(struct isl_surf_init_info) { __VA_ARGS__ });
2391
2392 bool
2393 isl_surf_init_s(const struct isl_device *dev,
2394 struct isl_surf *surf,
2395 const struct isl_surf_init_info *restrict info);
2396
2397 void
2398 isl_surf_get_tile_info(const struct isl_surf *surf,
2399 struct isl_tile_info *tile_info);
2400
2401 /**
2402 * @param[in] surf The main surface
2403 * @param[in] hiz_or_mcs_surf HiZ or MCS surface associated with the main
2404 * surface
2405 * @returns true if the given surface supports CCS.
2406 */
2407 bool
2408 isl_surf_supports_ccs(const struct isl_device *dev,
2409 const struct isl_surf *surf,
2410 const struct isl_surf *hiz_or_mcs_surf);
2411
2412 /** Constructs a HiZ surface for the given main surface.
2413 *
2414 * @param[in] surf The main surface
2415 * @param[out] hiz_surf The HiZ surface to populate on success
2416 * @returns false if the main surface cannot support HiZ.
2417 */
2418 bool
2419 isl_surf_get_hiz_surf(const struct isl_device *dev,
2420 const struct isl_surf *surf,
2421 struct isl_surf *hiz_surf);
2422
2423 /** Constructs a MCS for the given main surface.
2424 *
2425 * @param[in] surf The main surface
2426 * @param[out] mcs_surf The MCS to populate on success
2427 * @returns false if the main surface cannot support MCS.
2428 */
2429 bool
2430 isl_surf_get_mcs_surf(const struct isl_device *dev,
2431 const struct isl_surf *surf,
2432 struct isl_surf *mcs_surf);
2433
2434 /** Constructs a CCS for the given main surface.
2435 *
2436 * @note
2437 * Starting with Tigerlake, the CCS is no longer really a surface. It's not
2438 * laid out as an independent surface and isn't referenced by
2439 * RENDER_SURFACE_STATE::"Auxiliary Surface Base Address" like other auxiliary
2440 * compression surfaces. It's a blob of memory that's a 1:256 scale-down from
2441 * the main surfaced that's attached side-band via a second set of page
2442 * tables.
2443 *
2444 * @par
2445 * In spite of this, it's sometimes useful to think of it as being a linear
2446 * buffer-like surface, at least for the purposes of allocation. When invoked
2447 * on Tigerlake or later, this function still works and produces such a linear
2448 * surface.
2449 *
2450 * @param[in] surf The main surface
2451 * @param[in] hiz_or_mcs_surf HiZ or MCS surface associated with the main
2452 * surface
2453 * @param[out] ccs_surf The CCS to populate on success
2454 * @param row_pitch_B: The row pitch for the CCS in bytes or 0 if
2455 * ISL should calculate the row pitch.
2456 * @returns false if the main surface cannot support CCS.
2457 */
2458 bool
2459 isl_surf_get_ccs_surf(const struct isl_device *dev,
2460 const struct isl_surf *surf,
2461 const struct isl_surf *hiz_or_mcs_surf,
2462 struct isl_surf *ccs_surf,
2463 uint32_t row_pitch_B);
2464
2465 #define isl_surf_fill_state(dev, state, ...) \
2466 isl_surf_fill_state_s((dev), (state), \
2467 &(struct isl_surf_fill_state_info) { __VA_ARGS__ });
2468
2469 void
2470 isl_surf_fill_state_s(const struct isl_device *dev, void *state,
2471 const struct isl_surf_fill_state_info *restrict info);
2472
2473 #define isl_buffer_fill_state(dev, state, ...) \
2474 isl_buffer_fill_state_s((dev), (state), \
2475 &(struct isl_buffer_fill_state_info) { __VA_ARGS__ });
2476
2477 void
2478 isl_buffer_fill_state_s(const struct isl_device *dev, void *state,
2479 const struct isl_buffer_fill_state_info *restrict info);
2480
2481 void
2482 isl_null_fill_state_s(const struct isl_device *dev, void *state,
2483 const struct isl_null_fill_state_info *restrict info);
2484
2485 #define isl_null_fill_state(dev, state, ...) \
2486 isl_null_fill_state_s((dev), (state), \
2487 &(struct isl_null_fill_state_info) { __VA_ARGS__ });
2488
2489 #define isl_emit_depth_stencil_hiz(dev, batch, ...) \
2490 isl_emit_depth_stencil_hiz_s((dev), (batch), \
2491 &(struct isl_depth_stencil_hiz_emit_info) { __VA_ARGS__ })
2492
2493 void
2494 isl_emit_depth_stencil_hiz_s(const struct isl_device *dev, void *batch,
2495 const struct isl_depth_stencil_hiz_emit_info *restrict info);
2496
2497 void
2498 isl_emit_cpb_control_s(const struct isl_device *dev, void *batch,
2499 const struct isl_cpb_emit_info *restrict info);
2500
2501 void
2502 isl_surf_fill_image_param(const struct isl_device *dev,
2503 struct brw_image_param *param,
2504 const struct isl_surf *surf,
2505 const struct isl_view *view);
2506
2507 void
2508 isl_buffer_fill_image_param(const struct isl_device *dev,
2509 struct brw_image_param *param,
2510 enum isl_format format,
2511 uint64_t size);
2512
2513 /**
2514 * Alignment of the upper-left sample of each subimage, in units of surface
2515 * elements.
2516 */
2517 static inline struct isl_extent3d
isl_surf_get_image_alignment_el(const struct isl_surf * surf)2518 isl_surf_get_image_alignment_el(const struct isl_surf *surf)
2519 {
2520 return surf->image_alignment_el;
2521 }
2522
2523 /**
2524 * Alignment of the upper-left sample of each subimage, in units of surface
2525 * samples.
2526 */
2527 static inline struct isl_extent3d
isl_surf_get_image_alignment_sa(const struct isl_surf * surf)2528 isl_surf_get_image_alignment_sa(const struct isl_surf *surf)
2529 {
2530 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2531
2532 return isl_extent3d(fmtl->bw * surf->image_alignment_el.w,
2533 fmtl->bh * surf->image_alignment_el.h,
2534 fmtl->bd * surf->image_alignment_el.d);
2535 }
2536
2537 /**
2538 * Logical extent of level 0 in units of surface elements.
2539 */
2540 static inline struct isl_extent4d
isl_surf_get_logical_level0_el(const struct isl_surf * surf)2541 isl_surf_get_logical_level0_el(const struct isl_surf *surf)
2542 {
2543 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2544
2545 return isl_extent4d(DIV_ROUND_UP(surf->logical_level0_px.w, fmtl->bw),
2546 DIV_ROUND_UP(surf->logical_level0_px.h, fmtl->bh),
2547 DIV_ROUND_UP(surf->logical_level0_px.d, fmtl->bd),
2548 surf->logical_level0_px.a);
2549 }
2550
2551 /**
2552 * Physical extent of level 0 in units of surface elements.
2553 */
2554 static inline struct isl_extent4d
isl_surf_get_phys_level0_el(const struct isl_surf * surf)2555 isl_surf_get_phys_level0_el(const struct isl_surf *surf)
2556 {
2557 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2558
2559 return isl_extent4d(DIV_ROUND_UP(surf->phys_level0_sa.w, fmtl->bw),
2560 DIV_ROUND_UP(surf->phys_level0_sa.h, fmtl->bh),
2561 DIV_ROUND_UP(surf->phys_level0_sa.d, fmtl->bd),
2562 surf->phys_level0_sa.a);
2563 }
2564
2565 /**
2566 * Pitch between vertically adjacent surface elements, in bytes.
2567 */
2568 static inline uint32_t
isl_surf_get_row_pitch_B(const struct isl_surf * surf)2569 isl_surf_get_row_pitch_B(const struct isl_surf *surf)
2570 {
2571 return surf->row_pitch_B;
2572 }
2573
2574 /**
2575 * Pitch between vertically adjacent surface elements, in units of surface elements.
2576 */
2577 static inline uint32_t
isl_surf_get_row_pitch_el(const struct isl_surf * surf)2578 isl_surf_get_row_pitch_el(const struct isl_surf *surf)
2579 {
2580 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2581
2582 assert(surf->row_pitch_B % (fmtl->bpb / 8) == 0);
2583 return surf->row_pitch_B / (fmtl->bpb / 8);
2584 }
2585
2586 /**
2587 * Pitch between physical array slices, in rows of surface elements.
2588 */
2589 static inline uint32_t
isl_surf_get_array_pitch_el_rows(const struct isl_surf * surf)2590 isl_surf_get_array_pitch_el_rows(const struct isl_surf *surf)
2591 {
2592 return surf->array_pitch_el_rows;
2593 }
2594
2595 /**
2596 * Pitch between physical array slices, in units of surface elements.
2597 */
2598 static inline uint32_t
isl_surf_get_array_pitch_el(const struct isl_surf * surf)2599 isl_surf_get_array_pitch_el(const struct isl_surf *surf)
2600 {
2601 return isl_surf_get_array_pitch_el_rows(surf) *
2602 isl_surf_get_row_pitch_el(surf);
2603 }
2604
2605 /**
2606 * Pitch between physical array slices, in rows of surface samples.
2607 */
2608 static inline uint32_t
isl_surf_get_array_pitch_sa_rows(const struct isl_surf * surf)2609 isl_surf_get_array_pitch_sa_rows(const struct isl_surf *surf)
2610 {
2611 const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format);
2612 return fmtl->bh * isl_surf_get_array_pitch_el_rows(surf);
2613 }
2614
2615 /**
2616 * Pitch between physical array slices, in bytes.
2617 */
2618 static inline uint32_t
isl_surf_get_array_pitch(const struct isl_surf * surf)2619 isl_surf_get_array_pitch(const struct isl_surf *surf)
2620 {
2621 return isl_surf_get_array_pitch_sa_rows(surf) * surf->row_pitch_B;
2622 }
2623
2624 /**
2625 * Calculate the offset, in units of surface samples, to a subimage in the
2626 * surface.
2627 *
2628 * @invariant level < surface levels
2629 * @invariant logical_array_layer < logical array length of surface
2630 * @invariant logical_z_offset_px < logical depth of surface at level
2631 */
2632 void
2633 isl_surf_get_image_offset_sa(const struct isl_surf *surf,
2634 uint32_t level,
2635 uint32_t logical_array_layer,
2636 uint32_t logical_z_offset_px,
2637 uint32_t *x_offset_sa,
2638 uint32_t *y_offset_sa,
2639 uint32_t *z_offset_sa,
2640 uint32_t *array_offset);
2641
2642 /**
2643 * Calculate the offset, in units of surface elements, to a subimage in the
2644 * surface.
2645 *
2646 * @invariant level < surface levels
2647 * @invariant logical_array_layer < logical array length of surface
2648 * @invariant logical_z_offset_px < logical depth of surface at level
2649 */
2650 void
2651 isl_surf_get_image_offset_el(const struct isl_surf *surf,
2652 uint32_t level,
2653 uint32_t logical_array_layer,
2654 uint32_t logical_z_offset_px,
2655 uint32_t *x_offset_el,
2656 uint32_t *y_offset_el,
2657 uint32_t *z_offset_el,
2658 uint32_t *array_offset);
2659
2660 /**
2661 * Calculate the offset, in bytes and intratile surface samples, to a
2662 * subimage in the surface.
2663 *
2664 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2665 * result to isl_tiling_get_intratile_offset_el, and converting the tile
2666 * offsets to samples.
2667 *
2668 * @invariant level < surface levels
2669 * @invariant logical_array_layer < logical array length of surface
2670 * @invariant logical_z_offset_px < logical depth of surface at level
2671 */
2672 void
2673 isl_surf_get_image_offset_B_tile_sa(const struct isl_surf *surf,
2674 uint32_t level,
2675 uint32_t logical_array_layer,
2676 uint32_t logical_z_offset_px,
2677 uint64_t *offset_B,
2678 uint32_t *x_offset_sa,
2679 uint32_t *y_offset_sa);
2680
2681 /**
2682 * Calculate the offset, in bytes and intratile surface elements, to a
2683 * subimage in the surface.
2684 *
2685 * This is equivalent to calling isl_surf_get_image_offset_el, passing the
2686 * result to isl_tiling_get_intratile_offset_el.
2687 *
2688 * @invariant level < surface levels
2689 * @invariant logical_array_layer < logical array length of surface
2690 * @invariant logical_z_offset_px < logical depth of surface at level
2691 */
2692 void
2693 isl_surf_get_image_offset_B_tile_el(const struct isl_surf *surf,
2694 uint32_t level,
2695 uint32_t logical_array_layer,
2696 uint32_t logical_z_offset_px,
2697 uint64_t *offset_B,
2698 uint32_t *x_offset_el,
2699 uint32_t *y_offset_el);
2700
2701 /**
2702 * Calculate the range in bytes occupied by a subimage, to the nearest tile.
2703 *
2704 * The range returned will be the smallest memory range in which the give
2705 * subimage fits, rounded to even tiles. Intel images do not usually have a
2706 * direct subimage -> range mapping so the range returned may contain data
2707 * from other sub-images. The returned range is a half-open interval where
2708 * all of the addresses within the subimage are < end_tile_B.
2709 *
2710 * @invariant level < surface levels
2711 * @invariant logical_array_layer < logical array length of surface
2712 * @invariant logical_z_offset_px < logical depth of surface at level
2713 */
2714 void
2715 isl_surf_get_image_range_B_tile(const struct isl_surf *surf,
2716 uint32_t level,
2717 uint32_t logical_array_layer,
2718 uint32_t logical_z_offset_px,
2719 uint64_t *start_tile_B,
2720 uint64_t *end_tile_B);
2721
2722 /**
2723 * Create an isl_surf that represents a particular subimage in the surface.
2724 *
2725 * The newly created surface will have a single miplevel and array slice. The
2726 * surface lives at the returned byte and intratile offsets, in samples.
2727 *
2728 * It is safe to call this function with surf == image_surf.
2729 *
2730 * @invariant level < surface levels
2731 * @invariant logical_array_layer < logical array length of surface
2732 * @invariant logical_z_offset_px < logical depth of surface at level
2733 */
2734 void
2735 isl_surf_get_image_surf(const struct isl_device *dev,
2736 const struct isl_surf *surf,
2737 uint32_t level,
2738 uint32_t logical_array_layer,
2739 uint32_t logical_z_offset_px,
2740 struct isl_surf *image_surf,
2741 uint64_t *offset_B,
2742 uint32_t *x_offset_sa,
2743 uint32_t *y_offset_sa);
2744
2745 /**
2746 * Create an isl_surf that is an uncompressed view of a compressed isl_surf
2747 *
2748 * The incoming surface must have a compressed format. The incoming view must
2749 * be a valid view for the given surface with the exception that it's format
2750 * is an umcompressed format with the same bpb as the surface format. The
2751 * incoming view must have isl_view::levels == 1.
2752 *
2753 * When the function returns, the resulting combination of uncompressed_surf
2754 * and uncompressed_view will be a valid view giving an uncompressed view of
2755 * the incoming surface. Depending on tiling, uncompressed_surf may have a
2756 * different isl_surf::dim from surf and uncompressed_view may or may not have
2757 * a zero base_array_layer. For legacy tiling (not Yf or Ys), an intratile
2758 * offset is returned in x_offset_sa and y_offset_sa. For standard Y tilings
2759 * (Yf and Ys), x_offset_sa and y_offset_sa will be set to zero.
2760 *
2761 * It is safe to call this function with surf == uncompressed_surf and
2762 * view == uncompressed_view.
2763 */
2764 bool MUST_CHECK
2765 isl_surf_get_uncompressed_surf(const struct isl_device *dev,
2766 const struct isl_surf *surf,
2767 const struct isl_view *view,
2768 struct isl_surf *uncompressed_surf,
2769 struct isl_view *uncompressed_view,
2770 uint64_t *offset_B,
2771 uint32_t *x_offset_el,
2772 uint32_t *y_offset_el);
2773
2774 /**
2775 * Calculate the intratile offsets to a surface coordinate, in elements.
2776 *
2777 * This function takes a coordinate in global tile space and returns the byte
2778 * offset to the specific tile as well as the offset within that tile to the
2779 * given coordinate in tile space. The returned x/y/z/array offsets are
2780 * guaranteed to lie within the tile.
2781 *
2782 * @param[in] tiling The tiling of the surface
2783 * @param[in] bpb The size of the surface format in bits per
2784 * block
2785 * @param[in] array_pitch_el_rows The array pitch of the surface for flat 2D
2786 * tilings such as ISL_TILING_Y0
2787 * @param[in] total_x_offset_el The X offset in tile space, in elements
2788 * @param[in] total_y_offset_el The Y offset in tile space, in elements
2789 * @param[in] total_z_offset_el The Z offset in tile space, in elements
2790 * @param[in] total_array_offset The array offset in tile space
2791 * @param[out] tile_offset_B The returned byte offset to the tile
2792 * @param[out] x_offset_el The X offset within the tile, in elements
2793 * @param[out] y_offset_el The Y offset within the tile, in elements
2794 * @param[out] z_offset_el The Z offset within the tile, in elements
2795 * @param[out] array_offset The array offset within the tile
2796 */
2797 void
2798 isl_tiling_get_intratile_offset_el(enum isl_tiling tiling,
2799 enum isl_surf_dim dim,
2800 enum isl_msaa_layout msaa_layout,
2801 uint32_t bpb,
2802 uint32_t samples,
2803 uint32_t row_pitch_B,
2804 uint32_t array_pitch_el_rows,
2805 uint32_t total_x_offset_el,
2806 uint32_t total_y_offset_el,
2807 uint32_t total_z_offset_el,
2808 uint32_t total_array_offset,
2809 uint64_t *tile_offset_B,
2810 uint32_t *x_offset_el,
2811 uint32_t *y_offset_el,
2812 uint32_t *z_offset_el,
2813 uint32_t *array_offset);
2814
2815 /**
2816 * Calculate the intratile offsets to a surface coordinate, in samples.
2817 *
2818 * This function takes a coordinate in global tile space and returns the byte
2819 * offset to the specific tile as well as the offset within that tile to the
2820 * given coordinate in tile space. The returned x/y/z/array offsets are
2821 * guaranteed to lie within the tile.
2822 *
2823 * @param[in] tiling The tiling of the surface
2824 * @param[in] bpb The size of the surface format in bits per
2825 * block
2826 * @param[in] array_pitch_el_rows The array pitch of the surface for flat 2D
2827 * tilings such as ISL_TILING_Y0
2828 * @param[in] total_x_offset_sa The X offset in tile space, in samples
2829 * @param[in] total_y_offset_sa The Y offset in tile space, in samples
2830 * @param[in] total_z_offset_sa The Z offset in tile space, in samples
2831 * @param[in] total_array_offset The array offset in tile space
2832 * @param[out] tile_offset_B The returned byte offset to the tile
2833 * @param[out] x_offset_sa The X offset within the tile, in samples
2834 * @param[out] y_offset_sa The Y offset within the tile, in samples
2835 * @param[out] z_offset_sa The Z offset within the tile, in samples
2836 * @param[out] array_offset The array offset within the tile
2837 */
2838 static inline void
isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,enum isl_surf_dim dim,enum isl_msaa_layout msaa_layout,enum isl_format format,uint32_t samples,uint32_t row_pitch_B,uint32_t array_pitch_el_rows,uint32_t total_x_offset_sa,uint32_t total_y_offset_sa,uint32_t total_z_offset_sa,uint32_t total_array_offset,uint64_t * tile_offset_B,uint32_t * x_offset_sa,uint32_t * y_offset_sa,uint32_t * z_offset_sa,uint32_t * array_offset)2839 isl_tiling_get_intratile_offset_sa(enum isl_tiling tiling,
2840 enum isl_surf_dim dim,
2841 enum isl_msaa_layout msaa_layout,
2842 enum isl_format format,
2843 uint32_t samples,
2844 uint32_t row_pitch_B,
2845 uint32_t array_pitch_el_rows,
2846 uint32_t total_x_offset_sa,
2847 uint32_t total_y_offset_sa,
2848 uint32_t total_z_offset_sa,
2849 uint32_t total_array_offset,
2850 uint64_t *tile_offset_B,
2851 uint32_t *x_offset_sa,
2852 uint32_t *y_offset_sa,
2853 uint32_t *z_offset_sa,
2854 uint32_t *array_offset)
2855 {
2856 const struct isl_format_layout *fmtl = isl_format_get_layout(format);
2857
2858 /* For computing the intratile offsets, we actually want a strange unit
2859 * which is samples for multisampled surfaces but elements for compressed
2860 * surfaces.
2861 */
2862 assert(total_x_offset_sa % fmtl->bw == 0);
2863 assert(total_y_offset_sa % fmtl->bh == 0);
2864 assert(total_z_offset_sa % fmtl->bd == 0);
2865 const uint32_t total_x_offset_el = total_x_offset_sa / fmtl->bw;
2866 const uint32_t total_y_offset_el = total_y_offset_sa / fmtl->bh;
2867 const uint32_t total_z_offset_el = total_z_offset_sa / fmtl->bd;
2868
2869 isl_tiling_get_intratile_offset_el(tiling, dim, msaa_layout, fmtl->bpb,
2870 samples, row_pitch_B,
2871 array_pitch_el_rows,
2872 total_x_offset_el,
2873 total_y_offset_el,
2874 total_z_offset_el,
2875 total_array_offset,
2876 tile_offset_B,
2877 x_offset_sa, y_offset_sa,
2878 z_offset_sa, array_offset);
2879 *x_offset_sa *= fmtl->bw;
2880 *y_offset_sa *= fmtl->bh;
2881 *z_offset_sa *= fmtl->bd;
2882 }
2883
2884 /**
2885 * @brief Get value of 3DSTATE_DEPTH_BUFFER.SurfaceFormat
2886 *
2887 * @pre surf->usage has ISL_SURF_USAGE_DEPTH_BIT
2888 * @pre surf->format must be a valid format for depth surfaces
2889 */
2890 uint32_t
2891 isl_surf_get_depth_format(const struct isl_device *dev,
2892 const struct isl_surf *surf);
2893
2894 /**
2895 * @brief performs a copy from linear to tiled surface
2896 *
2897 */
2898 void
2899 isl_memcpy_linear_to_tiled(uint32_t xt1, uint32_t xt2,
2900 uint32_t yt1, uint32_t yt2,
2901 char *dst, const char *src,
2902 uint32_t dst_pitch, int32_t src_pitch,
2903 bool has_swizzling,
2904 enum isl_tiling tiling,
2905 isl_memcpy_type copy_type);
2906
2907 /**
2908 * @brief performs a copy from tiled to linear surface
2909 *
2910 */
2911 void
2912 isl_memcpy_tiled_to_linear(uint32_t xt1, uint32_t xt2,
2913 uint32_t yt1, uint32_t yt2,
2914 char *dst, const char *src,
2915 int32_t dst_pitch, uint32_t src_pitch,
2916 bool has_swizzling,
2917 enum isl_tiling tiling,
2918 isl_memcpy_type copy_type);
2919
2920 /**
2921 * @brief computes the tile_w (in bytes) and tile_h (in rows) of
2922 * different tiling patterns.
2923 */
2924 static inline void
isl_get_tile_dims(enum isl_tiling tiling,uint32_t cpp,uint32_t * tile_w,uint32_t * tile_h)2925 isl_get_tile_dims(enum isl_tiling tiling, uint32_t cpp,
2926 uint32_t *tile_w, uint32_t *tile_h)
2927 {
2928 switch (tiling) {
2929 case ISL_TILING_X:
2930 *tile_w = 512;
2931 *tile_h = 8;
2932 break;
2933 case ISL_TILING_Y0:
2934 *tile_w = 128;
2935 *tile_h = 32;
2936 break;
2937 case ISL_TILING_LINEAR:
2938 *tile_w = cpp;
2939 *tile_h = 1;
2940 break;
2941 default:
2942 unreachable("not reached");
2943 }
2944 }
2945
2946 /**
2947 * @brief Computes masks that may be used to select the bits of the X
2948 * and Y coordinates that indicate the offset within a tile. If the BO is
2949 * untiled, the masks are set to 0.
2950 */
2951 static inline void
isl_get_tile_masks(enum isl_tiling tiling,uint32_t cpp,uint32_t * mask_x,uint32_t * mask_y)2952 isl_get_tile_masks(enum isl_tiling tiling, uint32_t cpp,
2953 uint32_t *mask_x, uint32_t *mask_y)
2954 {
2955 uint32_t tile_w_bytes, tile_h;
2956
2957 isl_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h);
2958
2959 *mask_x = tile_w_bytes / cpp - 1;
2960 *mask_y = tile_h - 1;
2961 }
2962
2963 const char *
2964 isl_aux_op_to_name(enum isl_aux_op op);
2965
2966 #ifdef __cplusplus
2967 }
2968 #endif
2969
2970 #endif /* ISL_H */
2971