| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIFixupVectorISel.cpp | 87 unsigned &IndexReg, in findSRegBaseAndIndex()
176 unsigned IndexReg = 0; in fixupGlobalSaddr() local
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 286 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintLeaMemReference() local
352 const MachineOperand &IndexReg = MI->getOperand(OpNo + X86::AddrIndexReg); in PrintIntelMemReference() local
|
| D | X86FixupLEAs.cpp | 369 Register IndexReg = Index.getReg(); in optTwoAddrLEA() local
549 Register IndexReg = Index.getReg(); in processInstrForSlow3OpLEA() local
|
| D | X86InsertPrefetch.cpp | 83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg(); in IsMemOpCompatibleWithPrefetch() local
|
| D | X86InstrBuilder.h | 54 unsigned IndexReg; member
|
| D | X86SpeculativeLoadHardening.cpp | 1719 unsigned BaseReg = 0, IndexReg = 0; in tracePredStateThroughBlocksAndHarden() local
|
| D | X86FastISel.cpp | 904 unsigned IndexReg = AM.IndexReg; in X86SelectAddress() local
3961 unsigned IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI() local
|
| D | X86MCInstLower.cpp | 1062 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in EmitNop() local
|
| D | X86ISelDAGToDAG.cpp | 66 SDValue IndexReg; member
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 187 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is16BitMemOperand() local
206 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is32BitMemOperand() local
228 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in is64BitMemOperand() local
377 const MCOperand &IndexReg = MI.getOperand(Op + X86::AddrIndexReg); in emitMemModRMByte() local
|
| D | X86ATTInstPrinter.cpp | 389 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference() local
|
| D | X86IntelInstPrinter.cpp | 348 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); in printMemReference() local
|
| D | X86MCTargetDesc.cpp | 532 const MCOperand &IndexReg = Inst.getOperand(MemOpStart + X86::AddrIndexReg); in evaluateMemoryOperandAddress() local
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 345 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anonbe453f560111::X86AsmParser::IntelExprStateMachine
1043 static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg, in CheckBaseRegAndIndexRegAndScale()
1409 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, in CreateMemForInlineAsm()
1971 unsigned IndexReg = SM.getIndexReg(); in ParseIntelOperand() local
2294 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseMemOperand() local
|
| D | X86Operand.h | 63 unsigned IndexReg; member
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 425 unsigned &IndexReg) { in PPCSimplifyAddress()
510 unsigned IndexReg = 0; in PPCEmitLoad() local
659 unsigned IndexReg = 0; in PPCEmitStore() local
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/MCParser/ |
| D | MCTargetAsmParser.h | 68 StringRef IndexReg; member
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 264 Register IndexReg) { in buildBrJT()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 845 bool IndexReg; member
6949 Register IndexReg = MI.getOperand(3).getReg(); in emitCondStore() local
|