1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the interfaces that Sparc uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "SparcISelLowering.h"
15 #include "MCTargetDesc/SparcMCExpr.h"
16 #include "SparcMachineFunctionInfo.h"
17 #include "SparcRegisterInfo.h"
18 #include "SparcTargetMachine.h"
19 #include "SparcTargetObjectFile.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Module.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/KnownBits.h"
34 using namespace llvm;
35
36
37 //===----------------------------------------------------------------------===//
38 // Calling Convention Implementation
39 //===----------------------------------------------------------------------===//
40
CC_Sparc_Assign_SRet(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)41 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
42 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
43 ISD::ArgFlagsTy &ArgFlags, CCState &State)
44 {
45 assert (ArgFlags.isSRet());
46
47 // Assign SRet argument.
48 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
49 0,
50 LocVT, LocInfo));
51 return true;
52 }
53
CC_Sparc_Assign_Split_64(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)54 static bool CC_Sparc_Assign_Split_64(unsigned &ValNo, MVT &ValVT,
55 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
56 ISD::ArgFlagsTy &ArgFlags, CCState &State)
57 {
58 static const MCPhysReg RegList[] = {
59 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
60 };
61 // Try to get first reg.
62 if (unsigned Reg = State.AllocateReg(RegList)) {
63 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
64 } else {
65 // Assign whole thing in stack.
66 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
67 State.AllocateStack(8,4),
68 LocVT, LocInfo));
69 return true;
70 }
71
72 // Try to get second reg.
73 if (unsigned Reg = State.AllocateReg(RegList))
74 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
75 else
76 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
77 State.AllocateStack(4,4),
78 LocVT, LocInfo));
79 return true;
80 }
81
CC_Sparc_Assign_Ret_Split_64(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)82 static bool CC_Sparc_Assign_Ret_Split_64(unsigned &ValNo, MVT &ValVT,
83 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
84 ISD::ArgFlagsTy &ArgFlags, CCState &State)
85 {
86 static const MCPhysReg RegList[] = {
87 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
88 };
89
90 // Try to get first reg.
91 if (unsigned Reg = State.AllocateReg(RegList))
92 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
93 else
94 return false;
95
96 // Try to get second reg.
97 if (unsigned Reg = State.AllocateReg(RegList))
98 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
99 else
100 return false;
101
102 return true;
103 }
104
105 // Allocate a full-sized argument for the 64-bit ABI.
CC_Sparc64_Full(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)106 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
107 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
108 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
109 assert((LocVT == MVT::f32 || LocVT == MVT::f128
110 || LocVT.getSizeInBits() == 64) &&
111 "Can't handle non-64 bits locations");
112
113 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
114 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
115 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
116 unsigned Offset = State.AllocateStack(size, alignment);
117 unsigned Reg = 0;
118
119 if (LocVT == MVT::i64 && Offset < 6*8)
120 // Promote integers to %i0-%i5.
121 Reg = SP::I0 + Offset/8;
122 else if (LocVT == MVT::f64 && Offset < 16*8)
123 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
124 Reg = SP::D0 + Offset/8;
125 else if (LocVT == MVT::f32 && Offset < 16*8)
126 // Promote floats to %f1, %f3, ...
127 Reg = SP::F1 + Offset/4;
128 else if (LocVT == MVT::f128 && Offset < 16*8)
129 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
130 Reg = SP::Q0 + Offset/16;
131
132 // Promote to register when possible, otherwise use the stack slot.
133 if (Reg) {
134 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
135 return true;
136 }
137
138 // This argument goes on the stack in an 8-byte slot.
139 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
140 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
141 if (LocVT == MVT::f32)
142 Offset += 4;
143
144 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
145 return true;
146 }
147
148 // Allocate a half-sized argument for the 64-bit ABI.
149 //
150 // This is used when passing { float, int } structs by value in registers.
CC_Sparc64_Half(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)151 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
152 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
153 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
154 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
155 unsigned Offset = State.AllocateStack(4, 4);
156
157 if (LocVT == MVT::f32 && Offset < 16*8) {
158 // Promote floats to %f0-%f31.
159 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
160 LocVT, LocInfo));
161 return true;
162 }
163
164 if (LocVT == MVT::i32 && Offset < 6*8) {
165 // Promote integers to %i0-%i5, using half the register.
166 unsigned Reg = SP::I0 + Offset/8;
167 LocVT = MVT::i64;
168 LocInfo = CCValAssign::AExt;
169
170 // Set the Custom bit if this i32 goes in the high bits of a register.
171 if (Offset % 8 == 0)
172 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
173 LocVT, LocInfo));
174 else
175 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
176 return true;
177 }
178
179 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
180 return true;
181 }
182
183 #include "SparcGenCallingConv.inc"
184
185 // The calling conventions in SparcCallingConv.td are described in terms of the
186 // callee's register window. This function translates registers to the
187 // corresponding caller window %o register.
toCallerWindow(unsigned Reg)188 static unsigned toCallerWindow(unsigned Reg) {
189 static_assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7,
190 "Unexpected enum");
191 if (Reg >= SP::I0 && Reg <= SP::I7)
192 return Reg - SP::I0 + SP::O0;
193 return Reg;
194 }
195
196 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & DL,SelectionDAG & DAG) const197 SparcTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
198 bool IsVarArg,
199 const SmallVectorImpl<ISD::OutputArg> &Outs,
200 const SmallVectorImpl<SDValue> &OutVals,
201 const SDLoc &DL, SelectionDAG &DAG) const {
202 if (Subtarget->is64Bit())
203 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
204 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
205 }
206
207 SDValue
LowerReturn_32(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & DL,SelectionDAG & DAG) const208 SparcTargetLowering::LowerReturn_32(SDValue Chain, CallingConv::ID CallConv,
209 bool IsVarArg,
210 const SmallVectorImpl<ISD::OutputArg> &Outs,
211 const SmallVectorImpl<SDValue> &OutVals,
212 const SDLoc &DL, SelectionDAG &DAG) const {
213 MachineFunction &MF = DAG.getMachineFunction();
214
215 // CCValAssign - represent the assignment of the return value to locations.
216 SmallVector<CCValAssign, 16> RVLocs;
217
218 // CCState - Info about the registers and stack slot.
219 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
220 *DAG.getContext());
221
222 // Analyze return values.
223 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
224
225 SDValue Flag;
226 SmallVector<SDValue, 4> RetOps(1, Chain);
227 // Make room for the return address offset.
228 RetOps.push_back(SDValue());
229
230 // Copy the result values into the output registers.
231 for (unsigned i = 0, realRVLocIdx = 0;
232 i != RVLocs.size();
233 ++i, ++realRVLocIdx) {
234 CCValAssign &VA = RVLocs[i];
235 assert(VA.isRegLoc() && "Can only return in registers!");
236
237 SDValue Arg = OutVals[realRVLocIdx];
238
239 if (VA.needsCustom()) {
240 assert(VA.getLocVT() == MVT::v2i32);
241 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
242 // happen by default if this wasn't a legal type)
243
244 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
245 Arg,
246 DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout())));
247 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32,
248 Arg,
249 DAG.getConstant(1, DL, getVectorIdxTy(DAG.getDataLayout())));
250
251 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part0, Flag);
252 Flag = Chain.getValue(1);
253 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
254 VA = RVLocs[++i]; // skip ahead to next loc
255 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Part1,
256 Flag);
257 } else
258 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
259
260 // Guarantee that all emitted copies are stuck together with flags.
261 Flag = Chain.getValue(1);
262 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
263 }
264
265 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
266 // If the function returns a struct, copy the SRetReturnReg to I0
267 if (MF.getFunction().hasStructRetAttr()) {
268 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
269 unsigned Reg = SFI->getSRetReturnReg();
270 if (!Reg)
271 llvm_unreachable("sret virtual register not created in the entry block");
272 auto PtrVT = getPointerTy(DAG.getDataLayout());
273 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, PtrVT);
274 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
275 Flag = Chain.getValue(1);
276 RetOps.push_back(DAG.getRegister(SP::I0, PtrVT));
277 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
278 }
279
280 RetOps[0] = Chain; // Update chain.
281 RetOps[1] = DAG.getConstant(RetAddrOffset, DL, MVT::i32);
282
283 // Add the flag if we have it.
284 if (Flag.getNode())
285 RetOps.push_back(Flag);
286
287 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
288 }
289
290 // Lower return values for the 64-bit ABI.
291 // Return values are passed the exactly the same way as function arguments.
292 SDValue
LowerReturn_64(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & DL,SelectionDAG & DAG) const293 SparcTargetLowering::LowerReturn_64(SDValue Chain, CallingConv::ID CallConv,
294 bool IsVarArg,
295 const SmallVectorImpl<ISD::OutputArg> &Outs,
296 const SmallVectorImpl<SDValue> &OutVals,
297 const SDLoc &DL, SelectionDAG &DAG) const {
298 // CCValAssign - represent the assignment of the return value to locations.
299 SmallVector<CCValAssign, 16> RVLocs;
300
301 // CCState - Info about the registers and stack slot.
302 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
303 *DAG.getContext());
304
305 // Analyze return values.
306 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
307
308 SDValue Flag;
309 SmallVector<SDValue, 4> RetOps(1, Chain);
310
311 // The second operand on the return instruction is the return address offset.
312 // The return address is always %i7+8 with the 64-bit ABI.
313 RetOps.push_back(DAG.getConstant(8, DL, MVT::i32));
314
315 // Copy the result values into the output registers.
316 for (unsigned i = 0; i != RVLocs.size(); ++i) {
317 CCValAssign &VA = RVLocs[i];
318 assert(VA.isRegLoc() && "Can only return in registers!");
319 SDValue OutVal = OutVals[i];
320
321 // Integer return values must be sign or zero extended by the callee.
322 switch (VA.getLocInfo()) {
323 case CCValAssign::Full: break;
324 case CCValAssign::SExt:
325 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
326 break;
327 case CCValAssign::ZExt:
328 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
329 break;
330 case CCValAssign::AExt:
331 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
332 break;
333 default:
334 llvm_unreachable("Unknown loc info!");
335 }
336
337 // The custom bit on an i32 return value indicates that it should be passed
338 // in the high bits of the register.
339 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
340 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
341 DAG.getConstant(32, DL, MVT::i32));
342
343 // The next value may go in the low bits of the same register.
344 // Handle both at once.
345 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
346 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
347 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
348 // Skip the next value, it's already done.
349 ++i;
350 }
351 }
352
353 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
354
355 // Guarantee that all emitted copies are stuck together with flags.
356 Flag = Chain.getValue(1);
357 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
358 }
359
360 RetOps[0] = Chain; // Update chain.
361
362 // Add the flag if we have it.
363 if (Flag.getNode())
364 RetOps.push_back(Flag);
365
366 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
367 }
368
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const369 SDValue SparcTargetLowering::LowerFormalArguments(
370 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
371 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
372 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
373 if (Subtarget->is64Bit())
374 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
375 DL, DAG, InVals);
376 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
377 DL, DAG, InVals);
378 }
379
380 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
381 /// passed in either one or two GPRs, including FP values. TODO: we should
382 /// pass FP values in FP registers for fastcc functions.
LowerFormalArguments_32(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const383 SDValue SparcTargetLowering::LowerFormalArguments_32(
384 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
385 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
386 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
387 MachineFunction &MF = DAG.getMachineFunction();
388 MachineRegisterInfo &RegInfo = MF.getRegInfo();
389 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
390
391 // Assign locations to all of the incoming arguments.
392 SmallVector<CCValAssign, 16> ArgLocs;
393 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
394 *DAG.getContext());
395 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
396
397 const unsigned StackOffset = 92;
398 bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
399
400 unsigned InIdx = 0;
401 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
402 CCValAssign &VA = ArgLocs[i];
403
404 if (Ins[InIdx].Flags.isSRet()) {
405 if (InIdx != 0)
406 report_fatal_error("sparc only supports sret on the first parameter");
407 // Get SRet from [%fp+64].
408 int FrameIdx = MF.getFrameInfo().CreateFixedObject(4, 64, true);
409 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
410 SDValue Arg =
411 DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
412 InVals.push_back(Arg);
413 continue;
414 }
415
416 if (VA.isRegLoc()) {
417 if (VA.needsCustom()) {
418 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
419
420 Register VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
421 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
422 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
423
424 assert(i+1 < e);
425 CCValAssign &NextVA = ArgLocs[++i];
426
427 SDValue LoVal;
428 if (NextVA.isMemLoc()) {
429 int FrameIdx = MF.getFrameInfo().
430 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
431 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
432 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
433 } else {
434 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
435 &SP::IntRegsRegClass);
436 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
437 }
438
439 if (IsLittleEndian)
440 std::swap(LoVal, HiVal);
441
442 SDValue WholeValue =
443 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
444 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue);
445 InVals.push_back(WholeValue);
446 continue;
447 }
448 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
449 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
450 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
451 if (VA.getLocVT() == MVT::f32)
452 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
453 else if (VA.getLocVT() != MVT::i32) {
454 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
455 DAG.getValueType(VA.getLocVT()));
456 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
457 }
458 InVals.push_back(Arg);
459 continue;
460 }
461
462 assert(VA.isMemLoc());
463
464 unsigned Offset = VA.getLocMemOffset()+StackOffset;
465 auto PtrVT = getPointerTy(DAG.getDataLayout());
466
467 if (VA.needsCustom()) {
468 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32);
469 // If it is double-word aligned, just load.
470 if (Offset % 8 == 0) {
471 int FI = MF.getFrameInfo().CreateFixedObject(8,
472 Offset,
473 true);
474 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
475 SDValue Load =
476 DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
477 InVals.push_back(Load);
478 continue;
479 }
480
481 int FI = MF.getFrameInfo().CreateFixedObject(4,
482 Offset,
483 true);
484 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
485 SDValue HiVal =
486 DAG.getLoad(MVT::i32, dl, Chain, FIPtr, MachinePointerInfo());
487 int FI2 = MF.getFrameInfo().CreateFixedObject(4,
488 Offset+4,
489 true);
490 SDValue FIPtr2 = DAG.getFrameIndex(FI2, PtrVT);
491
492 SDValue LoVal =
493 DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, MachinePointerInfo());
494
495 if (IsLittleEndian)
496 std::swap(LoVal, HiVal);
497
498 SDValue WholeValue =
499 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
500 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), WholeValue);
501 InVals.push_back(WholeValue);
502 continue;
503 }
504
505 int FI = MF.getFrameInfo().CreateFixedObject(4,
506 Offset,
507 true);
508 SDValue FIPtr = DAG.getFrameIndex(FI, PtrVT);
509 SDValue Load ;
510 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
511 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, MachinePointerInfo());
512 } else if (VA.getValVT() == MVT::f128) {
513 report_fatal_error("SPARCv8 does not handle f128 in calls; "
514 "pass indirectly");
515 } else {
516 // We shouldn't see any other value types here.
517 llvm_unreachable("Unexpected ValVT encountered in frame lowering.");
518 }
519 InVals.push_back(Load);
520 }
521
522 if (MF.getFunction().hasStructRetAttr()) {
523 // Copy the SRet Argument to SRetReturnReg.
524 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
525 unsigned Reg = SFI->getSRetReturnReg();
526 if (!Reg) {
527 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
528 SFI->setSRetReturnReg(Reg);
529 }
530 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
531 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
532 }
533
534 // Store remaining ArgRegs to the stack if this is a varargs function.
535 if (isVarArg) {
536 static const MCPhysReg ArgRegs[] = {
537 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
538 };
539 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
540 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
541 unsigned ArgOffset = CCInfo.getNextStackOffset();
542 if (NumAllocated == 6)
543 ArgOffset += StackOffset;
544 else {
545 assert(!ArgOffset);
546 ArgOffset = 68+4*NumAllocated;
547 }
548
549 // Remember the vararg offset for the va_start implementation.
550 FuncInfo->setVarArgsFrameOffset(ArgOffset);
551
552 std::vector<SDValue> OutChains;
553
554 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
555 Register VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
556 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
557 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
558
559 int FrameIdx = MF.getFrameInfo().CreateFixedObject(4, ArgOffset,
560 true);
561 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
562
563 OutChains.push_back(
564 DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, MachinePointerInfo()));
565 ArgOffset += 4;
566 }
567
568 if (!OutChains.empty()) {
569 OutChains.push_back(Chain);
570 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
571 }
572 }
573
574 return Chain;
575 }
576
577 // Lower formal arguments for the 64 bit ABI.
LowerFormalArguments_64(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const578 SDValue SparcTargetLowering::LowerFormalArguments_64(
579 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
580 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
581 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
582 MachineFunction &MF = DAG.getMachineFunction();
583
584 // Analyze arguments according to CC_Sparc64.
585 SmallVector<CCValAssign, 16> ArgLocs;
586 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
587 *DAG.getContext());
588 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
589
590 // The argument array begins at %fp+BIAS+128, after the register save area.
591 const unsigned ArgArea = 128;
592
593 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
594 CCValAssign &VA = ArgLocs[i];
595 if (VA.isRegLoc()) {
596 // This argument is passed in a register.
597 // All integer register arguments are promoted by the caller to i64.
598
599 // Create a virtual register for the promoted live-in value.
600 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
601 getRegClassFor(VA.getLocVT()));
602 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
603
604 // Get the high bits for i32 struct elements.
605 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
606 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
607 DAG.getConstant(32, DL, MVT::i32));
608
609 // The caller promoted the argument, so insert an Assert?ext SDNode so we
610 // won't promote the value again in this function.
611 switch (VA.getLocInfo()) {
612 case CCValAssign::SExt:
613 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
614 DAG.getValueType(VA.getValVT()));
615 break;
616 case CCValAssign::ZExt:
617 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
618 DAG.getValueType(VA.getValVT()));
619 break;
620 default:
621 break;
622 }
623
624 // Truncate the register down to the argument type.
625 if (VA.isExtInLoc())
626 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
627
628 InVals.push_back(Arg);
629 continue;
630 }
631
632 // The registers are exhausted. This argument was passed on the stack.
633 assert(VA.isMemLoc());
634 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
635 // beginning of the arguments area at %fp+BIAS+128.
636 unsigned Offset = VA.getLocMemOffset() + ArgArea;
637 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
638 // Adjust offset for extended arguments, SPARC is big-endian.
639 // The caller will have written the full slot with extended bytes, but we
640 // prefer our own extending loads.
641 if (VA.isExtInLoc())
642 Offset += 8 - ValSize;
643 int FI = MF.getFrameInfo().CreateFixedObject(ValSize, Offset, true);
644 InVals.push_back(
645 DAG.getLoad(VA.getValVT(), DL, Chain,
646 DAG.getFrameIndex(FI, getPointerTy(MF.getDataLayout())),
647 MachinePointerInfo::getFixedStack(MF, FI)));
648 }
649
650 if (!IsVarArg)
651 return Chain;
652
653 // This function takes variable arguments, some of which may have been passed
654 // in registers %i0-%i5. Variable floating point arguments are never passed
655 // in floating point registers. They go on %i0-%i5 or on the stack like
656 // integer arguments.
657 //
658 // The va_start intrinsic needs to know the offset to the first variable
659 // argument.
660 unsigned ArgOffset = CCInfo.getNextStackOffset();
661 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
662 // Skip the 128 bytes of register save area.
663 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
664 Subtarget->getStackPointerBias());
665
666 // Save the variable arguments that were passed in registers.
667 // The caller is required to reserve stack space for 6 arguments regardless
668 // of how many arguments were actually passed.
669 SmallVector<SDValue, 8> OutChains;
670 for (; ArgOffset < 6*8; ArgOffset += 8) {
671 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
672 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
673 int FI = MF.getFrameInfo().CreateFixedObject(8, ArgOffset + ArgArea, true);
674 auto PtrVT = getPointerTy(MF.getDataLayout());
675 OutChains.push_back(
676 DAG.getStore(Chain, DL, VArg, DAG.getFrameIndex(FI, PtrVT),
677 MachinePointerInfo::getFixedStack(MF, FI)));
678 }
679
680 if (!OutChains.empty())
681 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
682
683 return Chain;
684 }
685
686 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const687 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
688 SmallVectorImpl<SDValue> &InVals) const {
689 if (Subtarget->is64Bit())
690 return LowerCall_64(CLI, InVals);
691 return LowerCall_32(CLI, InVals);
692 }
693
hasReturnsTwiceAttr(SelectionDAG & DAG,SDValue Callee,ImmutableCallSite CS)694 static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
695 ImmutableCallSite CS) {
696 if (CS)
697 return CS.hasFnAttr(Attribute::ReturnsTwice);
698
699 const Function *CalleeFn = nullptr;
700 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
701 CalleeFn = dyn_cast<Function>(G->getGlobal());
702 } else if (ExternalSymbolSDNode *E =
703 dyn_cast<ExternalSymbolSDNode>(Callee)) {
704 const Function &Fn = DAG.getMachineFunction().getFunction();
705 const Module *M = Fn.getParent();
706 const char *CalleeName = E->getSymbol();
707 CalleeFn = M->getFunction(CalleeName);
708 }
709
710 if (!CalleeFn)
711 return false;
712 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
713 }
714
715 // Lower a call for the 32-bit ABI.
716 SDValue
LowerCall_32(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const717 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
718 SmallVectorImpl<SDValue> &InVals) const {
719 SelectionDAG &DAG = CLI.DAG;
720 SDLoc &dl = CLI.DL;
721 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
722 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
723 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
724 SDValue Chain = CLI.Chain;
725 SDValue Callee = CLI.Callee;
726 bool &isTailCall = CLI.IsTailCall;
727 CallingConv::ID CallConv = CLI.CallConv;
728 bool isVarArg = CLI.IsVarArg;
729
730 // Sparc target does not yet support tail call optimization.
731 isTailCall = false;
732
733 // Analyze operands of the call, assigning locations to each operand.
734 SmallVector<CCValAssign, 16> ArgLocs;
735 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
736 *DAG.getContext());
737 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
738
739 // Get the size of the outgoing arguments stack space requirement.
740 unsigned ArgsSize = CCInfo.getNextStackOffset();
741
742 // Keep stack frames 8-byte aligned.
743 ArgsSize = (ArgsSize+7) & ~7;
744
745 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
746
747 // Create local copies for byval args.
748 SmallVector<SDValue, 8> ByValArgs;
749 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
750 ISD::ArgFlagsTy Flags = Outs[i].Flags;
751 if (!Flags.isByVal())
752 continue;
753
754 SDValue Arg = OutVals[i];
755 unsigned Size = Flags.getByValSize();
756 unsigned Align = Flags.getByValAlign();
757
758 if (Size > 0U) {
759 int FI = MFI.CreateStackObject(Size, Align, false);
760 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
761 SDValue SizeNode = DAG.getConstant(Size, dl, MVT::i32);
762
763 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
764 false, // isVolatile,
765 (Size <= 32), // AlwaysInline if size <= 32,
766 false, // isTailCall
767 MachinePointerInfo(), MachinePointerInfo());
768 ByValArgs.push_back(FIPtr);
769 }
770 else {
771 SDValue nullVal;
772 ByValArgs.push_back(nullVal);
773 }
774 }
775
776 Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, dl);
777
778 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
779 SmallVector<SDValue, 8> MemOpChains;
780
781 const unsigned StackOffset = 92;
782 bool hasStructRetAttr = false;
783 unsigned SRetArgSize = 0;
784 // Walk the register/memloc assignments, inserting copies/loads.
785 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
786 i != e;
787 ++i, ++realArgIdx) {
788 CCValAssign &VA = ArgLocs[i];
789 SDValue Arg = OutVals[realArgIdx];
790
791 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
792
793 // Use local copy if it is a byval arg.
794 if (Flags.isByVal()) {
795 Arg = ByValArgs[byvalArgIdx++];
796 if (!Arg) {
797 continue;
798 }
799 }
800
801 // Promote the value if needed.
802 switch (VA.getLocInfo()) {
803 default: llvm_unreachable("Unknown loc info!");
804 case CCValAssign::Full: break;
805 case CCValAssign::SExt:
806 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
807 break;
808 case CCValAssign::ZExt:
809 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
810 break;
811 case CCValAssign::AExt:
812 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
813 break;
814 case CCValAssign::BCvt:
815 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
816 break;
817 }
818
819 if (Flags.isSRet()) {
820 assert(VA.needsCustom());
821 // store SRet argument in %sp+64
822 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
823 SDValue PtrOff = DAG.getIntPtrConstant(64, dl);
824 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
825 MemOpChains.push_back(
826 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
827 hasStructRetAttr = true;
828 // sret only allowed on first argument
829 assert(Outs[realArgIdx].OrigArgIndex == 0);
830 PointerType *Ty = cast<PointerType>(CLI.getArgs()[0].Ty);
831 Type *ElementTy = Ty->getElementType();
832 SRetArgSize = DAG.getDataLayout().getTypeAllocSize(ElementTy);
833 continue;
834 }
835
836 if (VA.needsCustom()) {
837 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
838
839 if (VA.isMemLoc()) {
840 unsigned Offset = VA.getLocMemOffset() + StackOffset;
841 // if it is double-word aligned, just store.
842 if (Offset % 8 == 0) {
843 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
844 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
845 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
846 MemOpChains.push_back(
847 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
848 continue;
849 }
850 }
851
852 if (VA.getLocVT() == MVT::f64) {
853 // Move from the float value from float registers into the
854 // integer registers.
855 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Arg))
856 Arg = bitcastConstantFPToInt(C, dl, DAG);
857 else
858 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg);
859 }
860
861 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
862 Arg,
863 DAG.getConstant(0, dl, getVectorIdxTy(DAG.getDataLayout())));
864 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
865 Arg,
866 DAG.getConstant(1, dl, getVectorIdxTy(DAG.getDataLayout())));
867
868 if (VA.isRegLoc()) {
869 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Part0));
870 assert(i+1 != e);
871 CCValAssign &NextVA = ArgLocs[++i];
872 if (NextVA.isRegLoc()) {
873 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Part1));
874 } else {
875 // Store the second part in stack.
876 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
877 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
878 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
879 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
880 MemOpChains.push_back(
881 DAG.getStore(Chain, dl, Part1, PtrOff, MachinePointerInfo()));
882 }
883 } else {
884 unsigned Offset = VA.getLocMemOffset() + StackOffset;
885 // Store the first part.
886 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
887 SDValue PtrOff = DAG.getIntPtrConstant(Offset, dl);
888 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
889 MemOpChains.push_back(
890 DAG.getStore(Chain, dl, Part0, PtrOff, MachinePointerInfo()));
891 // Store the second part.
892 PtrOff = DAG.getIntPtrConstant(Offset + 4, dl);
893 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
894 MemOpChains.push_back(
895 DAG.getStore(Chain, dl, Part1, PtrOff, MachinePointerInfo()));
896 }
897 continue;
898 }
899
900 // Arguments that can be passed on register must be kept at
901 // RegsToPass vector
902 if (VA.isRegLoc()) {
903 if (VA.getLocVT() != MVT::f32) {
904 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
905 continue;
906 }
907 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
908 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
909 continue;
910 }
911
912 assert(VA.isMemLoc());
913
914 // Create a store off the stack pointer for this argument.
915 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
916 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + StackOffset,
917 dl);
918 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
919 MemOpChains.push_back(
920 DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo()));
921 }
922
923
924 // Emit all stores, make sure the occur before any copies into physregs.
925 if (!MemOpChains.empty())
926 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
927
928 // Build a sequence of copy-to-reg nodes chained together with token
929 // chain and flag operands which copy the outgoing args into registers.
930 // The InFlag in necessary since all emitted instructions must be
931 // stuck together.
932 SDValue InFlag;
933 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
934 unsigned Reg = toCallerWindow(RegsToPass[i].first);
935 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
936 InFlag = Chain.getValue(1);
937 }
938
939 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
940
941 // If the callee is a GlobalAddress node (quite common, every direct call is)
942 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
943 // Likewise ExternalSymbol -> TargetExternalSymbol.
944 unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30 : 0;
945 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
946 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
947 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
948 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
949
950 // Returns a chain & a flag for retval copy to use
951 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
952 SmallVector<SDValue, 8> Ops;
953 Ops.push_back(Chain);
954 Ops.push_back(Callee);
955 if (hasStructRetAttr)
956 Ops.push_back(DAG.getTargetConstant(SRetArgSize, dl, MVT::i32));
957 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
958 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
959 RegsToPass[i].second.getValueType()));
960
961 // Add a register mask operand representing the call-preserved registers.
962 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
963 const uint32_t *Mask =
964 ((hasReturnsTwice)
965 ? TRI->getRTCallPreservedMask(CallConv)
966 : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
967 assert(Mask && "Missing call preserved mask for calling convention");
968 Ops.push_back(DAG.getRegisterMask(Mask));
969
970 if (InFlag.getNode())
971 Ops.push_back(InFlag);
972
973 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
974 InFlag = Chain.getValue(1);
975
976 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, dl, true),
977 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
978 InFlag = Chain.getValue(1);
979
980 // Assign locations to each value returned by this call.
981 SmallVector<CCValAssign, 16> RVLocs;
982 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
983 *DAG.getContext());
984
985 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
986
987 // Copy all of the result registers out of their specified physreg.
988 for (unsigned i = 0; i != RVLocs.size(); ++i) {
989 if (RVLocs[i].getLocVT() == MVT::v2i32) {
990 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32);
991 SDValue Lo = DAG.getCopyFromReg(
992 Chain, dl, toCallerWindow(RVLocs[i++].getLocReg()), MVT::i32, InFlag);
993 Chain = Lo.getValue(1);
994 InFlag = Lo.getValue(2);
995 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Lo,
996 DAG.getConstant(0, dl, MVT::i32));
997 SDValue Hi = DAG.getCopyFromReg(
998 Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), MVT::i32, InFlag);
999 Chain = Hi.getValue(1);
1000 InFlag = Hi.getValue(2);
1001 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Vec, Hi,
1002 DAG.getConstant(1, dl, MVT::i32));
1003 InVals.push_back(Vec);
1004 } else {
1005 Chain =
1006 DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
1007 RVLocs[i].getValVT(), InFlag)
1008 .getValue(1);
1009 InFlag = Chain.getValue(2);
1010 InVals.push_back(Chain.getValue(0));
1011 }
1012 }
1013
1014 return Chain;
1015 }
1016
1017 // FIXME? Maybe this could be a TableGen attribute on some registers and
1018 // this table could be generated automatically from RegInfo.
getRegisterByName(const char * RegName,LLT VT,const MachineFunction & MF) const1019 Register SparcTargetLowering::getRegisterByName(const char* RegName, LLT VT,
1020 const MachineFunction &MF) const {
1021 Register Reg = StringSwitch<unsigned>(RegName)
1022 .Case("i0", SP::I0).Case("i1", SP::I1).Case("i2", SP::I2).Case("i3", SP::I3)
1023 .Case("i4", SP::I4).Case("i5", SP::I5).Case("i6", SP::I6).Case("i7", SP::I7)
1024 .Case("o0", SP::O0).Case("o1", SP::O1).Case("o2", SP::O2).Case("o3", SP::O3)
1025 .Case("o4", SP::O4).Case("o5", SP::O5).Case("o6", SP::O6).Case("o7", SP::O7)
1026 .Case("l0", SP::L0).Case("l1", SP::L1).Case("l2", SP::L2).Case("l3", SP::L3)
1027 .Case("l4", SP::L4).Case("l5", SP::L5).Case("l6", SP::L6).Case("l7", SP::L7)
1028 .Case("g0", SP::G0).Case("g1", SP::G1).Case("g2", SP::G2).Case("g3", SP::G3)
1029 .Case("g4", SP::G4).Case("g5", SP::G5).Case("g6", SP::G6).Case("g7", SP::G7)
1030 .Default(0);
1031
1032 if (Reg)
1033 return Reg;
1034
1035 report_fatal_error("Invalid register name global variable");
1036 }
1037
1038 // Fixup floating point arguments in the ... part of a varargs call.
1039 //
1040 // The SPARC v9 ABI requires that floating point arguments are treated the same
1041 // as integers when calling a varargs function. This does not apply to the
1042 // fixed arguments that are part of the function's prototype.
1043 //
1044 // This function post-processes a CCValAssign array created by
1045 // AnalyzeCallOperands().
fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> & ArgLocs,ArrayRef<ISD::OutputArg> Outs)1046 static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1047 ArrayRef<ISD::OutputArg> Outs) {
1048 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1049 const CCValAssign &VA = ArgLocs[i];
1050 MVT ValTy = VA.getLocVT();
1051 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1052 // varargs functions.
1053 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1054 continue;
1055 // The fixed arguments to a varargs function still go in FP registers.
1056 if (Outs[VA.getValNo()].IsFixed)
1057 continue;
1058
1059 // This floating point argument should be reassigned.
1060 CCValAssign NewVA;
1061
1062 // Determine the offset into the argument array.
1063 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1064 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1065 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1066 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1067
1068 if (Offset < 6*8) {
1069 // This argument should go in %i0-%i5.
1070 unsigned IReg = SP::I0 + Offset/8;
1071 if (ValTy == MVT::f64)
1072 // Full register, just bitconvert into i64.
1073 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1074 IReg, MVT::i64, CCValAssign::BCvt);
1075 else {
1076 assert(ValTy == MVT::f128 && "Unexpected type!");
1077 // Full register, just bitconvert into i128 -- We will lower this into
1078 // two i64s in LowerCall_64.
1079 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(),
1080 IReg, MVT::i128, CCValAssign::BCvt);
1081 }
1082 } else {
1083 // This needs to go to memory, we're out of integer registers.
1084 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1085 Offset, VA.getLocVT(), VA.getLocInfo());
1086 }
1087 ArgLocs[i] = NewVA;
1088 }
1089 }
1090
1091 // Lower a call for the 64-bit ABI.
1092 SDValue
LowerCall_64(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const1093 SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1094 SmallVectorImpl<SDValue> &InVals) const {
1095 SelectionDAG &DAG = CLI.DAG;
1096 SDLoc DL = CLI.DL;
1097 SDValue Chain = CLI.Chain;
1098 auto PtrVT = getPointerTy(DAG.getDataLayout());
1099
1100 // Sparc target does not yet support tail call optimization.
1101 CLI.IsTailCall = false;
1102
1103 // Analyze operands of the call, assigning locations to each operand.
1104 SmallVector<CCValAssign, 16> ArgLocs;
1105 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1106 *DAG.getContext());
1107 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1108
1109 // Get the size of the outgoing arguments stack space requirement.
1110 // The stack offset computed by CC_Sparc64 includes all arguments.
1111 // Called functions expect 6 argument words to exist in the stack frame, used
1112 // or not.
1113 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1114
1115 // Keep stack frames 16-byte aligned.
1116 ArgsSize = alignTo(ArgsSize, 16);
1117
1118 // Varargs calls require special treatment.
1119 if (CLI.IsVarArg)
1120 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1121
1122 // Adjust the stack pointer to make room for the arguments.
1123 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1124 // with more than 6 arguments.
1125 Chain = DAG.getCALLSEQ_START(Chain, ArgsSize, 0, DL);
1126
1127 // Collect the set of registers to pass to the function and their values.
1128 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1129 // instruction.
1130 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1131
1132 // Collect chains from all the memory opeations that copy arguments to the
1133 // stack. They must follow the stack pointer adjustment above and precede the
1134 // call instruction itself.
1135 SmallVector<SDValue, 8> MemOpChains;
1136
1137 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1138 const CCValAssign &VA = ArgLocs[i];
1139 SDValue Arg = CLI.OutVals[i];
1140
1141 // Promote the value if needed.
1142 switch (VA.getLocInfo()) {
1143 default:
1144 llvm_unreachable("Unknown location info!");
1145 case CCValAssign::Full:
1146 break;
1147 case CCValAssign::SExt:
1148 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1149 break;
1150 case CCValAssign::ZExt:
1151 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1152 break;
1153 case CCValAssign::AExt:
1154 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1155 break;
1156 case CCValAssign::BCvt:
1157 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1158 // SPARC does not support i128 natively. Lower it into two i64, see below.
1159 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1160 || VA.getLocVT() != MVT::i128)
1161 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1162 break;
1163 }
1164
1165 if (VA.isRegLoc()) {
1166 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1167 && VA.getLocVT() == MVT::i128) {
1168 // Store and reload into the integer register reg and reg+1.
1169 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1170 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1171 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1172 SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset, DL);
1173 HiPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, HiPtrOff);
1174 SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8, DL);
1175 LoPtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, LoPtrOff);
1176
1177 // Store to %sp+BIAS+128+Offset
1178 SDValue Store =
1179 DAG.getStore(Chain, DL, Arg, HiPtrOff, MachinePointerInfo());
1180 // Load into Reg and Reg+1
1181 SDValue Hi64 =
1182 DAG.getLoad(MVT::i64, DL, Store, HiPtrOff, MachinePointerInfo());
1183 SDValue Lo64 =
1184 DAG.getLoad(MVT::i64, DL, Store, LoPtrOff, MachinePointerInfo());
1185 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()),
1186 Hi64));
1187 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1),
1188 Lo64));
1189 continue;
1190 }
1191
1192 // The custom bit on an i32 return value indicates that it should be
1193 // passed in the high bits of the register.
1194 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1195 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1196 DAG.getConstant(32, DL, MVT::i32));
1197
1198 // The next value may go in the low bits of the same register.
1199 // Handle both at once.
1200 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1201 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1202 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1203 CLI.OutVals[i+1]);
1204 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1205 // Skip the next value, it's already done.
1206 ++i;
1207 }
1208 }
1209 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1210 continue;
1211 }
1212
1213 assert(VA.isMemLoc());
1214
1215 // Create a store off the stack pointer for this argument.
1216 SDValue StackPtr = DAG.getRegister(SP::O6, PtrVT);
1217 // The argument area starts at %fp+BIAS+128 in the callee frame,
1218 // %sp+BIAS+128 in ours.
1219 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1220 Subtarget->getStackPointerBias() +
1221 128, DL);
1222 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
1223 MemOpChains.push_back(
1224 DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()));
1225 }
1226
1227 // Emit all stores, make sure they occur before the call.
1228 if (!MemOpChains.empty())
1229 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1230
1231 // Build a sequence of CopyToReg nodes glued together with token chain and
1232 // glue operands which copy the outgoing args into registers. The InGlue is
1233 // necessary since all emitted instructions must be stuck together in order
1234 // to pass the live physical registers.
1235 SDValue InGlue;
1236 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1237 Chain = DAG.getCopyToReg(Chain, DL,
1238 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1239 InGlue = Chain.getValue(1);
1240 }
1241
1242 // If the callee is a GlobalAddress node (quite common, every direct call is)
1243 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1244 // Likewise ExternalSymbol -> TargetExternalSymbol.
1245 SDValue Callee = CLI.Callee;
1246 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1247 unsigned TF = isPositionIndependent() ? SparcMCExpr::VK_Sparc_WPLT30 : 0;
1248 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1249 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF);
1250 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1251 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF);
1252
1253 // Build the operands for the call instruction itself.
1254 SmallVector<SDValue, 8> Ops;
1255 Ops.push_back(Chain);
1256 Ops.push_back(Callee);
1257 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1258 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1259 RegsToPass[i].second.getValueType()));
1260
1261 // Add a register mask operand representing the call-preserved registers.
1262 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1263 const uint32_t *Mask =
1264 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
1265 : TRI->getCallPreservedMask(DAG.getMachineFunction(),
1266 CLI.CallConv));
1267 assert(Mask && "Missing call preserved mask for calling convention");
1268 Ops.push_back(DAG.getRegisterMask(Mask));
1269
1270 // Make sure the CopyToReg nodes are glued to the call instruction which
1271 // consumes the registers.
1272 if (InGlue.getNode())
1273 Ops.push_back(InGlue);
1274
1275 // Now the call itself.
1276 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1277 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1278 InGlue = Chain.getValue(1);
1279
1280 // Revert the stack pointer immediately after the call.
1281 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, DL, true),
1282 DAG.getIntPtrConstant(0, DL, true), InGlue, DL);
1283 InGlue = Chain.getValue(1);
1284
1285 // Now extract the return values. This is more or less the same as
1286 // LowerFormalArguments_64.
1287
1288 // Assign locations to each value returned by this call.
1289 SmallVector<CCValAssign, 16> RVLocs;
1290 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1291 *DAG.getContext());
1292
1293 // Set inreg flag manually for codegen generated library calls that
1294 // return float.
1295 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && !CLI.CS)
1296 CLI.Ins[0].Flags.setInReg();
1297
1298 RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1299
1300 // Copy all of the result registers out of their specified physreg.
1301 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1302 CCValAssign &VA = RVLocs[i];
1303 unsigned Reg = toCallerWindow(VA.getLocReg());
1304
1305 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1306 // reside in the same register in the high and low bits. Reuse the
1307 // CopyFromReg previous node to avoid duplicate copies.
1308 SDValue RV;
1309 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1310 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1311 RV = Chain.getValue(0);
1312
1313 // But usually we'll create a new CopyFromReg for a different register.
1314 if (!RV.getNode()) {
1315 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1316 Chain = RV.getValue(1);
1317 InGlue = Chain.getValue(2);
1318 }
1319
1320 // Get the high bits for i32 struct elements.
1321 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1322 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1323 DAG.getConstant(32, DL, MVT::i32));
1324
1325 // The callee promoted the return value, so insert an Assert?ext SDNode so
1326 // we won't promote the value again in this function.
1327 switch (VA.getLocInfo()) {
1328 case CCValAssign::SExt:
1329 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1330 DAG.getValueType(VA.getValVT()));
1331 break;
1332 case CCValAssign::ZExt:
1333 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1334 DAG.getValueType(VA.getValVT()));
1335 break;
1336 default:
1337 break;
1338 }
1339
1340 // Truncate the register down to the return value type.
1341 if (VA.isExtInLoc())
1342 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1343
1344 InVals.push_back(RV);
1345 }
1346
1347 return Chain;
1348 }
1349
1350 //===----------------------------------------------------------------------===//
1351 // TargetLowering Implementation
1352 //===----------------------------------------------------------------------===//
1353
shouldExpandAtomicRMWInIR(AtomicRMWInst * AI) const1354 TargetLowering::AtomicExpansionKind SparcTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
1355 if (AI->getOperation() == AtomicRMWInst::Xchg &&
1356 AI->getType()->getPrimitiveSizeInBits() == 32)
1357 return AtomicExpansionKind::None; // Uses xchg instruction
1358
1359 return AtomicExpansionKind::CmpXChg;
1360 }
1361
1362 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1363 /// condition.
IntCondCCodeToICC(ISD::CondCode CC)1364 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1365 switch (CC) {
1366 default: llvm_unreachable("Unknown integer condition code!");
1367 case ISD::SETEQ: return SPCC::ICC_E;
1368 case ISD::SETNE: return SPCC::ICC_NE;
1369 case ISD::SETLT: return SPCC::ICC_L;
1370 case ISD::SETGT: return SPCC::ICC_G;
1371 case ISD::SETLE: return SPCC::ICC_LE;
1372 case ISD::SETGE: return SPCC::ICC_GE;
1373 case ISD::SETULT: return SPCC::ICC_CS;
1374 case ISD::SETULE: return SPCC::ICC_LEU;
1375 case ISD::SETUGT: return SPCC::ICC_GU;
1376 case ISD::SETUGE: return SPCC::ICC_CC;
1377 }
1378 }
1379
1380 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1381 /// FCC condition.
FPCondCCodeToFCC(ISD::CondCode CC)1382 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1383 switch (CC) {
1384 default: llvm_unreachable("Unknown fp condition code!");
1385 case ISD::SETEQ:
1386 case ISD::SETOEQ: return SPCC::FCC_E;
1387 case ISD::SETNE:
1388 case ISD::SETUNE: return SPCC::FCC_NE;
1389 case ISD::SETLT:
1390 case ISD::SETOLT: return SPCC::FCC_L;
1391 case ISD::SETGT:
1392 case ISD::SETOGT: return SPCC::FCC_G;
1393 case ISD::SETLE:
1394 case ISD::SETOLE: return SPCC::FCC_LE;
1395 case ISD::SETGE:
1396 case ISD::SETOGE: return SPCC::FCC_GE;
1397 case ISD::SETULT: return SPCC::FCC_UL;
1398 case ISD::SETULE: return SPCC::FCC_ULE;
1399 case ISD::SETUGT: return SPCC::FCC_UG;
1400 case ISD::SETUGE: return SPCC::FCC_UGE;
1401 case ISD::SETUO: return SPCC::FCC_U;
1402 case ISD::SETO: return SPCC::FCC_O;
1403 case ISD::SETONE: return SPCC::FCC_LG;
1404 case ISD::SETUEQ: return SPCC::FCC_UE;
1405 }
1406 }
1407
SparcTargetLowering(const TargetMachine & TM,const SparcSubtarget & STI)1408 SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
1409 const SparcSubtarget &STI)
1410 : TargetLowering(TM), Subtarget(&STI) {
1411 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize(0));
1412
1413 // Instructions which use registers as conditionals examine all the
1414 // bits (as does the pseudo SELECT_CC expansion). I don't think it
1415 // matters much whether it's ZeroOrOneBooleanContent, or
1416 // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
1417 // former.
1418 setBooleanContents(ZeroOrOneBooleanContent);
1419 setBooleanVectorContents(ZeroOrOneBooleanContent);
1420
1421 // Set up the register classes.
1422 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1423 if (!Subtarget->useSoftFloat()) {
1424 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1425 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1426 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1427 }
1428 if (Subtarget->is64Bit()) {
1429 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1430 } else {
1431 // On 32bit sparc, we define a double-register 32bit register
1432 // class, as well. This is modeled in LLVM as a 2-vector of i32.
1433 addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
1434
1435 // ...but almost all operations must be expanded, so set that as
1436 // the default.
1437 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
1438 setOperationAction(Op, MVT::v2i32, Expand);
1439 }
1440 // Truncating/extending stores/loads are also not supported.
1441 for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) {
1442 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Expand);
1443 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand);
1444 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Expand);
1445
1446 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, VT, Expand);
1447 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand);
1448 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, VT, Expand);
1449
1450 setTruncStoreAction(VT, MVT::v2i32, Expand);
1451 setTruncStoreAction(MVT::v2i32, VT, Expand);
1452 }
1453 // However, load and store *are* legal.
1454 setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
1455 setOperationAction(ISD::STORE, MVT::v2i32, Legal);
1456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
1457 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal);
1458
1459 // And we need to promote i64 loads/stores into vector load/store
1460 setOperationAction(ISD::LOAD, MVT::i64, Custom);
1461 setOperationAction(ISD::STORE, MVT::i64, Custom);
1462
1463 // Sadly, this doesn't work:
1464 // AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
1465 // AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
1466 }
1467
1468 // Turn FP extload into load/fpextend
1469 for (MVT VT : MVT::fp_valuetypes()) {
1470 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1471 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
1472 }
1473
1474 // Sparc doesn't have i1 sign extending load
1475 for (MVT VT : MVT::integer_valuetypes())
1476 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1477
1478 // Turn FP truncstore into trunc + store.
1479 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1480 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1481 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1482
1483 // Custom legalize GlobalAddress nodes into LO/HI parts.
1484 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
1485 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
1486 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
1487 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
1488
1489 // Sparc doesn't have sext_inreg, replace them with shl/sra
1490 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1491 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1492 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1493
1494 // Sparc has no REM or DIVREM operations.
1495 setOperationAction(ISD::UREM, MVT::i32, Expand);
1496 setOperationAction(ISD::SREM, MVT::i32, Expand);
1497 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1498 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1499
1500 // ... nor does SparcV9.
1501 if (Subtarget->is64Bit()) {
1502 setOperationAction(ISD::UREM, MVT::i64, Expand);
1503 setOperationAction(ISD::SREM, MVT::i64, Expand);
1504 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1505 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1506 }
1507
1508 // Custom expand fp<->sint
1509 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1510 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1511 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
1512 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
1513
1514 // Custom Expand fp<->uint
1515 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1516 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1517 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
1518 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
1519
1520 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1521 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1522
1523 // Sparc has no select or setcc: expand to SELECT_CC.
1524 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1525 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1526 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1527 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1528
1529 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1530 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1531 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1532 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1533
1534 // Sparc doesn't have BRCOND either, it has BR_CC.
1535 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1536 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1537 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1538 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1539 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1540 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1541 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1542
1543 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1544 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1545 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1546 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1547
1548 setOperationAction(ISD::ADDC, MVT::i32, Custom);
1549 setOperationAction(ISD::ADDE, MVT::i32, Custom);
1550 setOperationAction(ISD::SUBC, MVT::i32, Custom);
1551 setOperationAction(ISD::SUBE, MVT::i32, Custom);
1552
1553 if (Subtarget->is64Bit()) {
1554 setOperationAction(ISD::ADDC, MVT::i64, Custom);
1555 setOperationAction(ISD::ADDE, MVT::i64, Custom);
1556 setOperationAction(ISD::SUBC, MVT::i64, Custom);
1557 setOperationAction(ISD::SUBE, MVT::i64, Custom);
1558 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1559 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1560 setOperationAction(ISD::SELECT, MVT::i64, Expand);
1561 setOperationAction(ISD::SETCC, MVT::i64, Expand);
1562 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1563 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1564
1565 setOperationAction(ISD::CTPOP, MVT::i64,
1566 Subtarget->usePopc() ? Legal : Expand);
1567 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1568 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1569 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1570 setOperationAction(ISD::ROTL , MVT::i64, Expand);
1571 setOperationAction(ISD::ROTR , MVT::i64, Expand);
1572 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
1573 }
1574
1575 // ATOMICs.
1576 // Atomics are supported on SparcV9. 32-bit atomics are also
1577 // supported by some Leon SparcV8 variants. Otherwise, atomics
1578 // are unsupported.
1579 if (Subtarget->isV9())
1580 setMaxAtomicSizeInBitsSupported(64);
1581 else if (Subtarget->hasLeonCasa())
1582 setMaxAtomicSizeInBitsSupported(32);
1583 else
1584 setMaxAtomicSizeInBitsSupported(0);
1585
1586 setMinCmpXchgSizeInBits(32);
1587
1588 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
1589
1590 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
1591
1592 // Custom Lower Atomic LOAD/STORE
1593 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1594 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1595
1596 if (Subtarget->is64Bit()) {
1597 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
1598 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
1599 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
1600 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
1601 }
1602
1603 if (!Subtarget->is64Bit()) {
1604 // These libcalls are not available in 32-bit.
1605 setLibcallName(RTLIB::SHL_I128, nullptr);
1606 setLibcallName(RTLIB::SRL_I128, nullptr);
1607 setLibcallName(RTLIB::SRA_I128, nullptr);
1608 }
1609
1610 if (!Subtarget->isV9()) {
1611 // SparcV8 does not have FNEGD and FABSD.
1612 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1613 setOperationAction(ISD::FABS, MVT::f64, Custom);
1614 }
1615
1616 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1617 setOperationAction(ISD::FCOS , MVT::f128, Expand);
1618 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1619 setOperationAction(ISD::FREM , MVT::f128, Expand);
1620 setOperationAction(ISD::FMA , MVT::f128, Expand);
1621 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1622 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1623 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1624 setOperationAction(ISD::FREM , MVT::f64, Expand);
1625 setOperationAction(ISD::FMA , MVT::f64, Expand);
1626 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1627 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1628 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1629 setOperationAction(ISD::FREM , MVT::f32, Expand);
1630 setOperationAction(ISD::FMA , MVT::f32, Expand);
1631 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1632 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1633 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1634 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1635 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1636 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1637 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1638 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1639 setOperationAction(ISD::FPOW , MVT::f128, Expand);
1640 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1641 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1642
1643 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1644 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1645 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1646
1647 // Expands to [SU]MUL_LOHI.
1648 setOperationAction(ISD::MULHU, MVT::i32, Expand);
1649 setOperationAction(ISD::MULHS, MVT::i32, Expand);
1650 setOperationAction(ISD::MUL, MVT::i32, Expand);
1651
1652 if (Subtarget->useSoftMulDiv()) {
1653 // .umul works for both signed and unsigned
1654 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1655 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1656 setLibcallName(RTLIB::MUL_I32, ".umul");
1657
1658 setOperationAction(ISD::SDIV, MVT::i32, Expand);
1659 setLibcallName(RTLIB::SDIV_I32, ".div");
1660
1661 setOperationAction(ISD::UDIV, MVT::i32, Expand);
1662 setLibcallName(RTLIB::UDIV_I32, ".udiv");
1663
1664 setLibcallName(RTLIB::SREM_I32, ".rem");
1665 setLibcallName(RTLIB::UREM_I32, ".urem");
1666 }
1667
1668 if (Subtarget->is64Bit()) {
1669 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1670 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1671 setOperationAction(ISD::MULHU, MVT::i64, Expand);
1672 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1673
1674 setOperationAction(ISD::UMULO, MVT::i64, Custom);
1675 setOperationAction(ISD::SMULO, MVT::i64, Custom);
1676
1677 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
1678 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
1679 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
1680 }
1681
1682 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1683 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1684 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1685 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1686
1687 setOperationAction(ISD::TRAP , MVT::Other, Legal);
1688 setOperationAction(ISD::DEBUGTRAP , MVT::Other, Legal);
1689
1690 // Use the default implementation.
1691 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1692 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1693 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1694 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1695 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1696
1697 setStackPointerRegisterToSaveRestore(SP::O6);
1698
1699 setOperationAction(ISD::CTPOP, MVT::i32,
1700 Subtarget->usePopc() ? Legal : Expand);
1701
1702 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1703 setOperationAction(ISD::LOAD, MVT::f128, Legal);
1704 setOperationAction(ISD::STORE, MVT::f128, Legal);
1705 } else {
1706 setOperationAction(ISD::LOAD, MVT::f128, Custom);
1707 setOperationAction(ISD::STORE, MVT::f128, Custom);
1708 }
1709
1710 if (Subtarget->hasHardQuad()) {
1711 setOperationAction(ISD::FADD, MVT::f128, Legal);
1712 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1713 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1714 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1715 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1716 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1717 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1718 if (Subtarget->isV9()) {
1719 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1720 setOperationAction(ISD::FABS, MVT::f128, Legal);
1721 } else {
1722 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1723 setOperationAction(ISD::FABS, MVT::f128, Custom);
1724 }
1725
1726 if (!Subtarget->is64Bit()) {
1727 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1728 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1729 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1730 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1731 }
1732
1733 } else {
1734 // Custom legalize f128 operations.
1735
1736 setOperationAction(ISD::FADD, MVT::f128, Custom);
1737 setOperationAction(ISD::FSUB, MVT::f128, Custom);
1738 setOperationAction(ISD::FMUL, MVT::f128, Custom);
1739 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1740 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1741 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1742 setOperationAction(ISD::FABS, MVT::f128, Custom);
1743
1744 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1745 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
1746 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1747
1748 // Setup Runtime library names.
1749 if (Subtarget->is64Bit() && !Subtarget->useSoftFloat()) {
1750 setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1751 setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1752 setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1753 setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1754 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1755 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1756 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1757 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1758 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1759 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1760 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1761 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1762 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1763 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1764 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1765 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1766 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1767 } else if (!Subtarget->useSoftFloat()) {
1768 setLibcallName(RTLIB::ADD_F128, "_Q_add");
1769 setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1770 setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1771 setLibcallName(RTLIB::DIV_F128, "_Q_div");
1772 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1773 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1774 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1775 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1776 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1777 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1778 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1779 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1780 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1781 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1782 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1783 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1784 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1785 }
1786 }
1787
1788 if (Subtarget->fixAllFDIVSQRT()) {
1789 // Promote FDIVS and FSQRTS to FDIVD and FSQRTD instructions instead as
1790 // the former instructions generate errata on LEON processors.
1791 setOperationAction(ISD::FDIV, MVT::f32, Promote);
1792 setOperationAction(ISD::FSQRT, MVT::f32, Promote);
1793 }
1794
1795 if (Subtarget->hasNoFMULS()) {
1796 setOperationAction(ISD::FMUL, MVT::f32, Promote);
1797 }
1798
1799 // Custom combine bitcast between f64 and v2i32
1800 if (!Subtarget->is64Bit())
1801 setTargetDAGCombine(ISD::BITCAST);
1802
1803 if (Subtarget->hasLeonCycleCounter())
1804 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
1805
1806 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1807
1808 setMinFunctionAlignment(Align(4));
1809
1810 computeRegisterProperties(Subtarget->getRegisterInfo());
1811 }
1812
useSoftFloat() const1813 bool SparcTargetLowering::useSoftFloat() const {
1814 return Subtarget->useSoftFloat();
1815 }
1816
getTargetNodeName(unsigned Opcode) const1817 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1818 switch ((SPISD::NodeType)Opcode) {
1819 case SPISD::FIRST_NUMBER: break;
1820 case SPISD::CMPICC: return "SPISD::CMPICC";
1821 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1822 case SPISD::BRICC: return "SPISD::BRICC";
1823 case SPISD::BRXCC: return "SPISD::BRXCC";
1824 case SPISD::BRFCC: return "SPISD::BRFCC";
1825 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1826 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1827 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1828 case SPISD::Hi: return "SPISD::Hi";
1829 case SPISD::Lo: return "SPISD::Lo";
1830 case SPISD::FTOI: return "SPISD::FTOI";
1831 case SPISD::ITOF: return "SPISD::ITOF";
1832 case SPISD::FTOX: return "SPISD::FTOX";
1833 case SPISD::XTOF: return "SPISD::XTOF";
1834 case SPISD::CALL: return "SPISD::CALL";
1835 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1836 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1837 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1838 case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
1839 case SPISD::TLS_LD: return "SPISD::TLS_LD";
1840 case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
1841 }
1842 return nullptr;
1843 }
1844
getSetCCResultType(const DataLayout &,LLVMContext &,EVT VT) const1845 EVT SparcTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
1846 EVT VT) const {
1847 if (!VT.isVector())
1848 return MVT::i32;
1849 return VT.changeVectorElementTypeToInteger();
1850 }
1851
1852 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1853 /// be zero. Op is expected to be a target specific node. Used by DAG
1854 /// combiner.
computeKnownBitsForTargetNode(const SDValue Op,KnownBits & Known,const APInt & DemandedElts,const SelectionDAG & DAG,unsigned Depth) const1855 void SparcTargetLowering::computeKnownBitsForTargetNode
1856 (const SDValue Op,
1857 KnownBits &Known,
1858 const APInt &DemandedElts,
1859 const SelectionDAG &DAG,
1860 unsigned Depth) const {
1861 KnownBits Known2;
1862 Known.resetAll();
1863
1864 switch (Op.getOpcode()) {
1865 default: break;
1866 case SPISD::SELECT_ICC:
1867 case SPISD::SELECT_XCC:
1868 case SPISD::SELECT_FCC:
1869 Known = DAG.computeKnownBits(Op.getOperand(1), Depth + 1);
1870 Known2 = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);
1871
1872 // Only known if known in both the LHS and RHS.
1873 Known.One &= Known2.One;
1874 Known.Zero &= Known2.Zero;
1875 break;
1876 }
1877 }
1878
1879 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1880 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
LookThroughSetCC(SDValue & LHS,SDValue & RHS,ISD::CondCode CC,unsigned & SPCC)1881 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1882 ISD::CondCode CC, unsigned &SPCC) {
1883 if (isNullConstant(RHS) &&
1884 CC == ISD::SETNE &&
1885 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1886 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1887 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1888 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1889 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1890 isOneConstant(LHS.getOperand(0)) &&
1891 isNullConstant(LHS.getOperand(1))) {
1892 SDValue CMPCC = LHS.getOperand(3);
1893 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1894 LHS = CMPCC.getOperand(0);
1895 RHS = CMPCC.getOperand(1);
1896 }
1897 }
1898
1899 // Convert to a target node and set target flags.
withTargetFlags(SDValue Op,unsigned TF,SelectionDAG & DAG) const1900 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1901 SelectionDAG &DAG) const {
1902 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1903 return DAG.getTargetGlobalAddress(GA->getGlobal(),
1904 SDLoc(GA),
1905 GA->getValueType(0),
1906 GA->getOffset(), TF);
1907
1908 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1909 return DAG.getTargetConstantPool(CP->getConstVal(),
1910 CP->getValueType(0),
1911 CP->getAlignment(),
1912 CP->getOffset(), TF);
1913
1914 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1915 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1916 Op.getValueType(),
1917 0,
1918 TF);
1919
1920 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1921 return DAG.getTargetExternalSymbol(ES->getSymbol(),
1922 ES->getValueType(0), TF);
1923
1924 llvm_unreachable("Unhandled address SDNode");
1925 }
1926
1927 // Split Op into high and low parts according to HiTF and LoTF.
1928 // Return an ADD node combining the parts.
makeHiLoPair(SDValue Op,unsigned HiTF,unsigned LoTF,SelectionDAG & DAG) const1929 SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1930 unsigned HiTF, unsigned LoTF,
1931 SelectionDAG &DAG) const {
1932 SDLoc DL(Op);
1933 EVT VT = Op.getValueType();
1934 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1935 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1936 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1937 }
1938
1939 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1940 // or ExternalSymbol SDNode.
makeAddress(SDValue Op,SelectionDAG & DAG) const1941 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1942 SDLoc DL(Op);
1943 EVT VT = getPointerTy(DAG.getDataLayout());
1944
1945 // Handle PIC mode first. SPARC needs a got load for every variable!
1946 if (isPositionIndependent()) {
1947 const Module *M = DAG.getMachineFunction().getFunction().getParent();
1948 PICLevel::Level picLevel = M->getPICLevel();
1949 SDValue Idx;
1950
1951 if (picLevel == PICLevel::SmallPIC) {
1952 // This is the pic13 code model, the GOT is known to be smaller than 8KiB.
1953 Idx = DAG.getNode(SPISD::Lo, DL, Op.getValueType(),
1954 withTargetFlags(Op, SparcMCExpr::VK_Sparc_GOT13, DAG));
1955 } else {
1956 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1957 Idx = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22,
1958 SparcMCExpr::VK_Sparc_GOT10, DAG);
1959 }
1960
1961 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1962 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, Idx);
1963 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1964 // function has calls.
1965 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
1966 MFI.setHasCalls(true);
1967 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1968 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1969 }
1970
1971 // This is one of the absolute code models.
1972 switch(getTargetMachine().getCodeModel()) {
1973 default:
1974 llvm_unreachable("Unsupported absolute code model");
1975 case CodeModel::Small:
1976 // abs32.
1977 return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1978 SparcMCExpr::VK_Sparc_LO, DAG);
1979 case CodeModel::Medium: {
1980 // abs44.
1981 SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44,
1982 SparcMCExpr::VK_Sparc_M44, DAG);
1983 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32));
1984 SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG);
1985 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1986 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1987 }
1988 case CodeModel::Large: {
1989 // abs64.
1990 SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH,
1991 SparcMCExpr::VK_Sparc_HM, DAG);
1992 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32));
1993 SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1994 SparcMCExpr::VK_Sparc_LO, DAG);
1995 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1996 }
1997 }
1998 }
1999
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const2000 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
2001 SelectionDAG &DAG) const {
2002 return makeAddress(Op, DAG);
2003 }
2004
LowerConstantPool(SDValue Op,SelectionDAG & DAG) const2005 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
2006 SelectionDAG &DAG) const {
2007 return makeAddress(Op, DAG);
2008 }
2009
LowerBlockAddress(SDValue Op,SelectionDAG & DAG) const2010 SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
2011 SelectionDAG &DAG) const {
2012 return makeAddress(Op, DAG);
2013 }
2014
LowerGlobalTLSAddress(SDValue Op,SelectionDAG & DAG) const2015 SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2016 SelectionDAG &DAG) const {
2017
2018 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2019 if (DAG.getTarget().useEmulatedTLS())
2020 return LowerToTLSEmulatedModel(GA, DAG);
2021
2022 SDLoc DL(GA);
2023 const GlobalValue *GV = GA->getGlobal();
2024 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2025
2026 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2027
2028 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2029 unsigned HiTF = ((model == TLSModel::GeneralDynamic)
2030 ? SparcMCExpr::VK_Sparc_TLS_GD_HI22
2031 : SparcMCExpr::VK_Sparc_TLS_LDM_HI22);
2032 unsigned LoTF = ((model == TLSModel::GeneralDynamic)
2033 ? SparcMCExpr::VK_Sparc_TLS_GD_LO10
2034 : SparcMCExpr::VK_Sparc_TLS_LDM_LO10);
2035 unsigned addTF = ((model == TLSModel::GeneralDynamic)
2036 ? SparcMCExpr::VK_Sparc_TLS_GD_ADD
2037 : SparcMCExpr::VK_Sparc_TLS_LDM_ADD);
2038 unsigned callTF = ((model == TLSModel::GeneralDynamic)
2039 ? SparcMCExpr::VK_Sparc_TLS_GD_CALL
2040 : SparcMCExpr::VK_Sparc_TLS_LDM_CALL);
2041
2042 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
2043 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
2044 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
2045 withTargetFlags(Op, addTF, DAG));
2046
2047 SDValue Chain = DAG.getEntryNode();
2048 SDValue InFlag;
2049
2050 Chain = DAG.getCALLSEQ_START(Chain, 1, 0, DL);
2051 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
2052 InFlag = Chain.getValue(1);
2053 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
2054 SDValue Symbol = withTargetFlags(Op, callTF, DAG);
2055
2056 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2057 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
2058 DAG.getMachineFunction(), CallingConv::C);
2059 assert(Mask && "Missing call preserved mask for calling convention");
2060 SDValue Ops[] = {Chain,
2061 Callee,
2062 Symbol,
2063 DAG.getRegister(SP::O0, PtrVT),
2064 DAG.getRegisterMask(Mask),
2065 InFlag};
2066 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
2067 InFlag = Chain.getValue(1);
2068 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, DL, true),
2069 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2070 InFlag = Chain.getValue(1);
2071 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
2072
2073 if (model != TLSModel::LocalDynamic)
2074 return Ret;
2075
2076 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2077 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG));
2078 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2079 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG));
2080 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2081 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
2082 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG));
2083 }
2084
2085 if (model == TLSModel::InitialExec) {
2086 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX
2087 : SparcMCExpr::VK_Sparc_TLS_IE_LD);
2088
2089 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
2090
2091 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
2092 // function has calls.
2093 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2094 MFI.setHasCalls(true);
2095
2096 SDValue TGA = makeHiLoPair(Op,
2097 SparcMCExpr::VK_Sparc_TLS_IE_HI22,
2098 SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG);
2099 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
2100 SDValue Offset = DAG.getNode(SPISD::TLS_LD,
2101 DL, PtrVT, Ptr,
2102 withTargetFlags(Op, ldTF, DAG));
2103 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
2104 DAG.getRegister(SP::G7, PtrVT), Offset,
2105 withTargetFlags(Op,
2106 SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG));
2107 }
2108
2109 assert(model == TLSModel::LocalExec);
2110 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
2111 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG));
2112 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
2113 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG));
2114 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
2115
2116 return DAG.getNode(ISD::ADD, DL, PtrVT,
2117 DAG.getRegister(SP::G7, PtrVT), Offset);
2118 }
2119
LowerF128_LibCallArg(SDValue Chain,ArgListTy & Args,SDValue Arg,const SDLoc & DL,SelectionDAG & DAG) const2120 SDValue SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain,
2121 ArgListTy &Args, SDValue Arg,
2122 const SDLoc &DL,
2123 SelectionDAG &DAG) const {
2124 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2125 EVT ArgVT = Arg.getValueType();
2126 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2127
2128 ArgListEntry Entry;
2129 Entry.Node = Arg;
2130 Entry.Ty = ArgTy;
2131
2132 if (ArgTy->isFP128Ty()) {
2133 // Create a stack object and pass the pointer to the library function.
2134 int FI = MFI.CreateStackObject(16, 8, false);
2135 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2136 Chain = DAG.getStore(Chain, DL, Entry.Node, FIPtr, MachinePointerInfo(),
2137 /* Alignment = */ 8);
2138
2139 Entry.Node = FIPtr;
2140 Entry.Ty = PointerType::getUnqual(ArgTy);
2141 }
2142 Args.push_back(Entry);
2143 return Chain;
2144 }
2145
2146 SDValue
LowerF128Op(SDValue Op,SelectionDAG & DAG,const char * LibFuncName,unsigned numArgs) const2147 SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2148 const char *LibFuncName,
2149 unsigned numArgs) const {
2150
2151 ArgListTy Args;
2152
2153 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2154 auto PtrVT = getPointerTy(DAG.getDataLayout());
2155
2156 SDValue Callee = DAG.getExternalSymbol(LibFuncName, PtrVT);
2157 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2158 Type *RetTyABI = RetTy;
2159 SDValue Chain = DAG.getEntryNode();
2160 SDValue RetPtr;
2161
2162 if (RetTy->isFP128Ty()) {
2163 // Create a Stack Object to receive the return value of type f128.
2164 ArgListEntry Entry;
2165 int RetFI = MFI.CreateStackObject(16, 8, false);
2166 RetPtr = DAG.getFrameIndex(RetFI, PtrVT);
2167 Entry.Node = RetPtr;
2168 Entry.Ty = PointerType::getUnqual(RetTy);
2169 if (!Subtarget->is64Bit())
2170 Entry.IsSRet = true;
2171 Entry.IsReturned = false;
2172 Args.push_back(Entry);
2173 RetTyABI = Type::getVoidTy(*DAG.getContext());
2174 }
2175
2176 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2177 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2178 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2179 }
2180 TargetLowering::CallLoweringInfo CLI(DAG);
2181 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2182 .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args));
2183
2184 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2185
2186 // chain is in second result.
2187 if (RetTyABI == RetTy)
2188 return CallInfo.first;
2189
2190 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2191
2192 Chain = CallInfo.second;
2193
2194 // Load RetPtr to get the return value.
2195 return DAG.getLoad(Op.getValueType(), SDLoc(Op), Chain, RetPtr,
2196 MachinePointerInfo(), /* Alignment = */ 8);
2197 }
2198
LowerF128Compare(SDValue LHS,SDValue RHS,unsigned & SPCC,const SDLoc & DL,SelectionDAG & DAG) const2199 SDValue SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2200 unsigned &SPCC, const SDLoc &DL,
2201 SelectionDAG &DAG) const {
2202
2203 const char *LibCall = nullptr;
2204 bool is64Bit = Subtarget->is64Bit();
2205 switch(SPCC) {
2206 default: llvm_unreachable("Unhandled conditional code!");
2207 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2208 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2209 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2210 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2211 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2212 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2213 case SPCC::FCC_UL :
2214 case SPCC::FCC_ULE:
2215 case SPCC::FCC_UG :
2216 case SPCC::FCC_UGE:
2217 case SPCC::FCC_U :
2218 case SPCC::FCC_O :
2219 case SPCC::FCC_LG :
2220 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2221 }
2222
2223 auto PtrVT = getPointerTy(DAG.getDataLayout());
2224 SDValue Callee = DAG.getExternalSymbol(LibCall, PtrVT);
2225 Type *RetTy = Type::getInt32Ty(*DAG.getContext());
2226 ArgListTy Args;
2227 SDValue Chain = DAG.getEntryNode();
2228 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2229 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2230
2231 TargetLowering::CallLoweringInfo CLI(DAG);
2232 CLI.setDebugLoc(DL).setChain(Chain)
2233 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args));
2234
2235 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2236
2237 // result is in first, and chain is in second result.
2238 SDValue Result = CallInfo.first;
2239
2240 switch(SPCC) {
2241 default: {
2242 SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2243 SPCC = SPCC::ICC_NE;
2244 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2245 }
2246 case SPCC::FCC_UL : {
2247 SDValue Mask = DAG.getConstant(1, DL, Result.getValueType());
2248 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2249 SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2250 SPCC = SPCC::ICC_NE;
2251 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2252 }
2253 case SPCC::FCC_ULE: {
2254 SDValue RHS = DAG.getTargetConstant(2, DL, Result.getValueType());
2255 SPCC = SPCC::ICC_NE;
2256 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2257 }
2258 case SPCC::FCC_UG : {
2259 SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
2260 SPCC = SPCC::ICC_G;
2261 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2262 }
2263 case SPCC::FCC_UGE: {
2264 SDValue RHS = DAG.getTargetConstant(1, DL, Result.getValueType());
2265 SPCC = SPCC::ICC_NE;
2266 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2267 }
2268
2269 case SPCC::FCC_U : {
2270 SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
2271 SPCC = SPCC::ICC_E;
2272 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2273 }
2274 case SPCC::FCC_O : {
2275 SDValue RHS = DAG.getTargetConstant(3, DL, Result.getValueType());
2276 SPCC = SPCC::ICC_NE;
2277 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2278 }
2279 case SPCC::FCC_LG : {
2280 SDValue Mask = DAG.getConstant(3, DL, Result.getValueType());
2281 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2282 SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2283 SPCC = SPCC::ICC_NE;
2284 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2285 }
2286 case SPCC::FCC_UE : {
2287 SDValue Mask = DAG.getConstant(3, DL, Result.getValueType());
2288 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2289 SDValue RHS = DAG.getTargetConstant(0, DL, Result.getValueType());
2290 SPCC = SPCC::ICC_E;
2291 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2292 }
2293 }
2294 }
2295
2296 static SDValue
LowerF128_FPEXTEND(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2297 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2298 const SparcTargetLowering &TLI) {
2299
2300 if (Op.getOperand(0).getValueType() == MVT::f64)
2301 return TLI.LowerF128Op(Op, DAG,
2302 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2303
2304 if (Op.getOperand(0).getValueType() == MVT::f32)
2305 return TLI.LowerF128Op(Op, DAG,
2306 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2307
2308 llvm_unreachable("fpextend with non-float operand!");
2309 return SDValue();
2310 }
2311
2312 static SDValue
LowerF128_FPROUND(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2313 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2314 const SparcTargetLowering &TLI) {
2315 // FP_ROUND on f64 and f32 are legal.
2316 if (Op.getOperand(0).getValueType() != MVT::f128)
2317 return Op;
2318
2319 if (Op.getValueType() == MVT::f64)
2320 return TLI.LowerF128Op(Op, DAG,
2321 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2322 if (Op.getValueType() == MVT::f32)
2323 return TLI.LowerF128Op(Op, DAG,
2324 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2325
2326 llvm_unreachable("fpround to non-float!");
2327 return SDValue();
2328 }
2329
LowerFP_TO_SINT(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2330 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2331 const SparcTargetLowering &TLI,
2332 bool hasHardQuad) {
2333 SDLoc dl(Op);
2334 EVT VT = Op.getValueType();
2335 assert(VT == MVT::i32 || VT == MVT::i64);
2336
2337 // Expand f128 operations to fp128 abi calls.
2338 if (Op.getOperand(0).getValueType() == MVT::f128
2339 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2340 const char *libName = TLI.getLibcallName(VT == MVT::i32
2341 ? RTLIB::FPTOSINT_F128_I32
2342 : RTLIB::FPTOSINT_F128_I64);
2343 return TLI.LowerF128Op(Op, DAG, libName, 1);
2344 }
2345
2346 // Expand if the resulting type is illegal.
2347 if (!TLI.isTypeLegal(VT))
2348 return SDValue();
2349
2350 // Otherwise, Convert the fp value to integer in an FP register.
2351 if (VT == MVT::i32)
2352 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2353 else
2354 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2355
2356 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2357 }
2358
LowerSINT_TO_FP(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2359 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2360 const SparcTargetLowering &TLI,
2361 bool hasHardQuad) {
2362 SDLoc dl(Op);
2363 EVT OpVT = Op.getOperand(0).getValueType();
2364 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2365
2366 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2367
2368 // Expand f128 operations to fp128 ABI calls.
2369 if (Op.getValueType() == MVT::f128
2370 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2371 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2372 ? RTLIB::SINTTOFP_I32_F128
2373 : RTLIB::SINTTOFP_I64_F128);
2374 return TLI.LowerF128Op(Op, DAG, libName, 1);
2375 }
2376
2377 // Expand if the operand type is illegal.
2378 if (!TLI.isTypeLegal(OpVT))
2379 return SDValue();
2380
2381 // Otherwise, Convert the int value to FP in an FP register.
2382 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2383 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2384 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2385 }
2386
LowerFP_TO_UINT(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2387 static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2388 const SparcTargetLowering &TLI,
2389 bool hasHardQuad) {
2390 SDLoc dl(Op);
2391 EVT VT = Op.getValueType();
2392
2393 // Expand if it does not involve f128 or the target has support for
2394 // quad floating point instructions and the resulting type is legal.
2395 if (Op.getOperand(0).getValueType() != MVT::f128 ||
2396 (hasHardQuad && TLI.isTypeLegal(VT)))
2397 return SDValue();
2398
2399 assert(VT == MVT::i32 || VT == MVT::i64);
2400
2401 return TLI.LowerF128Op(Op, DAG,
2402 TLI.getLibcallName(VT == MVT::i32
2403 ? RTLIB::FPTOUINT_F128_I32
2404 : RTLIB::FPTOUINT_F128_I64),
2405 1);
2406 }
2407
LowerUINT_TO_FP(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2408 static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2409 const SparcTargetLowering &TLI,
2410 bool hasHardQuad) {
2411 SDLoc dl(Op);
2412 EVT OpVT = Op.getOperand(0).getValueType();
2413 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2414
2415 // Expand if it does not involve f128 or the target has support for
2416 // quad floating point instructions and the operand type is legal.
2417 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2418 return SDValue();
2419
2420 return TLI.LowerF128Op(Op, DAG,
2421 TLI.getLibcallName(OpVT == MVT::i32
2422 ? RTLIB::UINTTOFP_I32_F128
2423 : RTLIB::UINTTOFP_I64_F128),
2424 1);
2425 }
2426
LowerBR_CC(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2427 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2428 const SparcTargetLowering &TLI,
2429 bool hasHardQuad) {
2430 SDValue Chain = Op.getOperand(0);
2431 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2432 SDValue LHS = Op.getOperand(2);
2433 SDValue RHS = Op.getOperand(3);
2434 SDValue Dest = Op.getOperand(4);
2435 SDLoc dl(Op);
2436 unsigned Opc, SPCC = ~0U;
2437
2438 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2439 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2440 LookThroughSetCC(LHS, RHS, CC, SPCC);
2441
2442 // Get the condition flag.
2443 SDValue CompareFlag;
2444 if (LHS.getValueType().isInteger()) {
2445 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2446 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2447 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2448 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
2449 } else {
2450 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2451 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2452 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2453 Opc = SPISD::BRICC;
2454 } else {
2455 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2456 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2457 Opc = SPISD::BRFCC;
2458 }
2459 }
2460 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2461 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2462 }
2463
LowerSELECT_CC(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2464 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2465 const SparcTargetLowering &TLI,
2466 bool hasHardQuad) {
2467 SDValue LHS = Op.getOperand(0);
2468 SDValue RHS = Op.getOperand(1);
2469 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2470 SDValue TrueVal = Op.getOperand(2);
2471 SDValue FalseVal = Op.getOperand(3);
2472 SDLoc dl(Op);
2473 unsigned Opc, SPCC = ~0U;
2474
2475 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2476 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2477 LookThroughSetCC(LHS, RHS, CC, SPCC);
2478
2479 SDValue CompareFlag;
2480 if (LHS.getValueType().isInteger()) {
2481 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2482 Opc = LHS.getValueType() == MVT::i32 ?
2483 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2484 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2485 } else {
2486 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2487 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2488 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2489 Opc = SPISD::SELECT_ICC;
2490 } else {
2491 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2492 Opc = SPISD::SELECT_FCC;
2493 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2494 }
2495 }
2496 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2497 DAG.getConstant(SPCC, dl, MVT::i32), CompareFlag);
2498 }
2499
LowerVASTART(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2500 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2501 const SparcTargetLowering &TLI) {
2502 MachineFunction &MF = DAG.getMachineFunction();
2503 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2504 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2505
2506 // Need frame address to find the address of VarArgsFrameIndex.
2507 MF.getFrameInfo().setFrameAddressIsTaken(true);
2508
2509 // vastart just stores the address of the VarArgsFrameIndex slot into the
2510 // memory location argument.
2511 SDLoc DL(Op);
2512 SDValue Offset =
2513 DAG.getNode(ISD::ADD, DL, PtrVT, DAG.getRegister(SP::I6, PtrVT),
2514 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL));
2515 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2516 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2517 MachinePointerInfo(SV));
2518 }
2519
LowerVAARG(SDValue Op,SelectionDAG & DAG)2520 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2521 SDNode *Node = Op.getNode();
2522 EVT VT = Node->getValueType(0);
2523 SDValue InChain = Node->getOperand(0);
2524 SDValue VAListPtr = Node->getOperand(1);
2525 EVT PtrVT = VAListPtr.getValueType();
2526 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2527 SDLoc DL(Node);
2528 SDValue VAList =
2529 DAG.getLoad(PtrVT, DL, InChain, VAListPtr, MachinePointerInfo(SV));
2530 // Increment the pointer, VAList, to the next vaarg.
2531 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2532 DAG.getIntPtrConstant(VT.getSizeInBits()/8,
2533 DL));
2534 // Store the incremented VAList to the legalized pointer.
2535 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr, VAListPtr,
2536 MachinePointerInfo(SV));
2537 // Load the actual argument out of the pointer VAList.
2538 // We can't count on greater alignment than the word size.
2539 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2540 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits()) / 8);
2541 }
2542
LowerDYNAMIC_STACKALLOC(SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget)2543 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2544 const SparcSubtarget *Subtarget) {
2545 SDValue Chain = Op.getOperand(0); // Legalize the chain.
2546 SDValue Size = Op.getOperand(1); // Legalize the size.
2547 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2548 unsigned StackAlign = Subtarget->getFrameLowering()->getStackAlignment();
2549 EVT VT = Size->getValueType(0);
2550 SDLoc dl(Op);
2551
2552 // TODO: implement over-aligned alloca. (Note: also implies
2553 // supporting support for overaligned function frames + dynamic
2554 // allocations, at all, which currently isn't supported)
2555 if (Align > StackAlign) {
2556 const MachineFunction &MF = DAG.getMachineFunction();
2557 report_fatal_error("Function \"" + Twine(MF.getName()) + "\": "
2558 "over-aligned dynamic alloca not supported.");
2559 }
2560
2561 // The resultant pointer needs to be above the register spill area
2562 // at the bottom of the stack.
2563 unsigned regSpillArea;
2564 if (Subtarget->is64Bit()) {
2565 regSpillArea = 128;
2566 } else {
2567 // On Sparc32, the size of the spill area is 92. Unfortunately,
2568 // that's only 4-byte aligned, not 8-byte aligned (the stack
2569 // pointer is 8-byte aligned). So, if the user asked for an 8-byte
2570 // aligned dynamic allocation, we actually need to add 96 to the
2571 // bottom of the stack, instead of 92, to ensure 8-byte alignment.
2572
2573 // That also means adding 4 to the size of the allocation --
2574 // before applying the 8-byte rounding. Unfortunately, we the
2575 // value we get here has already had rounding applied. So, we need
2576 // to add 8, instead, wasting a bit more memory.
2577
2578 // Further, this only actually needs to be done if the required
2579 // alignment is > 4, but, we've lost that info by this point, too,
2580 // so we always apply it.
2581
2582 // (An alternative approach would be to always reserve 96 bytes
2583 // instead of the required 92, but then we'd waste 4 extra bytes
2584 // in every frame, not just those with dynamic stack allocations)
2585
2586 // TODO: modify code in SelectionDAGBuilder to make this less sad.
2587
2588 Size = DAG.getNode(ISD::ADD, dl, VT, Size,
2589 DAG.getConstant(8, dl, VT));
2590 regSpillArea = 96;
2591 }
2592
2593 unsigned SPReg = SP::O6;
2594 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2595 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2596 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2597
2598 regSpillArea += Subtarget->getStackPointerBias();
2599
2600 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2601 DAG.getConstant(regSpillArea, dl, VT));
2602 SDValue Ops[2] = { NewVal, Chain };
2603 return DAG.getMergeValues(Ops, dl);
2604 }
2605
2606
getFLUSHW(SDValue Op,SelectionDAG & DAG)2607 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2608 SDLoc dl(Op);
2609 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2610 dl, MVT::Other, DAG.getEntryNode());
2611 return Chain;
2612 }
2613
getFRAMEADDR(uint64_t depth,SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget,bool AlwaysFlush=false)2614 static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2615 const SparcSubtarget *Subtarget,
2616 bool AlwaysFlush = false) {
2617 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2618 MFI.setFrameAddressIsTaken(true);
2619
2620 EVT VT = Op.getValueType();
2621 SDLoc dl(Op);
2622 unsigned FrameReg = SP::I6;
2623 unsigned stackBias = Subtarget->getStackPointerBias();
2624
2625 SDValue FrameAddr;
2626 SDValue Chain;
2627
2628 // flush first to make sure the windowed registers' values are in stack
2629 Chain = (depth || AlwaysFlush) ? getFLUSHW(Op, DAG) : DAG.getEntryNode();
2630
2631 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2632
2633 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2634
2635 while (depth--) {
2636 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2637 DAG.getIntPtrConstant(Offset, dl));
2638 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo());
2639 }
2640 if (Subtarget->is64Bit())
2641 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2642 DAG.getIntPtrConstant(stackBias, dl));
2643 return FrameAddr;
2644 }
2645
2646
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget)2647 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2648 const SparcSubtarget *Subtarget) {
2649
2650 uint64_t depth = Op.getConstantOperandVal(0);
2651
2652 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2653
2654 }
2655
LowerRETURNADDR(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,const SparcSubtarget * Subtarget)2656 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2657 const SparcTargetLowering &TLI,
2658 const SparcSubtarget *Subtarget) {
2659 MachineFunction &MF = DAG.getMachineFunction();
2660 MachineFrameInfo &MFI = MF.getFrameInfo();
2661 MFI.setReturnAddressIsTaken(true);
2662
2663 if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
2664 return SDValue();
2665
2666 EVT VT = Op.getValueType();
2667 SDLoc dl(Op);
2668 uint64_t depth = Op.getConstantOperandVal(0);
2669
2670 SDValue RetAddr;
2671 if (depth == 0) {
2672 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
2673 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT));
2674 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2675 return RetAddr;
2676 }
2677
2678 // Need frame address to find return address of the caller.
2679 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget, true);
2680
2681 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2682 SDValue Ptr = DAG.getNode(ISD::ADD,
2683 dl, VT,
2684 FrameAddr,
2685 DAG.getIntPtrConstant(Offset, dl));
2686 RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr, MachinePointerInfo());
2687
2688 return RetAddr;
2689 }
2690
LowerF64Op(SDValue SrcReg64,const SDLoc & dl,SelectionDAG & DAG,unsigned opcode)2691 static SDValue LowerF64Op(SDValue SrcReg64, const SDLoc &dl, SelectionDAG &DAG,
2692 unsigned opcode) {
2693 assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2694 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2695
2696 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2697 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2698 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2699
2700 // Note: in little-endian, the floating-point value is stored in the
2701 // registers are in the opposite order, so the subreg with the sign
2702 // bit is the highest-numbered (odd), rather than the
2703 // lowest-numbered (even).
2704
2705 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2706 SrcReg64);
2707 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2708 SrcReg64);
2709
2710 if (DAG.getDataLayout().isLittleEndian())
2711 Lo32 = DAG.getNode(opcode, dl, MVT::f32, Lo32);
2712 else
2713 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2714
2715 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2716 dl, MVT::f64), 0);
2717 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2718 DstReg64, Hi32);
2719 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2720 DstReg64, Lo32);
2721 return DstReg64;
2722 }
2723
2724 // Lower a f128 load into two f64 loads.
LowerF128Load(SDValue Op,SelectionDAG & DAG)2725 static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2726 {
2727 SDLoc dl(Op);
2728 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2729 assert(LdNode && LdNode->getOffset().isUndef()
2730 && "Unexpected node type");
2731
2732 unsigned alignment = LdNode->getAlignment();
2733 if (alignment > 8)
2734 alignment = 8;
2735
2736 SDValue Hi64 =
2737 DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LdNode->getBasePtr(),
2738 LdNode->getPointerInfo(), alignment);
2739 EVT addrVT = LdNode->getBasePtr().getValueType();
2740 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2741 LdNode->getBasePtr(),
2742 DAG.getConstant(8, dl, addrVT));
2743 SDValue Lo64 = DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LoPtr,
2744 LdNode->getPointerInfo(), alignment);
2745
2746 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2747 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2748
2749 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2750 dl, MVT::f128);
2751 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2752 MVT::f128,
2753 SDValue(InFP128, 0),
2754 Hi64,
2755 SubRegEven);
2756 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2757 MVT::f128,
2758 SDValue(InFP128, 0),
2759 Lo64,
2760 SubRegOdd);
2761 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2762 SDValue(Lo64.getNode(), 1) };
2763 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2764 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2765 return DAG.getMergeValues(Ops, dl);
2766 }
2767
LowerLOAD(SDValue Op,SelectionDAG & DAG)2768 static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG)
2769 {
2770 LoadSDNode *LdNode = cast<LoadSDNode>(Op.getNode());
2771
2772 EVT MemVT = LdNode->getMemoryVT();
2773 if (MemVT == MVT::f128)
2774 return LowerF128Load(Op, DAG);
2775
2776 return Op;
2777 }
2778
2779 // Lower a f128 store into two f64 stores.
LowerF128Store(SDValue Op,SelectionDAG & DAG)2780 static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2781 SDLoc dl(Op);
2782 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2783 assert(StNode && StNode->getOffset().isUndef()
2784 && "Unexpected node type");
2785 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, dl, MVT::i32);
2786 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, dl, MVT::i32);
2787
2788 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2789 dl,
2790 MVT::f64,
2791 StNode->getValue(),
2792 SubRegEven);
2793 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2794 dl,
2795 MVT::f64,
2796 StNode->getValue(),
2797 SubRegOdd);
2798
2799 unsigned alignment = StNode->getAlignment();
2800 if (alignment > 8)
2801 alignment = 8;
2802
2803 SDValue OutChains[2];
2804 OutChains[0] =
2805 DAG.getStore(StNode->getChain(), dl, SDValue(Hi64, 0),
2806 StNode->getBasePtr(), MachinePointerInfo(), alignment);
2807 EVT addrVT = StNode->getBasePtr().getValueType();
2808 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2809 StNode->getBasePtr(),
2810 DAG.getConstant(8, dl, addrVT));
2811 OutChains[1] = DAG.getStore(StNode->getChain(), dl, SDValue(Lo64, 0), LoPtr,
2812 MachinePointerInfo(), alignment);
2813 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2814 }
2815
LowerSTORE(SDValue Op,SelectionDAG & DAG)2816 static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG)
2817 {
2818 SDLoc dl(Op);
2819 StoreSDNode *St = cast<StoreSDNode>(Op.getNode());
2820
2821 EVT MemVT = St->getMemoryVT();
2822 if (MemVT == MVT::f128)
2823 return LowerF128Store(Op, DAG);
2824
2825 if (MemVT == MVT::i64) {
2826 // Custom handling for i64 stores: turn it into a bitcast and a
2827 // v2i32 store.
2828 SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue());
2829 SDValue Chain = DAG.getStore(
2830 St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(),
2831 St->getAlignment(), St->getMemOperand()->getFlags(), St->getAAInfo());
2832 return Chain;
2833 }
2834
2835 return SDValue();
2836 }
2837
LowerFNEGorFABS(SDValue Op,SelectionDAG & DAG,bool isV9)2838 static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2839 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
2840 && "invalid opcode");
2841
2842 SDLoc dl(Op);
2843
2844 if (Op.getValueType() == MVT::f64)
2845 return LowerF64Op(Op.getOperand(0), dl, DAG, Op.getOpcode());
2846 if (Op.getValueType() != MVT::f128)
2847 return Op;
2848
2849 // Lower fabs/fneg on f128 to fabs/fneg on f64
2850 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
2851 // (As with LowerF64Op, on little-endian, we need to negate the odd
2852 // subreg)
2853
2854 SDValue SrcReg128 = Op.getOperand(0);
2855 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2856 SrcReg128);
2857 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2858 SrcReg128);
2859
2860 if (DAG.getDataLayout().isLittleEndian()) {
2861 if (isV9)
2862 Lo64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Lo64);
2863 else
2864 Lo64 = LowerF64Op(Lo64, dl, DAG, Op.getOpcode());
2865 } else {
2866 if (isV9)
2867 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2868 else
2869 Hi64 = LowerF64Op(Hi64, dl, DAG, Op.getOpcode());
2870 }
2871
2872 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2873 dl, MVT::f128), 0);
2874 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2875 DstReg128, Hi64);
2876 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2877 DstReg128, Lo64);
2878 return DstReg128;
2879 }
2880
LowerADDC_ADDE_SUBC_SUBE(SDValue Op,SelectionDAG & DAG)2881 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
2882
2883 if (Op.getValueType() != MVT::i64)
2884 return Op;
2885
2886 SDLoc dl(Op);
2887 SDValue Src1 = Op.getOperand(0);
2888 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2889 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
2890 DAG.getConstant(32, dl, MVT::i64));
2891 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
2892
2893 SDValue Src2 = Op.getOperand(1);
2894 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
2895 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
2896 DAG.getConstant(32, dl, MVT::i64));
2897 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
2898
2899
2900 bool hasChain = false;
2901 unsigned hiOpc = Op.getOpcode();
2902 switch (Op.getOpcode()) {
2903 default: llvm_unreachable("Invalid opcode");
2904 case ISD::ADDC: hiOpc = ISD::ADDE; break;
2905 case ISD::ADDE: hasChain = true; break;
2906 case ISD::SUBC: hiOpc = ISD::SUBE; break;
2907 case ISD::SUBE: hasChain = true; break;
2908 }
2909 SDValue Lo;
2910 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
2911 if (hasChain) {
2912 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2913 Op.getOperand(2));
2914 } else {
2915 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2916 }
2917 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2918 SDValue Carry = Hi.getValue(1);
2919
2920 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2921 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
2922 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
2923 DAG.getConstant(32, dl, MVT::i64));
2924
2925 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
2926 SDValue Ops[2] = { Dst, Carry };
2927 return DAG.getMergeValues(Ops, dl);
2928 }
2929
2930 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2931 // in LegalizeDAG.cpp except the order of arguments to the library function.
LowerUMULO_SMULO(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2932 static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
2933 const SparcTargetLowering &TLI)
2934 {
2935 unsigned opcode = Op.getOpcode();
2936 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
2937
2938 bool isSigned = (opcode == ISD::SMULO);
2939 EVT VT = MVT::i64;
2940 EVT WideVT = MVT::i128;
2941 SDLoc dl(Op);
2942 SDValue LHS = Op.getOperand(0);
2943
2944 if (LHS.getValueType() != VT)
2945 return Op;
2946
2947 SDValue ShiftAmt = DAG.getConstant(63, dl, VT);
2948
2949 SDValue RHS = Op.getOperand(1);
2950 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
2951 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
2952 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
2953
2954 TargetLowering::MakeLibCallOptions CallOptions;
2955 CallOptions.setSExt(isSigned);
2956 SDValue MulResult = TLI.makeLibCall(DAG,
2957 RTLIB::MUL_I128, WideVT,
2958 Args, CallOptions, dl).first;
2959 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2960 MulResult, DAG.getIntPtrConstant(0, dl));
2961 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2962 MulResult, DAG.getIntPtrConstant(1, dl));
2963 if (isSigned) {
2964 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
2965 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
2966 } else {
2967 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, dl, VT),
2968 ISD::SETNE);
2969 }
2970 // MulResult is a node with an illegal type. Because such things are not
2971 // generally permitted during this phase of legalization, ensure that
2972 // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have
2973 // been folded.
2974 assert(MulResult->use_empty() && "Illegally typed node still in use!");
2975
2976 SDValue Ops[2] = { BottomHalf, TopHalf } ;
2977 return DAG.getMergeValues(Ops, dl);
2978 }
2979
LowerATOMIC_LOAD_STORE(SDValue Op,SelectionDAG & DAG)2980 static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
2981 if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getOrdering()))
2982 // Expand with a fence.
2983 return SDValue();
2984
2985 // Monotonic load/stores are legal.
2986 return Op;
2987 }
2988
LowerINTRINSIC_WO_CHAIN(SDValue Op,SelectionDAG & DAG) const2989 SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2990 SelectionDAG &DAG) const {
2991 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2992 SDLoc dl(Op);
2993 switch (IntNo) {
2994 default: return SDValue(); // Don't custom lower most intrinsics.
2995 case Intrinsic::thread_pointer: {
2996 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2997 return DAG.getRegister(SP::G7, PtrVT);
2998 }
2999 }
3000 }
3001
3002 SDValue SparcTargetLowering::
LowerOperation(SDValue Op,SelectionDAG & DAG) const3003 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3004
3005 bool hasHardQuad = Subtarget->hasHardQuad();
3006 bool isV9 = Subtarget->isV9();
3007
3008 switch (Op.getOpcode()) {
3009 default: llvm_unreachable("Should not custom lower this!");
3010
3011 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this,
3012 Subtarget);
3013 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
3014 Subtarget);
3015 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3016 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3017 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3018 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3019 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
3020 hasHardQuad);
3021 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
3022 hasHardQuad);
3023 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
3024 hasHardQuad);
3025 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
3026 hasHardQuad);
3027 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
3028 hasHardQuad);
3029 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
3030 hasHardQuad);
3031 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
3032 case ISD::VAARG: return LowerVAARG(Op, DAG);
3033 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
3034 Subtarget);
3035
3036 case ISD::LOAD: return LowerLOAD(Op, DAG);
3037 case ISD::STORE: return LowerSTORE(Op, DAG);
3038 case ISD::FADD: return LowerF128Op(Op, DAG,
3039 getLibcallName(RTLIB::ADD_F128), 2);
3040 case ISD::FSUB: return LowerF128Op(Op, DAG,
3041 getLibcallName(RTLIB::SUB_F128), 2);
3042 case ISD::FMUL: return LowerF128Op(Op, DAG,
3043 getLibcallName(RTLIB::MUL_F128), 2);
3044 case ISD::FDIV: return LowerF128Op(Op, DAG,
3045 getLibcallName(RTLIB::DIV_F128), 2);
3046 case ISD::FSQRT: return LowerF128Op(Op, DAG,
3047 getLibcallName(RTLIB::SQRT_F128),1);
3048 case ISD::FABS:
3049 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
3050 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
3051 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
3052 case ISD::ADDC:
3053 case ISD::ADDE:
3054 case ISD::SUBC:
3055 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
3056 case ISD::UMULO:
3057 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
3058 case ISD::ATOMIC_LOAD:
3059 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
3060 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3061 }
3062 }
3063
bitcastConstantFPToInt(ConstantFPSDNode * C,const SDLoc & DL,SelectionDAG & DAG) const3064 SDValue SparcTargetLowering::bitcastConstantFPToInt(ConstantFPSDNode *C,
3065 const SDLoc &DL,
3066 SelectionDAG &DAG) const {
3067 APInt V = C->getValueAPF().bitcastToAPInt();
3068 SDValue Lo = DAG.getConstant(V.zextOrTrunc(32), DL, MVT::i32);
3069 SDValue Hi = DAG.getConstant(V.lshr(32).zextOrTrunc(32), DL, MVT::i32);
3070 if (DAG.getDataLayout().isLittleEndian())
3071 std::swap(Lo, Hi);
3072 return DAG.getBuildVector(MVT::v2i32, DL, {Hi, Lo});
3073 }
3074
PerformBITCASTCombine(SDNode * N,DAGCombinerInfo & DCI) const3075 SDValue SparcTargetLowering::PerformBITCASTCombine(SDNode *N,
3076 DAGCombinerInfo &DCI) const {
3077 SDLoc dl(N);
3078 SDValue Src = N->getOperand(0);
3079
3080 if (isa<ConstantFPSDNode>(Src) && N->getSimpleValueType(0) == MVT::v2i32 &&
3081 Src.getSimpleValueType() == MVT::f64)
3082 return bitcastConstantFPToInt(cast<ConstantFPSDNode>(Src), dl, DCI.DAG);
3083
3084 return SDValue();
3085 }
3086
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const3087 SDValue SparcTargetLowering::PerformDAGCombine(SDNode *N,
3088 DAGCombinerInfo &DCI) const {
3089 switch (N->getOpcode()) {
3090 default:
3091 break;
3092 case ISD::BITCAST:
3093 return PerformBITCASTCombine(N, DCI);
3094 }
3095 return SDValue();
3096 }
3097
3098 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr & MI,MachineBasicBlock * BB) const3099 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
3100 MachineBasicBlock *BB) const {
3101 switch (MI.getOpcode()) {
3102 default: llvm_unreachable("Unknown SELECT_CC!");
3103 case SP::SELECT_CC_Int_ICC:
3104 case SP::SELECT_CC_FP_ICC:
3105 case SP::SELECT_CC_DFP_ICC:
3106 case SP::SELECT_CC_QFP_ICC:
3107 return expandSelectCC(MI, BB, SP::BCOND);
3108 case SP::SELECT_CC_Int_FCC:
3109 case SP::SELECT_CC_FP_FCC:
3110 case SP::SELECT_CC_DFP_FCC:
3111 case SP::SELECT_CC_QFP_FCC:
3112 return expandSelectCC(MI, BB, SP::FBCOND);
3113 }
3114 }
3115
3116 MachineBasicBlock *
expandSelectCC(MachineInstr & MI,MachineBasicBlock * BB,unsigned BROpcode) const3117 SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
3118 unsigned BROpcode) const {
3119 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
3120 DebugLoc dl = MI.getDebugLoc();
3121 unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm();
3122
3123 // To "insert" a SELECT_CC instruction, we actually have to insert the
3124 // triangle control-flow pattern. The incoming instruction knows the
3125 // destination vreg to set, the condition code register to branch on, the
3126 // true/false values to select between, and the condition code for the branch.
3127 //
3128 // We produce the following control flow:
3129 // ThisMBB
3130 // | \
3131 // | IfFalseMBB
3132 // | /
3133 // SinkMBB
3134 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3135 MachineFunction::iterator It = ++BB->getIterator();
3136
3137 MachineBasicBlock *ThisMBB = BB;
3138 MachineFunction *F = BB->getParent();
3139 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
3140 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3141 F->insert(It, IfFalseMBB);
3142 F->insert(It, SinkMBB);
3143
3144 // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
3145 SinkMBB->splice(SinkMBB->begin(), ThisMBB,
3146 std::next(MachineBasicBlock::iterator(MI)), ThisMBB->end());
3147 SinkMBB->transferSuccessorsAndUpdatePHIs(ThisMBB);
3148
3149 // Set the new successors for ThisMBB.
3150 ThisMBB->addSuccessor(IfFalseMBB);
3151 ThisMBB->addSuccessor(SinkMBB);
3152
3153 BuildMI(ThisMBB, dl, TII.get(BROpcode))
3154 .addMBB(SinkMBB)
3155 .addImm(CC);
3156
3157 // IfFalseMBB just falls through to SinkMBB.
3158 IfFalseMBB->addSuccessor(SinkMBB);
3159
3160 // %Result = phi [ %TrueValue, ThisMBB ], [ %FalseValue, IfFalseMBB ]
3161 BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI),
3162 MI.getOperand(0).getReg())
3163 .addReg(MI.getOperand(1).getReg())
3164 .addMBB(ThisMBB)
3165 .addReg(MI.getOperand(2).getReg())
3166 .addMBB(IfFalseMBB);
3167
3168 MI.eraseFromParent(); // The pseudo instruction is gone now.
3169 return SinkMBB;
3170 }
3171
3172 //===----------------------------------------------------------------------===//
3173 // Sparc Inline Assembly Support
3174 //===----------------------------------------------------------------------===//
3175
3176 /// getConstraintType - Given a constraint letter, return the type of
3177 /// constraint it is for this target.
3178 SparcTargetLowering::ConstraintType
getConstraintType(StringRef Constraint) const3179 SparcTargetLowering::getConstraintType(StringRef Constraint) const {
3180 if (Constraint.size() == 1) {
3181 switch (Constraint[0]) {
3182 default: break;
3183 case 'r':
3184 case 'f':
3185 case 'e':
3186 return C_RegisterClass;
3187 case 'I': // SIMM13
3188 return C_Immediate;
3189 }
3190 }
3191
3192 return TargetLowering::getConstraintType(Constraint);
3193 }
3194
3195 TargetLowering::ConstraintWeight SparcTargetLowering::
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const3196 getSingleConstraintMatchWeight(AsmOperandInfo &info,
3197 const char *constraint) const {
3198 ConstraintWeight weight = CW_Invalid;
3199 Value *CallOperandVal = info.CallOperandVal;
3200 // If we don't have a value, we can't do a match,
3201 // but allow it at the lowest weight.
3202 if (!CallOperandVal)
3203 return CW_Default;
3204
3205 // Look at the constraint type.
3206 switch (*constraint) {
3207 default:
3208 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3209 break;
3210 case 'I': // SIMM13
3211 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3212 if (isInt<13>(C->getSExtValue()))
3213 weight = CW_Constant;
3214 }
3215 break;
3216 }
3217 return weight;
3218 }
3219
3220 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3221 /// vector. If it is invalid, don't add anything to Ops.
3222 void SparcTargetLowering::
LowerAsmOperandForConstraint(SDValue Op,std::string & Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const3223 LowerAsmOperandForConstraint(SDValue Op,
3224 std::string &Constraint,
3225 std::vector<SDValue> &Ops,
3226 SelectionDAG &DAG) const {
3227 SDValue Result(nullptr, 0);
3228
3229 // Only support length 1 constraints for now.
3230 if (Constraint.length() > 1)
3231 return;
3232
3233 char ConstraintLetter = Constraint[0];
3234 switch (ConstraintLetter) {
3235 default: break;
3236 case 'I':
3237 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3238 if (isInt<13>(C->getSExtValue())) {
3239 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
3240 Op.getValueType());
3241 break;
3242 }
3243 return;
3244 }
3245 }
3246
3247 if (Result.getNode()) {
3248 Ops.push_back(Result);
3249 return;
3250 }
3251 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3252 }
3253
3254 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const3255 SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3256 StringRef Constraint,
3257 MVT VT) const {
3258 if (Constraint.size() == 1) {
3259 switch (Constraint[0]) {
3260 case 'r':
3261 if (VT == MVT::v2i32)
3262 return std::make_pair(0U, &SP::IntPairRegClass);
3263 else if (Subtarget->is64Bit())
3264 return std::make_pair(0U, &SP::I64RegsRegClass);
3265 else
3266 return std::make_pair(0U, &SP::IntRegsRegClass);
3267 case 'f':
3268 if (VT == MVT::f32 || VT == MVT::i32)
3269 return std::make_pair(0U, &SP::FPRegsRegClass);
3270 else if (VT == MVT::f64 || VT == MVT::i64)
3271 return std::make_pair(0U, &SP::LowDFPRegsRegClass);
3272 else if (VT == MVT::f128)
3273 return std::make_pair(0U, &SP::LowQFPRegsRegClass);
3274 // This will generate an error message
3275 return std::make_pair(0U, nullptr);
3276 case 'e':
3277 if (VT == MVT::f32 || VT == MVT::i32)
3278 return std::make_pair(0U, &SP::FPRegsRegClass);
3279 else if (VT == MVT::f64 || VT == MVT::i64 )
3280 return std::make_pair(0U, &SP::DFPRegsRegClass);
3281 else if (VT == MVT::f128)
3282 return std::make_pair(0U, &SP::QFPRegsRegClass);
3283 // This will generate an error message
3284 return std::make_pair(0U, nullptr);
3285 }
3286 } else if (!Constraint.empty() && Constraint.size() <= 5
3287 && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
3288 // constraint = '{r<d>}'
3289 // Remove the braces from around the name.
3290 StringRef name(Constraint.data()+1, Constraint.size()-2);
3291 // Handle register aliases:
3292 // r0-r7 -> g0-g7
3293 // r8-r15 -> o0-o7
3294 // r16-r23 -> l0-l7
3295 // r24-r31 -> i0-i7
3296 uint64_t intVal = 0;
3297 if (name.substr(0, 1).equals("r")
3298 && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3299 const char regTypes[] = { 'g', 'o', 'l', 'i' };
3300 char regType = regTypes[intVal/8];
3301 char regIdx = '0' + (intVal % 8);
3302 char tmp[] = { '{', regType, regIdx, '}', 0 };
3303 std::string newConstraint = std::string(tmp);
3304 return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint,
3305 VT);
3306 }
3307 if (name.substr(0, 1).equals("f") &&
3308 !name.substr(1).getAsInteger(10, intVal) && intVal <= 63) {
3309 std::string newConstraint;
3310
3311 if (VT == MVT::f32 || VT == MVT::Other) {
3312 newConstraint = "{f" + utostr(intVal) + "}";
3313 } else if (VT == MVT::f64 && (intVal % 2 == 0)) {
3314 newConstraint = "{d" + utostr(intVal / 2) + "}";
3315 } else if (VT == MVT::f128 && (intVal % 4 == 0)) {
3316 newConstraint = "{q" + utostr(intVal / 4) + "}";
3317 } else {
3318 return std::make_pair(0U, nullptr);
3319 }
3320 return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint,
3321 VT);
3322 }
3323 }
3324
3325 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3326 }
3327
3328 bool
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const3329 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3330 // The Sparc target isn't yet aware of offsets.
3331 return false;
3332 }
3333
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const3334 void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3335 SmallVectorImpl<SDValue>& Results,
3336 SelectionDAG &DAG) const {
3337
3338 SDLoc dl(N);
3339
3340 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3341
3342 switch (N->getOpcode()) {
3343 default:
3344 llvm_unreachable("Do not know how to custom type legalize this operation!");
3345
3346 case ISD::FP_TO_SINT:
3347 case ISD::FP_TO_UINT:
3348 // Custom lower only if it involves f128 or i64.
3349 if (N->getOperand(0).getValueType() != MVT::f128
3350 || N->getValueType(0) != MVT::i64)
3351 return;
3352 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3353 ? RTLIB::FPTOSINT_F128_I64
3354 : RTLIB::FPTOUINT_F128_I64);
3355
3356 Results.push_back(LowerF128Op(SDValue(N, 0),
3357 DAG,
3358 getLibcallName(libCall),
3359 1));
3360 return;
3361 case ISD::READCYCLECOUNTER: {
3362 assert(Subtarget->hasLeonCycleCounter());
3363 SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), dl, SP::ASR23, MVT::i32);
3364 SDValue Hi = DAG.getCopyFromReg(Lo, dl, SP::G0, MVT::i32);
3365 SDValue Ops[] = { Lo, Hi };
3366 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops);
3367 Results.push_back(Pair);
3368 Results.push_back(N->getOperand(0));
3369 return;
3370 }
3371 case ISD::SINT_TO_FP:
3372 case ISD::UINT_TO_FP:
3373 // Custom lower only if it involves f128 or i64.
3374 if (N->getValueType(0) != MVT::f128
3375 || N->getOperand(0).getValueType() != MVT::i64)
3376 return;
3377
3378 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3379 ? RTLIB::SINTTOFP_I64_F128
3380 : RTLIB::UINTTOFP_I64_F128);
3381
3382 Results.push_back(LowerF128Op(SDValue(N, 0),
3383 DAG,
3384 getLibcallName(libCall),
3385 1));
3386 return;
3387 case ISD::LOAD: {
3388 LoadSDNode *Ld = cast<LoadSDNode>(N);
3389 // Custom handling only for i64: turn i64 load into a v2i32 load,
3390 // and a bitcast.
3391 if (Ld->getValueType(0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64)
3392 return;
3393
3394 SDLoc dl(N);
3395 SDValue LoadRes = DAG.getExtLoad(
3396 Ld->getExtensionType(), dl, MVT::v2i32, Ld->getChain(),
3397 Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, Ld->getAlignment(),
3398 Ld->getMemOperand()->getFlags(), Ld->getAAInfo());
3399
3400 SDValue Res = DAG.getNode(ISD::BITCAST, dl, MVT::i64, LoadRes);
3401 Results.push_back(Res);
3402 Results.push_back(LoadRes.getValue(1));
3403 return;
3404 }
3405 }
3406 }
3407
3408 // Override to enable LOAD_STACK_GUARD lowering on Linux.
useLoadStackGuardNode() const3409 bool SparcTargetLowering::useLoadStackGuardNode() const {
3410 if (!Subtarget->isTargetLinux())
3411 return TargetLowering::useLoadStackGuardNode();
3412 return true;
3413 }
3414
3415 // Override to disable global variable loading on Linux.
insertSSPDeclarations(Module & M) const3416 void SparcTargetLowering::insertSSPDeclarations(Module &M) const {
3417 if (!Subtarget->isTargetLinux())
3418 return TargetLowering::insertSSPDeclarations(M);
3419 }
3420