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1 /*
2  * Copyright © 2016 Red Hat.
3  * Copyright © 2016 Bas Nieuwenhuizen
4  *
5  * based in part on anv driver which is:
6  * Copyright © 2015 Intel Corporation
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25  * IN THE SOFTWARE.
26  */
27 
28 #ifndef RADV_CONSTANTS_H
29 #define RADV_CONSTANTS_H
30 
31 #define ATI_VENDOR_ID 0x1002
32 
33 #define MAX_VBS                        32
34 #define MAX_VERTEX_ATTRIBS             32
35 #define MAX_RTS                        8
36 #define MAX_VIEWPORTS                  16
37 #define MAX_SCISSORS                   16
38 #define MAX_DISCARD_RECTANGLES         4
39 #define MAX_SAMPLE_LOCATIONS           32
40 #define MAX_PUSH_CONSTANTS_SIZE        256
41 #define MAX_PUSH_DESCRIPTORS           32
42 #define MAX_DYNAMIC_UNIFORM_BUFFERS    16
43 #define MAX_DYNAMIC_STORAGE_BUFFERS    8
44 #define MAX_DYNAMIC_BUFFERS            (MAX_DYNAMIC_UNIFORM_BUFFERS + MAX_DYNAMIC_STORAGE_BUFFERS)
45 #define MAX_SAMPLES_LOG2               4
46 #define NUM_META_FS_KEYS               12
47 #define RADV_MAX_DRM_DEVICES           8
48 #define MAX_VIEWS                      8
49 #define MAX_SO_STREAMS                 4
50 #define MAX_SO_BUFFERS                 4
51 #define MAX_SO_OUTPUTS                 64
52 #define MAX_INLINE_UNIFORM_BLOCK_SIZE  (4ull * 1024 * 1024)
53 #define MAX_INLINE_UNIFORM_BLOCK_COUNT 64
54 #define MAX_BIND_POINTS                3 /* compute + graphics + raytracing */
55 
56 #define NUM_DEPTH_CLEAR_PIPELINES      2
57 #define NUM_DEPTH_DECOMPRESS_PIPELINES 3
58 #define MAX_FRAMEBUFFER_WIDTH (1u << 14)
59 #define MAX_FRAMEBUFFER_HEIGHT (1u << 14)
60 
61 /*
62  * This is the point we switch from using CP to compute shader
63  * for certain buffer operations.
64  */
65 #define RADV_BUFFER_OPS_CS_THRESHOLD 4096
66 
67 #define RADV_BUFFER_UPDATE_THRESHOLD 1024
68 
69 /* descriptor index into scratch ring offsets */
70 #define RING_SCRATCH             0
71 #define RING_ESGS_VS             1
72 #define RING_ESGS_GS             2
73 #define RING_GSVS_VS             3
74 #define RING_GSVS_GS             4
75 #define RING_HS_TESS_FACTOR      5
76 #define RING_HS_TESS_OFFCHIP     6
77 #define RING_TS_DRAW             7
78 #define RING_TS_PAYLOAD          8
79 #define RING_MS_SCRATCH          9
80 #define RING_PS_SAMPLE_POSITIONS 10
81 
82 /* max number of descriptor sets */
83 #define MAX_SETS 32
84 
85 /* Make sure everything is addressable by a signed 32-bit int, and
86  * our largest descriptors are 96 bytes.
87  */
88 #define RADV_MAX_PER_SET_DESCRIPTORS ((1ull << 31) / 96)
89 
90 /* Our buffer size fields allow only 2**32 - 1. We round that down to a multiple
91  * of 4 bytes so we can align buffer sizes up.
92  */
93 #define RADV_MAX_MEMORY_ALLOCATION_SIZE 0xFFFFFFFCull
94 
95 /* Number of entries in the mesh shader scratch ring.
96  * This depends on VGT_GS_MAX_WAVE_ID which is set by the kernel
97  * and is impossible to query. We leave it on its maximum value
98  * because real applications are unlikely to use it.
99  *
100  * The maximum ID on GFX10.3 is 2047 (0x7ff), so we need 2048 entries.
101  */
102 #define RADV_MESH_SCRATCH_NUM_ENTRIES 2048
103 
104 /* Size of each entry in the mesh shader scratch ring.
105  * We must ensure that the absolute maximum mesh shader output fits here.
106  *
107  * Mesh shaders can create up to 256 vertices/primitives per workgroup,
108  * and up to the following amount of outputs:
109  * - 32 parameters
110  * - 4 positions (clip/cull distance, etc.)
111  * - 4 per-primitive built-in outputs (layer, view index, prim id, VRS rate)
112  * - primitive indices which are always kept in LDS
113  * That is a total of 32+4+4=40 output slots x 16 bytes per slot x 256 = 160K bytes.
114  */
115 #define RADV_MESH_SCRATCH_ENTRY_BYTES (160 * 1024)
116 
117 /* Number of invocations in each subgroup. */
118 #define RADV_SUBGROUP_SIZE 64
119 
120 /* The spec requires this to be 32. */
121 #define RADV_RT_HANDLE_SIZE 32
122 
123 #define RADV_MAX_HIT_ATTRIB_SIZE 32
124 
125 #define RADV_SHADER_ALLOC_ALIGNMENT      256
126 #define RADV_SHADER_ALLOC_MIN_ARENA_SIZE (256 * 1024)
127 /* 256 KiB << 5 = 8 MiB */
128 #define RADV_SHADER_ALLOC_MAX_ARENA_SIZE_SHIFT 5u
129 #define RADV_SHADER_ALLOC_MIN_SIZE_CLASS 8
130 #define RADV_SHADER_ALLOC_MAX_SIZE_CLASS 15
131 #define RADV_SHADER_ALLOC_NUM_FREE_LISTS                                                           \
132    (RADV_SHADER_ALLOC_MAX_SIZE_CLASS - RADV_SHADER_ALLOC_MIN_SIZE_CLASS + 1)
133 
134 #define PERF_CTR_MAX_PASSES      512
135 #define PERF_CTR_BO_PASS_OFFSET  16
136 #define PERF_CTR_BO_LOCK_OFFSET  0
137 #define PERF_CTR_BO_FENCE_OFFSET 8
138 
139 #endif /* RADV_CONSTANTS_H */
140