1 /* 2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef MDIO_H 17 #define MDIO_H 18 19 #include "eth_mac.h" 20 21 #ifdef __cplusplus 22 #if __cplusplus 23 extern "C" { 24 #endif /* __cplusplus */ 25 #endif /* __cplusplus */ 26 27 #define MDIO_RWCTRL 0x1100 28 #define MDIO_RO_DATA 0x1104 29 #define U_MDIO_PHYADDR 0x0108 30 #define D_MDIO_PHYADDR 0x2108 31 #define U_MDIO_RO_STAT 0x010C 32 #define D_MDIO_RO_STAT 0x210C 33 #define U_MDIO_ANEG_CTRL 0x0110 34 #define D_MDIO_ANEG_CTRL 0x2110 35 #define U_MDIO_IRQENA 0x0114 36 #define D_MDIO_IRQENA 0x2114 37 38 #define MDIO_MK_RWCTL(cpuDataIn, finish, rw, phyExAddr, frqDiv, phyRegNum) \ 39 (((uint32_t)(cpuDataIn) << 16) | \ 40 (((finish) & 0x01) << 15) | \ 41 (((rw) & 0x01) << 13) | \ 42 (((uint32_t)(phyExAddr) & 0x1F) << 8) | \ 43 (((uint32_t)(frqDiv) & 0x7) << 5) | \ 44 ((uint32_t)(phyRegNum) & 0x1F)) 45 46 /* hardware set bit'15 of MDIO_REG(0) if mdio ready */ 47 #define TestMdioReady(ld) (HiethRead(ld, MDIO_RWCTRL) & (1 << 15)) 48 49 #define MdioStartPhyread(ld, phyAddr, regNum) \ 50 HiethWrite(ld, MDIO_MK_RWCTL(0, 0, 0, phyAddr, (ld)->mdioFrqdiv, regNum), MDIO_RWCTRL) 51 52 #define MdioGetPhyreadVal(ld) (HiethRead(ld, MDIO_RO_DATA) & 0xFFFF) 53 54 #define MdioPhyWrite(ld, phyAddr, regNum, val) \ 55 HiethWrite(ld, MDIO_MK_RWCTL(val, 0, 1, phyAddr, (ld)->mdioFrqdiv, regNum), MDIO_RWCTRL) 56 57 /* write mdio registers reset value */ 58 #define MdioRegReset(ld) \ 59 do { \ 60 HiethWrite(ld, 0x00008000, MDIO_RWCTRL); \ 61 HiethWrite(ld, 0x00000001, U_MDIO_PHYADDR); \ 62 HiethWrite(ld, 0x00000001, D_MDIO_PHYADDR); \ 63 HiethWrite(ld, 0x04631EA9, U_MDIO_ANEG_CTRL); \ 64 HiethWrite(ld, 0x04631EA9, D_MDIO_ANEG_CTRL); \ 65 HiethWrite(ld, 0x00000000, U_MDIO_IRQENA); \ 66 HiethWrite(ld, 0x00000000, D_MDIO_IRQENA); \ 67 } while (0) 68 69 int32_t HiethMdioRead(struct HiethNetdevLocal *ld, int32_t phyAddr, int32_t regNum); 70 int32_t HiethMdioWrite(struct HiethNetdevLocal *ld, int32_t phyAddr, int32_t regNum, int32_t val); 71 int32_t HiethMdioReset(struct HiethNetdevLocal *ld); 72 int32_t HiethMdioInit(struct HiethNetdevLocal *ld); 73 void HiethMdioExit(struct HiethNetdevLocal *ld); 74 75 #ifdef __cplusplus 76 #if __cplusplus 77 } 78 #endif /* __cplusplus */ 79 #endif /* __cplusplus */ 80 81 #endif /* MDIO_H */ 82