1 /* 2 * Copyright (C) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef __DRV_OSAL_HI3516CV500_H__ 20 #define __DRV_OSAL_HI3516CV500_H__ 21 22 /* the total cipher hard channel which we can used. */ 23 #define CIPHER_HARD_CHANNEL_CNT 0x07 24 /* mask which cipher channel we can used, bit0 means channel 0. */ 25 #define CIPHER_HARD_CHANNEL_MASK 0xFE 26 27 /* the total hash hard channel which we can used. */ 28 #define HASH_HARD_CHANNEL_CNT 0x01 29 30 /* liteos resource config */ 31 #ifdef __HuaweiLite__ 32 /* mask which cipher channel we can used, bit0 means channel 0. */ 33 #define HASH_HARD_CHANNEL_MASK 0x04 34 #define HASH_HARD_CHANNEL 0x02 35 #else 36 /* mask which cipher channel we can used, bit0 means channel 0. */ 37 #define HASH_HARD_CHANNEL_MASK 0x02 38 #define HASH_HARD_CHANNEL 0x01 39 #endif 40 41 /* the total cipher hard key channel which we can used. */ 42 #define CIPHER_HARD_KEY_CHANNEL_CNT 0x04 43 44 /* mask which cipher hard key channel we can used, bit0 means channel 0. */ 45 #define CIPHER_HARD_KEY_CHANNEL_MASK 0xF0 46 47 /* support read IRQ number from DTS */ 48 #define IRQ_DTS_SUPPORT 49 50 /* support OTP load key */ 51 #define OTP_SUPPORT 52 53 /* support reducing power dissipation. */ 54 #define CRYPTO_CORE_AUTO_CKEN_SUPPORT 55 56 #ifndef __HuaweiLite__ 57 /* support interrupt. */ 58 #define CRYPTO_OS_INT_SUPPORT 59 #endif 60 61 /* the hardware version */ 62 #define CHIP_SYMC_VER_V200 63 #define CHIP_HASH_VER_V200 64 #define CHIP_TRNG_VER_V200 65 #define CHIP_IFEP_RSA_VER_V100 66 67 /* 68 * SMP version linux is sec config 69 * module unsupported, we need set the table. 70 */ 71 #define BASE_TABLE_NULL { \ 72 .reset_valid = 0, \ 73 .clk_valid = 0, \ 74 .phy_valid = 0, \ 75 .crg_valid = 0, \ 76 .ver_valid = 0, \ 77 .int_valid = 0, \ 78 } 79 80 /* support des */ 81 #define CHIP_DES_SUPPORT 82 83 /* support 3des */ 84 #define CHIP_3DES_SUPPORT 85 86 /* support sha1 */ 87 #define CHIP_SHA1_SUPPORT 88 89 /* support sha224 */ 90 #define CHIP_SHA224_SUPPORT 91 92 /* support rsa1024 */ 93 #define CHIP_RSA1024_SUPPORT 94 95 /* mbedtls hardening */ 96 #define SOFT_RSA_PADDING_SUPPORT 97 98 /* support trng version v200. 99 * CHIP_TRNG_VER_V200 100 * 101 * supoort odd key. 102 * CHIP_SYMC_ODD_KEY_SUPPORT 103 * 104 * support rsa3072 105 * CHIP_RSA3072_SUPPORT 106 * 107 * supoort SM1. 108 * CHIP_SYMC_SM1_SUPPORT 109 * 110 * the hardware capacity. 111 * CHIP_AES_CCM_GCM_SUPPORT 112 * 113 * supoort sm2 ver v100. 114 * CHIP_SM2_VER_V100 115 * 116 * RSA rand mask. 117 * RSA_RAND_MASK 118 * 119 * support smmu. 120 * CRYPTO_SMMU_SUPPORT 121 * 122 * support secure cpu 123 * CRYPTO_SEC_CPU 124 * 125 * support switch cpu. 126 * CRYPTO_SWITCH_CPU 127 * 128 * the software capacity. 129 * SOFT_AES_SUPPORT 130 * SOFT_TDES_SUPPORT 131 * SOFT_AES_CCM_GCM_SUPPORT 132 * SOFT_SHA1_SUPPORT 133 * SOFT_SHA256_SUPPORT 134 * SOFT_SHA512_SUPPORT 135 * SOFT_SM2_SUPPORT 136 * SOFT_SM3_SUPPORT 137 * SOFT_ECC_SUPPORT 138 * SOFT_AES_CTS_SUPPORT 139 */ 140 #if defined(ARCH_TYPE_amp) && !defined(AMP_NONSECURE_VERSION) && !defined(__HuaweiLite__) 141 142 /* linux of AMP use non-secure config. */ 143 #define HARD_INFO_TRNG BASE_TABLE_NULL 144 145 #define HARD_INFO_CIPHER { \ 146 .name = "nonsec_cipher", \ 147 .reset_valid = 1, \ 148 .clk_valid = 1, \ 149 .phy_valid = 1, \ 150 .crg_valid = 1, \ 151 .ver_valid = 1, \ 152 .int_valid = 1, \ 153 .int_num = 104, \ 154 .reset_bit = 8, \ 155 .clk_bit = 9, \ 156 .version_reg = 0x308, \ 157 .version_val = 0x2018121, \ 158 .reg_addr_phy = 0x100C0000, \ 159 .reg_addr_size = 0x4000, \ 160 .crg_addr_phy = 0x120101A0, \ 161 } 162 163 /* define initial value of struct sys_arch_boot_dts for cipher. */ 164 #define HARD_INFO_HASH { \ 165 .name = "nonsec_hash", \ 166 .reset_valid = 0, \ 167 .clk_valid = 0, \ 168 .phy_valid = 1, \ 169 .crg_valid = 0, \ 170 .ver_valid = 1, \ 171 .int_valid = 1, \ 172 .int_num = 104, \ 173 .reset_bit = 8, \ 174 .clk_bit = 9, \ 175 .version_reg = 0x308, \ 176 .version_val = 0x2018121, \ 177 .reg_addr_phy = 0x100C0000, \ 178 .reg_addr_size = 0x4000, \ 179 .crg_addr_phy = 0x120101A0, \ 180 } 181 182 /* define initial value of struct sys_arch_boot_dts for IFEP RSA. */ 183 #define HARD_INFO_IFEP_RSA { \ 184 .name = "nonsec_rsa", \ 185 .reset_valid = 1, \ 186 .clk_valid = 1, \ 187 .phy_valid = 1, \ 188 .crg_valid = 1, \ 189 .ver_valid = 1, \ 190 .int_valid = 0, \ 191 .reg_addr_phy = 0x100D0000, \ 192 .reg_addr_size = 0x1000, \ 193 .crg_addr_phy = 0x120101A0, \ 194 .reset_bit = 6, \ 195 .clk_bit = 7, \ 196 .version_reg = 0x90, \ 197 .version_val = 0, \ 198 } 199 #else 200 /* SMP, liteos of secure AMP, linux of non-secure AMP use secure config. */ 201 #define CRYPTO_SEC_CPU 202 203 #define CHIP_TRNG_VER_V200 204 205 /* define initial value of struct sys_arch_boot_dts for cipher. */ 206 #define HARD_INFO_CIPHER { \ 207 .name = "cipher", \ 208 .reset_valid = 1, \ 209 .clk_valid = 1, \ 210 .phy_valid = 1, \ 211 .crg_valid = 1, \ 212 .ver_valid = 1, \ 213 .int_valid = 1, \ 214 .int_num = 103, \ 215 .reset_bit = 8, \ 216 .clk_bit = 9, \ 217 .version_reg = 0x308, \ 218 .version_val = 0x2018121, \ 219 .reg_addr_phy = 0x100C0000, \ 220 .reg_addr_size = 0x4000, \ 221 .crg_addr_phy = 0x120101A0, \ 222 } 223 224 /* define initial value of struct sys_arch_boot_dts for cipher. */ 225 #define HARD_INFO_HASH { \ 226 .name = "hash", \ 227 .reset_valid = 0, \ 228 .clk_valid = 0, \ 229 .phy_valid = 1, \ 230 .crg_valid = 0, \ 231 .ver_valid = 1, \ 232 .int_valid = 1, \ 233 .int_num = 103, \ 234 .reset_bit = 8, \ 235 .clk_bit = 9, \ 236 .version_reg = 0x308, \ 237 .version_val = 0x2018121, \ 238 .reg_addr_phy = 0x100C0000, \ 239 .reg_addr_size = 0x4000, \ 240 .crg_addr_phy = 0x120101A0, \ 241 } 242 243 /* define sec rsa1 for SMP VERSION. */ 244 #define HARD_INFO_IFEP_RSA { \ 245 .name = "rsa0", \ 246 .reset_valid = 1, \ 247 .clk_valid = 1, \ 248 .phy_valid = 1, \ 249 .crg_valid = 1, \ 250 .ver_valid = 1, \ 251 .int_valid = 0, \ 252 .reg_addr_phy = 0x10080000, \ 253 .reg_addr_size = 0x1000, \ 254 .crg_addr_phy = 0x120101A0, \ 255 .reset_bit = 4, \ 256 .clk_bit = 5, \ 257 .version_reg = 0x90, \ 258 .version_val = 0, \ 259 } 260 261 /* define initial value of struct sys_arch_boot_dts for HASH. */ 262 #define HARD_INFO_TRNG { \ 263 .name = "trng", \ 264 .reset_valid = 1, \ 265 .clk_valid = 1, \ 266 .phy_valid = 1, \ 267 .crg_valid = 1, \ 268 .ver_valid = 0, \ 269 .int_valid = 0, \ 270 .reset_bit = 2, \ 271 .clk_bit = 3, \ 272 .reg_addr_phy = 0x10090200, \ 273 .reg_addr_size = 0x100, \ 274 .crg_addr_phy = 0x120101A0, \ 275 } 276 #endif 277 278 #define KLAD_REG_BASE_ADDR_PHY 0x10070000 279 #define OTP_REG_BASE_ADDR_PHY 0x100B0000 280 #define KLAD_CRG_ADDR_PHY 0x120101A0 281 #define REG_SYS_OTP_CLK_ADDR_PHY 0x120101BC 282 283 #define OTP_CRG_CLOCK_BIT (0x01 << 1) 284 285 #define KLAD_CRG_CLOCK_BIT (0x01 << 1) 286 #define KLAD_CRG_RESET_BIT (0x01 << 0) 287 288 #define HARD_INFO_SMMU BASE_TABLE_NULL 289 #define HARD_INFO_SIC_RSA BASE_TABLE_NULL 290 #define HARD_INFO_CIPHER_KEY BASE_TABLE_NULL 291 #define HARD_INFO_SM4 BASE_TABLE_NULL 292 #define HARD_INFO_SM2 BASE_TABLE_NULL 293 294 #define NSEC_HARD_INFO_CIPHER BASE_TABLE_NULL 295 #define NSEC_HARD_INFO_HASH BASE_TABLE_NULL 296 #define NSEC_HARD_INFO_IFEP_RSA BASE_TABLE_NULL 297 #define NSEC_HARD_INFO_SMMU BASE_TABLE_NULL 298 #define NSEC_HARD_INFO_SIC_RSA BASE_TABLE_NULL 299 #define NSEC_HARD_INFO_CIPHER_KEY BASE_TABLE_NULL 300 #define NSEC_HARD_INFO_SM4 BASE_TABLE_NULL 301 #define NSEC_HARD_INFO_SM2 BASE_TABLE_NULL 302 #define NSEC_HARD_INFO_TRNG BASE_TABLE_NULL 303 304 #endif /* __DRV_OSAL_HI3516CV500_H__ */ 305