1 /* 2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef ETH_PHY_H 17 #define ETH_PHY_H 18 19 #include "los_typedef.h" 20 21 #include "hieth_pri.h" 22 23 #ifdef __cplusplus 24 #if __cplusplus 25 extern "C" { 26 #endif /* __cplusplus */ 27 #endif /* __cplusplus */ 28 29 #define PHY_BMCR 0x00 30 #define BMCR_RESET 0x8000 31 #define BMCR_LOOPBACK 0x4000 32 #define BMCR_SPEED100 0x2000 33 #define BMCR_AN_ENABLE 0x1000 34 #define BMCR_POWER_DOWN 0x0800 35 #define BMCR_ISOLATE 0x0400 36 #define BMCR_AN_RESTART 0x0200 37 #define BMCR_FULL_DUPLEX 0x0100 38 #define BMCR_COLL_TEST 0x0080 39 40 #define PHY_BMSR 0x01 41 #define BMSR_100T4 0x8000 42 #define BMSR_100FULL 0x4000 43 #define BMSR_100HALF 0x2000 44 #define BMSR_10FULL 0x1000 45 #define BMSR_10HALF 0x0800 46 #define BMSR_ESTATEN 0x0100 47 #define BMSR_AN_COMPLETE 0x0020 48 #define BMSR_LINK 0x0004 49 50 #define PHY_ID1 0x02 /* PHY ID register 1 (high 16 bits) */ 51 #define PHY_ID2 0x03 /* PHY ID register 2 (low 16 bits) */ 52 53 #define PHY_ANLPAR 0x05 /* Auto negotiation link partner ability */ 54 #define ANLPAR_NP 0x8000 55 #define ANLPAR_ACK 0x4000 56 #define ANLPAR_RF 0x2000 57 #define ANLPAR_ASYMP 0x0800 58 #define ANLPAR_PAUSE 0x0400 59 #define ANLPAR_T4 0x0200 60 #define ANLPAR_TXFD 0x0100 61 #define ANLPAR_TX 0x0080 62 #define ANLPAR_10FD 0x0040 63 #define ANLPAR_10 0x0020 64 #define ANLPAR_100 0x0380 65 66 #define PHY_1000BTSR 0x0A 67 #define PHY_1000BTSR_MSCF 0x8000 68 #define PHY_1000BTSR_MSCR 0x4000 69 #define PHY_1000BTSR_LRS 0x2000 70 #define PHY_1000BTSR_RRS 0x1000 71 #define PHY_1000BTSR_1000FD 0x0800 72 #define PHY_1000BTSR_1000HD 0x0400 73 74 #define PHY_EXSR 0x0F 75 #define EXSR_1000XF 0x8000 76 #define EXSR_1000XH 0x4000 77 #define EXSR_1000TF 0x2000 78 #define EXSR_1000TH 0x1000 79 80 /* The ethernet phy speed: 10Mb, 100Mb, 1Gb */ 81 #define PHY_SPEED_10 10 82 #define PHY_SPEED_100 100 83 #define PHY_SPEED_1000 1000 84 #define PHY_SPEED_UNKNOWN -1 85 86 /* The ethernet phy duplex: half or full */ 87 #define PHY_DUPLEX_HALF 0x00 88 #define PHY_DUPLEX_FULL 0x01 89 90 #define MAX_PHY_ADDR 31 91 92 /* Physical device access - defined by hardware instance */ 93 typedef struct { 94 bool initDone; 95 void (*init)(void); 96 void (*reset)(void); 97 int32_t phyAddr; 98 int32_t phyMode; 99 } EthPhyAccess; 100 101 #define ETH_PHY_STAT_LINK 0x0001 /* Link up/down */ 102 #define ETH_PHY_STAT_100MB 0x0002 /* Connection is 100Mb/10Mb */ 103 #define ETH_PHY_STAT_FDX 0x0004 /* Connection is full/half duplex */ 104 105 bool HiethGetPhyStat(struct HiethNetdevLocal *pld, EthPhyAccess *phyAccess, uint32_t *state); 106 int32_t MiiphyLink(struct HiethNetdevLocal *pld, EthPhyAccess *phyAccess); 107 int32_t MiiphySpeed(struct HiethNetdevLocal *pld, EthPhyAccess *phyAccess); 108 int32_t MiiphyDuplex(struct HiethNetdevLocal *pld, EthPhyAccess *phyAccess); 109 110 #ifdef __cplusplus 111 #if __cplusplus 112 } 113 #endif /* __cplusplus */ 114 #endif /* __cplusplus */ 115 116 #endif /* ETH_PHY_H */ 117