1 /************************************************************************** 2 * 3 * Copyright 2007 VMware, Inc. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #ifndef PIPE_DEFINES_H 29 #define PIPE_DEFINES_H 30 31 #include "p_compiler.h" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /** 38 * Gallium error codes. 39 * 40 * - A zero value always means success. 41 * - A negative value always means failure. 42 * - The meaning of a positive value is function dependent. 43 */ 44 enum pipe_error 45 { 46 PIPE_OK = 0, 47 PIPE_ERROR = -1, /**< Generic error */ 48 PIPE_ERROR_BAD_INPUT = -2, 49 PIPE_ERROR_OUT_OF_MEMORY = -3, 50 PIPE_ERROR_RETRY = -4 51 /* TODO */ 52 }; 53 54 enum pipe_blendfactor { 55 PIPE_BLENDFACTOR_ONE = 1, 56 PIPE_BLENDFACTOR_SRC_COLOR, 57 PIPE_BLENDFACTOR_SRC_ALPHA, 58 PIPE_BLENDFACTOR_DST_ALPHA, 59 PIPE_BLENDFACTOR_DST_COLOR, 60 PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE, 61 PIPE_BLENDFACTOR_CONST_COLOR, 62 PIPE_BLENDFACTOR_CONST_ALPHA, 63 PIPE_BLENDFACTOR_SRC1_COLOR, 64 PIPE_BLENDFACTOR_SRC1_ALPHA, 65 66 PIPE_BLENDFACTOR_ZERO = 0x11, 67 PIPE_BLENDFACTOR_INV_SRC_COLOR, 68 PIPE_BLENDFACTOR_INV_SRC_ALPHA, 69 PIPE_BLENDFACTOR_INV_DST_ALPHA, 70 PIPE_BLENDFACTOR_INV_DST_COLOR, 71 72 PIPE_BLENDFACTOR_INV_CONST_COLOR = 0x17, 73 PIPE_BLENDFACTOR_INV_CONST_ALPHA, 74 PIPE_BLENDFACTOR_INV_SRC1_COLOR, 75 PIPE_BLENDFACTOR_INV_SRC1_ALPHA, 76 }; 77 78 enum pipe_blend_func { 79 PIPE_BLEND_ADD, 80 PIPE_BLEND_SUBTRACT, 81 PIPE_BLEND_REVERSE_SUBTRACT, 82 PIPE_BLEND_MIN, 83 PIPE_BLEND_MAX, 84 }; 85 86 enum pipe_logicop { 87 PIPE_LOGICOP_CLEAR, 88 PIPE_LOGICOP_NOR, 89 PIPE_LOGICOP_AND_INVERTED, 90 PIPE_LOGICOP_COPY_INVERTED, 91 PIPE_LOGICOP_AND_REVERSE, 92 PIPE_LOGICOP_INVERT, 93 PIPE_LOGICOP_XOR, 94 PIPE_LOGICOP_NAND, 95 PIPE_LOGICOP_AND, 96 PIPE_LOGICOP_EQUIV, 97 PIPE_LOGICOP_NOOP, 98 PIPE_LOGICOP_OR_INVERTED, 99 PIPE_LOGICOP_COPY, 100 PIPE_LOGICOP_OR_REVERSE, 101 PIPE_LOGICOP_OR, 102 PIPE_LOGICOP_SET, 103 }; 104 105 #define PIPE_MASK_R 0x1 106 #define PIPE_MASK_G 0x2 107 #define PIPE_MASK_B 0x4 108 #define PIPE_MASK_A 0x8 109 #define PIPE_MASK_RGBA 0xf 110 #define PIPE_MASK_Z 0x10 111 #define PIPE_MASK_S 0x20 112 #define PIPE_MASK_ZS 0x30 113 #define PIPE_MASK_RGBAZS (PIPE_MASK_RGBA|PIPE_MASK_ZS) 114 115 116 /** 117 * Inequality functions. Used for depth test, stencil compare, alpha 118 * test, shadow compare, etc. 119 */ 120 enum pipe_compare_func { 121 PIPE_FUNC_NEVER, 122 PIPE_FUNC_LESS, 123 PIPE_FUNC_EQUAL, 124 PIPE_FUNC_LEQUAL, 125 PIPE_FUNC_GREATER, 126 PIPE_FUNC_NOTEQUAL, 127 PIPE_FUNC_GEQUAL, 128 PIPE_FUNC_ALWAYS, 129 }; 130 131 /** Polygon fill mode */ 132 enum { 133 PIPE_POLYGON_MODE_FILL, 134 PIPE_POLYGON_MODE_LINE, 135 PIPE_POLYGON_MODE_POINT, 136 PIPE_POLYGON_MODE_FILL_RECTANGLE, 137 }; 138 139 /** Polygon face specification, eg for culling */ 140 #define PIPE_FACE_NONE 0 141 #define PIPE_FACE_FRONT 1 142 #define PIPE_FACE_BACK 2 143 #define PIPE_FACE_FRONT_AND_BACK (PIPE_FACE_FRONT | PIPE_FACE_BACK) 144 145 /** Stencil ops */ 146 enum pipe_stencil_op { 147 PIPE_STENCIL_OP_KEEP, 148 PIPE_STENCIL_OP_ZERO, 149 PIPE_STENCIL_OP_REPLACE, 150 PIPE_STENCIL_OP_INCR, 151 PIPE_STENCIL_OP_DECR, 152 PIPE_STENCIL_OP_INCR_WRAP, 153 PIPE_STENCIL_OP_DECR_WRAP, 154 PIPE_STENCIL_OP_INVERT, 155 }; 156 157 /** Texture types. 158 * See the documentation for info on PIPE_TEXTURE_RECT vs PIPE_TEXTURE_2D 159 */ 160 enum pipe_texture_target 161 { 162 PIPE_BUFFER, 163 PIPE_TEXTURE_1D, 164 PIPE_TEXTURE_2D, 165 PIPE_TEXTURE_3D, 166 PIPE_TEXTURE_CUBE, 167 PIPE_TEXTURE_RECT, 168 PIPE_TEXTURE_1D_ARRAY, 169 PIPE_TEXTURE_2D_ARRAY, 170 PIPE_TEXTURE_CUBE_ARRAY, 171 PIPE_MAX_TEXTURE_TYPES, 172 }; 173 174 enum pipe_tex_face { 175 PIPE_TEX_FACE_POS_X, 176 PIPE_TEX_FACE_NEG_X, 177 PIPE_TEX_FACE_POS_Y, 178 PIPE_TEX_FACE_NEG_Y, 179 PIPE_TEX_FACE_POS_Z, 180 PIPE_TEX_FACE_NEG_Z, 181 PIPE_TEX_FACE_MAX, 182 }; 183 184 enum pipe_tex_wrap { 185 PIPE_TEX_WRAP_REPEAT, 186 PIPE_TEX_WRAP_CLAMP, 187 PIPE_TEX_WRAP_CLAMP_TO_EDGE, 188 PIPE_TEX_WRAP_CLAMP_TO_BORDER, 189 PIPE_TEX_WRAP_MIRROR_REPEAT, 190 PIPE_TEX_WRAP_MIRROR_CLAMP, 191 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE, 192 PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER, 193 }; 194 195 /** Between mipmaps, ie mipfilter */ 196 enum pipe_tex_mipfilter { 197 PIPE_TEX_MIPFILTER_NEAREST, 198 PIPE_TEX_MIPFILTER_LINEAR, 199 PIPE_TEX_MIPFILTER_NONE, 200 }; 201 202 /** Within a mipmap, ie min/mag filter */ 203 enum pipe_tex_filter { 204 PIPE_TEX_FILTER_NEAREST, 205 PIPE_TEX_FILTER_LINEAR, 206 }; 207 208 enum pipe_tex_compare { 209 PIPE_TEX_COMPARE_NONE, 210 PIPE_TEX_COMPARE_R_TO_TEXTURE, 211 }; 212 213 enum pipe_tex_reduction_mode { 214 PIPE_TEX_REDUCTION_WEIGHTED_AVERAGE, 215 PIPE_TEX_REDUCTION_MIN, 216 PIPE_TEX_REDUCTION_MAX, 217 }; 218 219 /** 220 * Clear buffer bits 221 */ 222 #define PIPE_CLEAR_DEPTH (1 << 0) 223 #define PIPE_CLEAR_STENCIL (1 << 1) 224 #define PIPE_CLEAR_COLOR0 (1 << 2) 225 #define PIPE_CLEAR_COLOR1 (1 << 3) 226 #define PIPE_CLEAR_COLOR2 (1 << 4) 227 #define PIPE_CLEAR_COLOR3 (1 << 5) 228 #define PIPE_CLEAR_COLOR4 (1 << 6) 229 #define PIPE_CLEAR_COLOR5 (1 << 7) 230 #define PIPE_CLEAR_COLOR6 (1 << 8) 231 #define PIPE_CLEAR_COLOR7 (1 << 9) 232 /** Combined flags */ 233 /** All color buffers currently bound */ 234 #define PIPE_CLEAR_COLOR (PIPE_CLEAR_COLOR0 | PIPE_CLEAR_COLOR1 | \ 235 PIPE_CLEAR_COLOR2 | PIPE_CLEAR_COLOR3 | \ 236 PIPE_CLEAR_COLOR4 | PIPE_CLEAR_COLOR5 | \ 237 PIPE_CLEAR_COLOR6 | PIPE_CLEAR_COLOR7) 238 #define PIPE_CLEAR_DEPTHSTENCIL (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL) 239 240 /** 241 * CPU access map flags 242 */ 243 enum pipe_map_flags 244 { 245 /** 246 * Resource contents read back (or accessed directly) at transfer 247 * create time. 248 */ 249 PIPE_MAP_READ = 1 << 0, 250 251 /** 252 * Resource contents will be written back at buffer/texture_unmap 253 * time (or modified as a result of being accessed directly). 254 */ 255 PIPE_MAP_WRITE = 1 << 1, 256 257 /** 258 * Read/modify/write 259 */ 260 PIPE_MAP_READ_WRITE = PIPE_MAP_READ | PIPE_MAP_WRITE, 261 262 /** 263 * The transfer should map the texture storage directly. The driver may 264 * return NULL if that isn't possible, and the gallium frontend needs to cope 265 * with that and use an alternative path without this flag. 266 * 267 * E.g. the gallium frontend could have a simpler path which maps textures and 268 * does read/modify/write cycles on them directly, and a more complicated 269 * path which uses minimal read and write transfers. 270 * 271 * This flag supresses implicit "DISCARD" for buffer_subdata. 272 */ 273 PIPE_MAP_DIRECTLY = 1 << 2, 274 275 /** 276 * Discards the memory within the mapped region. 277 * 278 * It should not be used with PIPE_MAP_READ. 279 * 280 * See also: 281 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_RANGE_BIT flag. 282 */ 283 PIPE_MAP_DISCARD_RANGE = 1 << 3, 284 285 /** 286 * Fail if the resource cannot be mapped immediately. 287 * 288 * See also: 289 * - Direct3D's D3DLOCK_DONOTWAIT flag. 290 * - Mesa's MESA_MAP_NOWAIT_BIT flag. 291 * - WDDM's D3DDDICB_LOCKFLAGS.DonotWait flag. 292 */ 293 PIPE_MAP_DONTBLOCK = 1 << 4, 294 295 /** 296 * Do not attempt to synchronize pending operations on the resource when mapping. 297 * 298 * It should not be used with PIPE_MAP_READ. 299 * 300 * See also: 301 * - OpenGL's ARB_map_buffer_range extension, MAP_UNSYNCHRONIZED_BIT flag. 302 * - Direct3D's D3DLOCK_NOOVERWRITE flag. 303 * - WDDM's D3DDDICB_LOCKFLAGS.IgnoreSync flag. 304 */ 305 PIPE_MAP_UNSYNCHRONIZED = 1 << 5, 306 307 /** 308 * Written ranges will be notified later with 309 * pipe_context::transfer_flush_region. 310 * 311 * It should not be used with PIPE_MAP_READ. 312 * 313 * See also: 314 * - pipe_context::transfer_flush_region 315 * - OpenGL's ARB_map_buffer_range extension, MAP_FLUSH_EXPLICIT_BIT flag. 316 */ 317 PIPE_MAP_FLUSH_EXPLICIT = 1 << 6, 318 319 /** 320 * Discards all memory backing the resource. 321 * 322 * It should not be used with PIPE_MAP_READ. 323 * 324 * This is equivalent to: 325 * - OpenGL's ARB_map_buffer_range extension, MAP_INVALIDATE_BUFFER_BIT 326 * - BufferData(NULL) on a GL buffer 327 * - Direct3D's D3DLOCK_DISCARD flag. 328 * - WDDM's D3DDDICB_LOCKFLAGS.Discard flag. 329 * - D3D10 DDI's D3D10_DDI_MAP_WRITE_DISCARD flag 330 * - D3D10's D3D10_MAP_WRITE_DISCARD flag. 331 */ 332 PIPE_MAP_DISCARD_WHOLE_RESOURCE = 1 << 7, 333 334 /** 335 * Allows the resource to be used for rendering while mapped. 336 * 337 * PIPE_RESOURCE_FLAG_MAP_PERSISTENT must be set when creating 338 * the resource. 339 * 340 * If COHERENT is not set, memory_barrier(PIPE_BARRIER_MAPPED_BUFFER) 341 * must be called to ensure the device can see what the CPU has written. 342 */ 343 PIPE_MAP_PERSISTENT = 1 << 8, 344 345 /** 346 * If PERSISTENT is set, this ensures any writes done by the device are 347 * immediately visible to the CPU and vice versa. 348 * 349 * PIPE_RESOURCE_FLAG_MAP_COHERENT must be set when creating 350 * the resource. 351 */ 352 PIPE_MAP_COHERENT = 1 << 9, 353 354 /** 355 * Map a resource in a thread-safe manner, because the calling thread can 356 * be any thread. It can only be used if both WRITE and UNSYNCHRONIZED are 357 * set. 358 */ 359 PIPE_MAP_THREAD_SAFE = 1 << 10, 360 361 /** 362 * Map only the depth aspect of a resource 363 */ 364 PIPE_MAP_DEPTH_ONLY = 1 << 11, 365 366 /** 367 * Map only the stencil aspect of a resource 368 */ 369 PIPE_MAP_STENCIL_ONLY = 1 << 12, 370 371 /** 372 * Mapping will be used only once (never remapped). 373 */ 374 PIPE_MAP_ONCE = 1 << 13, 375 376 /** 377 * This and higher bits are reserved for private use by drivers. Drivers 378 * should use this as (PIPE_MAP_DRV_PRV << i). 379 */ 380 PIPE_MAP_DRV_PRV = 1 << 14, 381 }; 382 383 /** 384 * Flags for the flush function. 385 */ 386 enum pipe_flush_flags 387 { 388 PIPE_FLUSH_END_OF_FRAME = (1 << 0), 389 PIPE_FLUSH_DEFERRED = (1 << 1), 390 PIPE_FLUSH_FENCE_FD = (1 << 2), 391 PIPE_FLUSH_ASYNC = (1 << 3), 392 PIPE_FLUSH_HINT_FINISH = (1 << 4), 393 PIPE_FLUSH_TOP_OF_PIPE = (1 << 5), 394 PIPE_FLUSH_BOTTOM_OF_PIPE = (1 << 6), 395 }; 396 397 /** 398 * Flags for pipe_context::dump_debug_state. 399 */ 400 #define PIPE_DUMP_DEVICE_STATUS_REGISTERS (1 << 0) 401 402 /** 403 * Create a compute-only context. Use in pipe_screen::context_create. 404 * This disables draw, blit, and clear*, render_condition, and other graphics 405 * functions. Interop with other graphics contexts is still allowed. 406 * This allows scheduling jobs on a compute-only hardware command queue that 407 * can run in parallel with graphics without stalling it. 408 */ 409 #define PIPE_CONTEXT_COMPUTE_ONLY (1 << 0) 410 411 /** 412 * Gather debug information and expect that pipe_context::dump_debug_state 413 * will be called. Use in pipe_screen::context_create. 414 */ 415 #define PIPE_CONTEXT_DEBUG (1 << 1) 416 417 /** 418 * Whether out-of-bounds shader loads must return zero and out-of-bounds 419 * shader stores must be dropped. 420 */ 421 #define PIPE_CONTEXT_ROBUST_BUFFER_ACCESS (1 << 2) 422 423 /** 424 * Prefer threaded pipe_context. It also implies that video codec functions 425 * will not be used. (they will be either no-ops or NULL when threading is 426 * enabled) 427 */ 428 #define PIPE_CONTEXT_PREFER_THREADED (1 << 3) 429 430 /** 431 * Create a high priority context. 432 */ 433 #define PIPE_CONTEXT_HIGH_PRIORITY (1 << 4) 434 435 /** 436 * Create a low priority context. 437 */ 438 #define PIPE_CONTEXT_LOW_PRIORITY (1 << 5) 439 440 /** Stop execution if the device is reset. */ 441 #define PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET (1 << 6) 442 443 /** 444 * Flags for pipe_context::memory_barrier. 445 */ 446 #define PIPE_BARRIER_MAPPED_BUFFER (1 << 0) 447 #define PIPE_BARRIER_SHADER_BUFFER (1 << 1) 448 #define PIPE_BARRIER_QUERY_BUFFER (1 << 2) 449 #define PIPE_BARRIER_VERTEX_BUFFER (1 << 3) 450 #define PIPE_BARRIER_INDEX_BUFFER (1 << 4) 451 #define PIPE_BARRIER_CONSTANT_BUFFER (1 << 5) 452 #define PIPE_BARRIER_INDIRECT_BUFFER (1 << 6) 453 #define PIPE_BARRIER_TEXTURE (1 << 7) 454 #define PIPE_BARRIER_IMAGE (1 << 8) 455 #define PIPE_BARRIER_FRAMEBUFFER (1 << 9) 456 #define PIPE_BARRIER_STREAMOUT_BUFFER (1 << 10) 457 #define PIPE_BARRIER_GLOBAL_BUFFER (1 << 11) 458 #define PIPE_BARRIER_UPDATE_BUFFER (1 << 12) 459 #define PIPE_BARRIER_UPDATE_TEXTURE (1 << 13) 460 #define PIPE_BARRIER_ALL ((1 << 14) - 1) 461 462 #define PIPE_BARRIER_UPDATE \ 463 (PIPE_BARRIER_UPDATE_BUFFER | PIPE_BARRIER_UPDATE_TEXTURE) 464 465 /** 466 * Flags for pipe_context::texture_barrier. 467 */ 468 #define PIPE_TEXTURE_BARRIER_SAMPLER (1 << 0) 469 #define PIPE_TEXTURE_BARRIER_FRAMEBUFFER (1 << 1) 470 471 /** 472 * Resource binding flags -- gallium frontends must specify in advance all 473 * the ways a resource might be used. 474 */ 475 #define PIPE_BIND_DEPTH_STENCIL (1 << 0) /* create_surface */ 476 #define PIPE_BIND_RENDER_TARGET (1 << 1) /* create_surface */ 477 #define PIPE_BIND_BLENDABLE (1 << 2) /* create_surface */ 478 #define PIPE_BIND_SAMPLER_VIEW (1 << 3) /* create_sampler_view */ 479 #define PIPE_BIND_VERTEX_BUFFER (1 << 4) /* set_vertex_buffers */ 480 #define PIPE_BIND_INDEX_BUFFER (1 << 5) /* draw_elements */ 481 #define PIPE_BIND_CONSTANT_BUFFER (1 << 6) /* set_constant_buffer */ 482 #define PIPE_BIND_DISPLAY_TARGET (1 << 7) /* flush_front_buffer */ 483 #define PIPE_BIND_VERTEX_STATE (1 << 8) /* create_vertex_state */ 484 /* gap */ 485 #define PIPE_BIND_STREAM_OUTPUT (1 << 10) /* set_stream_output_buffers */ 486 #define PIPE_BIND_CURSOR (1 << 11) /* mouse cursor */ 487 #define PIPE_BIND_CUSTOM (1 << 12) /* gallium frontend/winsys usages */ 488 #define PIPE_BIND_GLOBAL (1 << 13) /* set_global_binding */ 489 #define PIPE_BIND_SHADER_BUFFER (1 << 14) /* set_shader_buffers */ 490 #define PIPE_BIND_SHADER_IMAGE (1 << 15) /* set_shader_images */ 491 #define PIPE_BIND_COMPUTE_RESOURCE (1 << 16) /* set_compute_resources */ 492 #define PIPE_BIND_COMMAND_ARGS_BUFFER (1 << 17) /* pipe_draw_info.indirect */ 493 #define PIPE_BIND_QUERY_BUFFER (1 << 18) /* get_query_result_resource */ 494 495 /** 496 * The first two flags above were previously part of the amorphous 497 * TEXTURE_USAGE, most of which are now descriptions of the ways a 498 * particular texture can be bound to the gallium pipeline. The two flags 499 * below do not fit within that and probably need to be migrated to some 500 * other place. 501 * 502 * Scanout is used to ask for a texture suitable for actual scanout (hence 503 * the name), which implies extra layout constraints on some hardware. 504 * It may also have some special meaning regarding mouse cursor images. 505 * 506 * The shared flag is quite underspecified, but certainly isn't a 507 * binding flag - it seems more like a message to the winsys to create 508 * a shareable allocation. 509 * 510 * The third flag has been added to be able to force textures to be created 511 * in linear mode (no tiling). 512 */ 513 #define PIPE_BIND_SCANOUT (1 << 19) /* */ 514 #define PIPE_BIND_SHARED (1 << 20) /* get_texture_handle ??? */ 515 #define PIPE_BIND_LINEAR (1 << 21) 516 #define PIPE_BIND_PROTECTED (1 << 22) /* Resource will be protected/encrypted */ 517 #define PIPE_BIND_SAMPLER_REDUCTION_MINMAX (1 << 23) /* PIPE_CAP_SAMPLER_REDUCTION_MINMAX */ 518 /* Resource is the DRI_PRIME blit destination. Only set on on the render GPU. */ 519 #define PIPE_BIND_PRIME_BLIT_DST (1 << 24) 520 521 522 /** 523 * Flags for the driver about resource behaviour: 524 */ 525 #define PIPE_RESOURCE_FLAG_MAP_PERSISTENT (1 << 0) 526 #define PIPE_RESOURCE_FLAG_MAP_COHERENT (1 << 1) 527 #define PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY (1 << 2) 528 #define PIPE_RESOURCE_FLAG_SPARSE (1 << 3) 529 #define PIPE_RESOURCE_FLAG_SINGLE_THREAD_USE (1 << 4) 530 #define PIPE_RESOURCE_FLAG_ENCRYPTED (1 << 5) 531 #define PIPE_RESOURCE_FLAG_DONT_OVER_ALLOCATE (1 << 6) 532 #define PIPE_RESOURCE_FLAG_DONT_MAP_DIRECTLY (1 << 7) /* for small visible VRAM */ 533 #define PIPE_RESOURCE_FLAG_UNMAPPABLE (1 << 8) /* implies staging transfers due to VK interop */ 534 #define PIPE_RESOURCE_FLAG_DRV_PRIV (1 << 9) /* driver/winsys private */ 535 #define PIPE_RESOURCE_FLAG_FRONTEND_PRIV (1 << 24) /* gallium frontend private */ 536 537 /** 538 * Hint about the expected lifecycle of a resource. 539 * Sorted according to GPU vs CPU access. 540 */ 541 enum pipe_resource_usage { 542 PIPE_USAGE_DEFAULT, /* fast GPU access */ 543 PIPE_USAGE_IMMUTABLE, /* fast GPU access, immutable */ 544 PIPE_USAGE_DYNAMIC, /* uploaded data is used multiple times */ 545 PIPE_USAGE_STREAM, /* uploaded data is used once */ 546 PIPE_USAGE_STAGING, /* fast CPU access */ 547 }; 548 549 /** 550 * Shaders 551 */ 552 enum pipe_shader_type { 553 PIPE_SHADER_VERTEX, 554 PIPE_SHADER_FRAGMENT, 555 PIPE_SHADER_GEOMETRY, 556 PIPE_SHADER_TESS_CTRL, 557 PIPE_SHADER_TESS_EVAL, 558 PIPE_SHADER_COMPUTE, 559 PIPE_SHADER_TYPES, 560 }; 561 562 /** 563 * Primitive types: 564 */ 565 enum pipe_prim_type { 566 PIPE_PRIM_POINTS, 567 PIPE_PRIM_LINES, 568 PIPE_PRIM_LINE_LOOP, 569 PIPE_PRIM_LINE_STRIP, 570 PIPE_PRIM_TRIANGLES, 571 PIPE_PRIM_TRIANGLE_STRIP, 572 PIPE_PRIM_TRIANGLE_FAN, 573 PIPE_PRIM_QUADS, 574 PIPE_PRIM_QUAD_STRIP, 575 PIPE_PRIM_POLYGON, 576 PIPE_PRIM_LINES_ADJACENCY, 577 PIPE_PRIM_LINE_STRIP_ADJACENCY, 578 PIPE_PRIM_TRIANGLES_ADJACENCY, 579 PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY, 580 PIPE_PRIM_PATCHES, 581 PIPE_PRIM_MAX, 582 } ENUM_PACKED; 583 584 /** 585 * Tessellator spacing types 586 */ 587 enum pipe_tess_spacing { 588 PIPE_TESS_SPACING_FRACTIONAL_ODD, 589 PIPE_TESS_SPACING_FRACTIONAL_EVEN, 590 PIPE_TESS_SPACING_EQUAL, 591 }; 592 593 /** 594 * Query object types 595 */ 596 enum pipe_query_type { 597 PIPE_QUERY_OCCLUSION_COUNTER, 598 PIPE_QUERY_OCCLUSION_PREDICATE, 599 PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE, 600 PIPE_QUERY_TIMESTAMP, 601 PIPE_QUERY_TIMESTAMP_DISJOINT, 602 PIPE_QUERY_TIME_ELAPSED, 603 PIPE_QUERY_PRIMITIVES_GENERATED, 604 PIPE_QUERY_PRIMITIVES_EMITTED, 605 PIPE_QUERY_SO_STATISTICS, 606 PIPE_QUERY_SO_OVERFLOW_PREDICATE, 607 PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE, 608 PIPE_QUERY_GPU_FINISHED, 609 PIPE_QUERY_PIPELINE_STATISTICS, 610 PIPE_QUERY_PIPELINE_STATISTICS_SINGLE, 611 PIPE_QUERY_TYPES, 612 /* start of driver queries, see pipe_screen::get_driver_query_info */ 613 PIPE_QUERY_DRIVER_SPECIFIC = 256, 614 }; 615 616 /** 617 * Index for PIPE_QUERY_PIPELINE_STATISTICS subqueries. 618 */ 619 enum pipe_statistics_query_index { 620 PIPE_STAT_QUERY_IA_VERTICES, 621 PIPE_STAT_QUERY_IA_PRIMITIVES, 622 PIPE_STAT_QUERY_VS_INVOCATIONS, 623 PIPE_STAT_QUERY_GS_INVOCATIONS, 624 PIPE_STAT_QUERY_GS_PRIMITIVES, 625 PIPE_STAT_QUERY_C_INVOCATIONS, 626 PIPE_STAT_QUERY_C_PRIMITIVES, 627 PIPE_STAT_QUERY_PS_INVOCATIONS, 628 PIPE_STAT_QUERY_HS_INVOCATIONS, 629 PIPE_STAT_QUERY_DS_INVOCATIONS, 630 PIPE_STAT_QUERY_CS_INVOCATIONS, 631 }; 632 633 /** 634 * Conditional rendering modes 635 */ 636 enum pipe_render_cond_flag { 637 PIPE_RENDER_COND_WAIT, 638 PIPE_RENDER_COND_NO_WAIT, 639 PIPE_RENDER_COND_BY_REGION_WAIT, 640 PIPE_RENDER_COND_BY_REGION_NO_WAIT, 641 }; 642 643 /** 644 * Point sprite coord modes 645 */ 646 enum pipe_sprite_coord_mode { 647 PIPE_SPRITE_COORD_UPPER_LEFT, 648 PIPE_SPRITE_COORD_LOWER_LEFT, 649 }; 650 651 /** 652 * Texture & format swizzles 653 */ 654 enum pipe_swizzle { 655 PIPE_SWIZZLE_X, 656 PIPE_SWIZZLE_Y, 657 PIPE_SWIZZLE_Z, 658 PIPE_SWIZZLE_W, 659 PIPE_SWIZZLE_0, 660 PIPE_SWIZZLE_1, 661 PIPE_SWIZZLE_NONE, 662 PIPE_SWIZZLE_MAX, /**< Number of enums counter (must be last) */ 663 }; 664 665 /** 666 * Viewport swizzles 667 */ 668 enum pipe_viewport_swizzle { 669 PIPE_VIEWPORT_SWIZZLE_POSITIVE_X, 670 PIPE_VIEWPORT_SWIZZLE_NEGATIVE_X, 671 PIPE_VIEWPORT_SWIZZLE_POSITIVE_Y, 672 PIPE_VIEWPORT_SWIZZLE_NEGATIVE_Y, 673 PIPE_VIEWPORT_SWIZZLE_POSITIVE_Z, 674 PIPE_VIEWPORT_SWIZZLE_NEGATIVE_Z, 675 PIPE_VIEWPORT_SWIZZLE_POSITIVE_W, 676 PIPE_VIEWPORT_SWIZZLE_NEGATIVE_W, 677 }; 678 679 #define PIPE_TIMEOUT_INFINITE 0xffffffffffffffffull 680 681 682 /** 683 * Device reset status. 684 */ 685 enum pipe_reset_status 686 { 687 PIPE_NO_RESET, 688 PIPE_GUILTY_CONTEXT_RESET, 689 PIPE_INNOCENT_CONTEXT_RESET, 690 PIPE_UNKNOWN_CONTEXT_RESET, 691 }; 692 693 694 /** 695 * Conservative rasterization modes. 696 */ 697 enum pipe_conservative_raster_mode 698 { 699 PIPE_CONSERVATIVE_RASTER_OFF, 700 701 /** 702 * The post-snap mode means the conservative rasterization occurs after 703 * the conversion from floating-point to fixed-point coordinates 704 * on the subpixel grid. 705 */ 706 PIPE_CONSERVATIVE_RASTER_POST_SNAP, 707 708 /** 709 * The pre-snap mode means the conservative rasterization occurs before 710 * the conversion from floating-point to fixed-point coordinates. 711 */ 712 PIPE_CONSERVATIVE_RASTER_PRE_SNAP, 713 }; 714 715 716 /** 717 * resource_get_handle flags. 718 */ 719 /* Requires pipe_context::flush_resource before external use. */ 720 #define PIPE_HANDLE_USAGE_EXPLICIT_FLUSH (1 << 0) 721 /* Expected external use of the resource: */ 722 #define PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE (1 << 1) 723 #define PIPE_HANDLE_USAGE_SHADER_WRITE (1 << 2) 724 725 /** 726 * pipe_image_view access flags. 727 */ 728 #define PIPE_IMAGE_ACCESS_READ (1 << 0) 729 #define PIPE_IMAGE_ACCESS_WRITE (1 << 1) 730 #define PIPE_IMAGE_ACCESS_READ_WRITE (PIPE_IMAGE_ACCESS_READ | \ 731 PIPE_IMAGE_ACCESS_WRITE) 732 733 /** 734 * Implementation capabilities/limits which are queried through 735 * pipe_screen::get_param() 736 */ 737 enum pipe_cap 738 { 739 PIPE_CAP_GRAPHICS, 740 PIPE_CAP_NPOT_TEXTURES, 741 PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS, 742 PIPE_CAP_ANISOTROPIC_FILTER, 743 PIPE_CAP_POINT_SPRITE, 744 PIPE_CAP_MAX_RENDER_TARGETS, 745 PIPE_CAP_OCCLUSION_QUERY, 746 PIPE_CAP_QUERY_TIME_ELAPSED, 747 PIPE_CAP_TEXTURE_SHADOW_MAP, 748 PIPE_CAP_TEXTURE_SWIZZLE, 749 PIPE_CAP_MAX_TEXTURE_2D_SIZE, 750 PIPE_CAP_MAX_TEXTURE_3D_LEVELS, 751 PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS, 752 PIPE_CAP_TEXTURE_MIRROR_CLAMP, 753 PIPE_CAP_BLEND_EQUATION_SEPARATE, 754 PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS, 755 PIPE_CAP_PRIMITIVE_RESTART, 756 /** subset of PRIMITIVE_RESTART where the restart index is always the fixed 757 * maximum value for the index type 758 */ 759 PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX, 760 /** blend enables and write masks per rendertarget */ 761 PIPE_CAP_INDEP_BLEND_ENABLE, 762 /** different blend funcs per rendertarget */ 763 PIPE_CAP_INDEP_BLEND_FUNC, 764 PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS, 765 PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT, 766 PIPE_CAP_FS_COORD_ORIGIN_LOWER_LEFT, 767 PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER, 768 PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER, 769 PIPE_CAP_POINT_COORD_ORIGIN_UPPER_LEFT, 770 PIPE_CAP_DEPTH_CLIP_DISABLE, 771 PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE, 772 PIPE_CAP_DEPTH_CLAMP_ENABLE, 773 PIPE_CAP_SHADER_STENCIL_EXPORT, 774 PIPE_CAP_VS_INSTANCEID, 775 PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR, 776 PIPE_CAP_FRAGMENT_COLOR_CLAMPED, 777 PIPE_CAP_MIXED_COLORBUFFER_FORMATS, 778 PIPE_CAP_SEAMLESS_CUBE_MAP, 779 PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE, 780 PIPE_CAP_MIN_TEXEL_OFFSET, 781 PIPE_CAP_MAX_TEXEL_OFFSET, 782 PIPE_CAP_CONDITIONAL_RENDER, 783 PIPE_CAP_TEXTURE_BARRIER, 784 PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS, 785 PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS, 786 PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME, 787 PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS, 788 PIPE_CAP_VERTEX_COLOR_UNCLAMPED, 789 PIPE_CAP_VERTEX_COLOR_CLAMPED, 790 PIPE_CAP_GLSL_FEATURE_LEVEL, 791 PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY, 792 PIPE_CAP_ESSL_FEATURE_LEVEL, 793 PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION, 794 PIPE_CAP_USER_VERTEX_BUFFERS, 795 PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY, 796 PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY, 797 PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY, 798 PIPE_CAP_VERTEX_ATTRIB_ELEMENT_ALIGNED_ONLY, 799 PIPE_CAP_COMPUTE, 800 PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT, 801 PIPE_CAP_START_INSTANCE, 802 PIPE_CAP_QUERY_TIMESTAMP, 803 PIPE_CAP_TEXTURE_MULTISAMPLE, 804 PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT, 805 PIPE_CAP_CUBE_MAP_ARRAY, 806 PIPE_CAP_TEXTURE_BUFFER_OBJECTS, 807 PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT, 808 PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY, 809 PIPE_CAP_TGSI_TEXCOORD, 810 PIPE_CAP_TEXTURE_BUFFER_SAMPLER, 811 PIPE_CAP_TEXTURE_TRANSFER_MODES, 812 PIPE_CAP_QUERY_PIPELINE_STATISTICS, 813 PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK, 814 PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT, 815 PIPE_CAP_MAX_VIEWPORTS, 816 PIPE_CAP_ENDIANNESS, 817 PIPE_CAP_MIXED_FRAMEBUFFER_SIZES, 818 PIPE_CAP_VS_LAYER_VIEWPORT, 819 PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES, 820 PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS, 821 PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS, 822 PIPE_CAP_TEXTURE_GATHER_SM5, 823 PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT, 824 PIPE_CAP_FAKE_SW_MSAA, 825 PIPE_CAP_TEXTURE_QUERY_LOD, 826 PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET, 827 PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET, 828 PIPE_CAP_SAMPLE_SHADING, 829 PIPE_CAP_TEXTURE_GATHER_OFFSETS, 830 PIPE_CAP_VS_WINDOW_SPACE_POSITION, 831 PIPE_CAP_MAX_VERTEX_STREAMS, 832 PIPE_CAP_DRAW_INDIRECT, 833 PIPE_CAP_FS_FINE_DERIVATIVE, 834 PIPE_CAP_VENDOR_ID, 835 PIPE_CAP_DEVICE_ID, 836 PIPE_CAP_ACCELERATED, 837 PIPE_CAP_VIDEO_MEMORY, 838 PIPE_CAP_UMA, 839 PIPE_CAP_CONDITIONAL_RENDER_INVERTED, 840 PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE, 841 PIPE_CAP_SAMPLER_VIEW_TARGET, 842 PIPE_CAP_CLIP_HALFZ, 843 PIPE_CAP_VERTEXID_NOBASE, 844 PIPE_CAP_POLYGON_OFFSET_CLAMP, 845 PIPE_CAP_MULTISAMPLE_Z_RESOLVE, 846 PIPE_CAP_RESOURCE_FROM_USER_MEMORY, 847 PIPE_CAP_RESOURCE_FROM_USER_MEMORY_COMPUTE_ONLY, 848 PIPE_CAP_DEVICE_RESET_STATUS_QUERY, 849 PIPE_CAP_MAX_SHADER_PATCH_VARYINGS, 850 PIPE_CAP_TEXTURE_FLOAT_LINEAR, 851 PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR, 852 PIPE_CAP_DEPTH_BOUNDS_TEST, 853 PIPE_CAP_TEXTURE_QUERY_SAMPLES, 854 PIPE_CAP_FORCE_PERSAMPLE_INTERP, 855 PIPE_CAP_SHAREABLE_SHADERS, 856 PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS, 857 PIPE_CAP_CLEAR_TEXTURE, 858 PIPE_CAP_CLEAR_SCISSORED, 859 PIPE_CAP_DRAW_PARAMETERS, 860 PIPE_CAP_SHADER_PACK_HALF_FLOAT, 861 PIPE_CAP_MULTI_DRAW_INDIRECT, 862 PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS, 863 PIPE_CAP_MULTI_DRAW_INDIRECT_PARTIAL_STRIDE, 864 PIPE_CAP_FS_POSITION_IS_SYSVAL, 865 PIPE_CAP_FS_POINT_IS_SYSVAL, 866 PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL, 867 PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT, 868 PIPE_CAP_INVALIDATE_BUFFER, 869 PIPE_CAP_GENERATE_MIPMAP, 870 PIPE_CAP_STRING_MARKER, 871 PIPE_CAP_SURFACE_REINTERPRET_BLOCKS, 872 PIPE_CAP_QUERY_BUFFER_OBJECT, 873 PIPE_CAP_QUERY_MEMORY_INFO, 874 PIPE_CAP_PCI_GROUP, 875 PIPE_CAP_PCI_BUS, 876 PIPE_CAP_PCI_DEVICE, 877 PIPE_CAP_PCI_FUNCTION, 878 PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT, 879 PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR, 880 PIPE_CAP_CULL_DISTANCE, 881 PIPE_CAP_CULL_DISTANCE_NOCOMBINE, 882 PIPE_CAP_SHADER_GROUP_VOTE, 883 PIPE_CAP_MAX_WINDOW_RECTANGLES, 884 PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED, 885 PIPE_CAP_VIEWPORT_SUBPIXEL_BITS, 886 PIPE_CAP_RASTERIZER_SUBPIXEL_BITS, 887 PIPE_CAP_MIXED_COLOR_DEPTH_BITS, 888 PIPE_CAP_SHADER_ARRAY_COMPONENTS, 889 PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS, 890 PIPE_CAP_SHADER_CAN_READ_OUTPUTS, 891 PIPE_CAP_NATIVE_FENCE_FD, 892 PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS, 893 PIPE_CAP_FBFETCH, 894 PIPE_CAP_LEGACY_MATH_RULES, 895 PIPE_CAP_DOUBLES, 896 PIPE_CAP_INT64, 897 PIPE_CAP_INT64_DIVMOD, 898 PIPE_CAP_TGSI_TEX_TXF_LZ, 899 PIPE_CAP_SHADER_CLOCK, 900 PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE, 901 PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE, 902 PIPE_CAP_SHADER_BALLOT, 903 PIPE_CAP_TES_LAYER_VIEWPORT, 904 PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX, 905 PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION, 906 PIPE_CAP_POST_DEPTH_COVERAGE, 907 PIPE_CAP_BINDLESS_TEXTURE, 908 PIPE_CAP_NIR_SAMPLERS_AS_DEREF, 909 PIPE_CAP_QUERY_SO_OVERFLOW, 910 PIPE_CAP_MEMOBJ, 911 PIPE_CAP_LOAD_CONSTBUF, 912 PIPE_CAP_TILE_RASTER_ORDER, 913 PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES, 914 PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS, 915 PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET, 916 PIPE_CAP_CONTEXT_PRIORITY_MASK, 917 PIPE_CAP_FENCE_SIGNAL, 918 PIPE_CAP_CONSTBUF0_FLAGS, 919 PIPE_CAP_PACKED_UNIFORMS, 920 PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES, 921 PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES, 922 PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES, 923 PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES, 924 PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS, 925 PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE, 926 PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE, 927 PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS, 928 PIPE_CAP_MAX_GS_INVOCATIONS, 929 PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT, 930 PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE, 931 PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS, 932 PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS, 933 PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS, 934 PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET, 935 PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET, 936 PIPE_CAP_SURFACE_SAMPLE_COUNT, 937 PIPE_CAP_IMAGE_ATOMIC_FLOAT_ADD, 938 PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE, 939 PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND, 940 PIPE_CAP_DEST_SURFACE_SRGB_CONTROL, 941 PIPE_CAP_NIR_COMPACT_ARRAYS, 942 PIPE_CAP_MAX_VARYINGS, 943 PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK, 944 PIPE_CAP_COMPUTE_SHADER_DERIVATIVES, 945 PIPE_CAP_IMAGE_LOAD_FORMATTED, 946 PIPE_CAP_IMAGE_STORE_FORMATTED, 947 PIPE_CAP_THROTTLE, 948 PIPE_CAP_DMABUF, 949 PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA, 950 PIPE_CAP_FRAGMENT_SHADER_INTERLOCK, 951 PIPE_CAP_FBFETCH_COHERENT, 952 PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED, 953 PIPE_CAP_ATOMIC_FLOAT_MINMAX, 954 PIPE_CAP_TGSI_DIV, 955 PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD, 956 PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES, 957 PIPE_CAP_TEXTURE_SHADOW_LOD, 958 PIPE_CAP_SHADER_SAMPLES_IDENTICAL, 959 PIPE_CAP_IMAGE_ATOMIC_INC_WRAP, 960 PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF, 961 PIPE_CAP_GL_SPIRV, 962 PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS, 963 PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION, 964 PIPE_CAP_TGSI_TG4_COMPONENT_IN_SWIZZLE, 965 PIPE_CAP_FLATSHADE, 966 PIPE_CAP_ALPHA_TEST, 967 PIPE_CAP_POINT_SIZE_FIXED, 968 PIPE_CAP_TWO_SIDED_COLOR, 969 PIPE_CAP_CLIP_PLANES, 970 PIPE_CAP_MAX_VERTEX_BUFFERS, 971 PIPE_CAP_OPENCL_INTEGER_FUNCTIONS, 972 PIPE_CAP_INTEGER_MULTIPLY_32X16, 973 /* Turn draw, dispatch, blit into NOOP */ 974 PIPE_CAP_FRONTEND_NOOP, 975 PIPE_CAP_NIR_IMAGES_AS_DEREF, 976 PIPE_CAP_PACKED_STREAM_OUTPUT, 977 PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED, 978 PIPE_CAP_PSIZ_CLAMPED, 979 PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE, 980 PIPE_CAP_VIEWPORT_SWIZZLE, 981 PIPE_CAP_SYSTEM_SVM, 982 PIPE_CAP_VIEWPORT_MASK, 983 PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL, 984 PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE, 985 PIPE_CAP_GLSL_ZERO_INIT, 986 PIPE_CAP_BLEND_EQUATION_ADVANCED, 987 PIPE_CAP_NIR_ATOMICS_AS_DEREF, 988 PIPE_CAP_NO_CLIP_ON_COPY_TEX, 989 PIPE_CAP_MAX_TEXTURE_MB, 990 PIPE_CAP_SHADER_ATOMIC_INT64, 991 PIPE_CAP_DEVICE_PROTECTED_CONTENT, 992 PIPE_CAP_PREFER_REAL_BUFFER_IN_CONSTBUF0, 993 PIPE_CAP_GL_CLAMP, 994 PIPE_CAP_TEXRECT, 995 PIPE_CAP_SAMPLER_REDUCTION_MINMAX, 996 PIPE_CAP_SAMPLER_REDUCTION_MINMAX_ARB, 997 PIPE_CAP_ALLOW_DYNAMIC_VAO_FASTPATH, 998 PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART, 999 PIPE_CAP_SUPPORTED_PRIM_MODES, 1000 PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART, 1001 PIPE_CAP_PREFER_BACK_BUFFER_REUSE, 1002 PIPE_CAP_DRAW_VERTEX_STATE, 1003 PIPE_CAP_PREFER_POT_ALIGNED_VARYINGS, 1004 PIPE_CAP_MAX_SPARSE_TEXTURE_SIZE, 1005 PIPE_CAP_MAX_SPARSE_3D_TEXTURE_SIZE, 1006 PIPE_CAP_MAX_SPARSE_ARRAY_TEXTURE_LAYERS, 1007 PIPE_CAP_SPARSE_TEXTURE_FULL_ARRAY_CUBE_MIPMAPS, 1008 PIPE_CAP_QUERY_SPARSE_TEXTURE_RESIDENCY, 1009 PIPE_CAP_CLAMP_SPARSE_TEXTURE_LOD, 1010 PIPE_CAP_ALLOW_DRAW_OUT_OF_ORDER, 1011 PIPE_CAP_MAX_CONSTANT_BUFFER_SIZE_UINT, 1012 PIPE_CAP_HARDWARE_GL_SELECT, 1013 PIPE_CAP_DITHERING, 1014 PIPE_CAP_FBFETCH_ZS, 1015 PIPE_CAP_TIMELINE_SEMAPHORE_IMPORT, 1016 1017 PIPE_CAP_LAST, 1018 /* XXX do not add caps after PIPE_CAP_LAST! */ 1019 }; 1020 1021 enum pipe_texture_transfer_mode { 1022 PIPE_TEXTURE_TRANSFER_DEFAULT = 0, 1023 PIPE_TEXTURE_TRANSFER_BLIT = (1 << 0), 1024 PIPE_TEXTURE_TRANSFER_COMPUTE = (1 << 1), 1025 }; 1026 1027 /** 1028 * Possible bits for PIPE_CAP_CONTEXT_PRIORITY_MASK param, which should 1029 * return a bitmask of the supported priorities. If the driver does not 1030 * support prioritized contexts, it can return 0. 1031 * 1032 * Note that these match __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_* 1033 */ 1034 #define PIPE_CONTEXT_PRIORITY_LOW (1 << 0) 1035 #define PIPE_CONTEXT_PRIORITY_MEDIUM (1 << 1) 1036 #define PIPE_CONTEXT_PRIORITY_HIGH (1 << 2) 1037 1038 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50 (1 << 0) 1039 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 (1 << 1) 1040 #define PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_FREEDRENO (1 << 2) 1041 1042 enum pipe_endian 1043 { 1044 PIPE_ENDIAN_LITTLE = 0, 1045 PIPE_ENDIAN_BIG = 1, 1046 #if UTIL_ARCH_LITTLE_ENDIAN 1047 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_LITTLE 1048 #elif UTIL_ARCH_BIG_ENDIAN 1049 PIPE_ENDIAN_NATIVE = PIPE_ENDIAN_BIG 1050 #endif 1051 }; 1052 1053 /** 1054 * Implementation limits which are queried through 1055 * pipe_screen::get_paramf() 1056 */ 1057 enum pipe_capf 1058 { 1059 PIPE_CAPF_MIN_LINE_WIDTH, 1060 PIPE_CAPF_MIN_LINE_WIDTH_AA, 1061 PIPE_CAPF_MAX_LINE_WIDTH, 1062 PIPE_CAPF_MAX_LINE_WIDTH_AA, 1063 PIPE_CAPF_LINE_WIDTH_GRANULARITY, 1064 PIPE_CAPF_MIN_POINT_SIZE, 1065 PIPE_CAPF_MIN_POINT_SIZE_AA, 1066 PIPE_CAPF_MAX_POINT_SIZE, 1067 PIPE_CAPF_MAX_POINT_SIZE_AA, 1068 PIPE_CAPF_POINT_SIZE_GRANULARITY, 1069 PIPE_CAPF_MAX_TEXTURE_ANISOTROPY, 1070 PIPE_CAPF_MAX_TEXTURE_LOD_BIAS, 1071 PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE, 1072 PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE, 1073 PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY, 1074 }; 1075 1076 /** Shader caps not specific to any single stage */ 1077 enum pipe_shader_cap 1078 { 1079 PIPE_SHADER_CAP_MAX_INSTRUCTIONS, /* if 0, it means the stage is unsupported */ 1080 PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS, 1081 PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS, 1082 PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS, 1083 PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH, 1084 PIPE_SHADER_CAP_MAX_INPUTS, 1085 PIPE_SHADER_CAP_MAX_OUTPUTS, 1086 PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE, 1087 PIPE_SHADER_CAP_MAX_CONST_BUFFERS, 1088 PIPE_SHADER_CAP_MAX_TEMPS, 1089 /* boolean caps */ 1090 PIPE_SHADER_CAP_CONT_SUPPORTED, 1091 PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR, 1092 PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR, 1093 PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR, 1094 PIPE_SHADER_CAP_INDIRECT_CONST_ADDR, 1095 PIPE_SHADER_CAP_SUBROUTINES, /* BGNSUB, ENDSUB, CAL, RET */ 1096 PIPE_SHADER_CAP_INTEGERS, 1097 PIPE_SHADER_CAP_INT64_ATOMICS, 1098 PIPE_SHADER_CAP_FP16, 1099 PIPE_SHADER_CAP_FP16_DERIVATIVES, 1100 PIPE_SHADER_CAP_FP16_CONST_BUFFERS, 1101 PIPE_SHADER_CAP_INT16, 1102 PIPE_SHADER_CAP_GLSL_16BIT_CONSTS, 1103 PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS, 1104 PIPE_SHADER_CAP_PREFERRED_IR, 1105 PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED, 1106 PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS, 1107 PIPE_SHADER_CAP_DROUND_SUPPORTED, /* all rounding modes */ 1108 PIPE_SHADER_CAP_DFRACEXP_DLDEXP_SUPPORTED, 1109 PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE, 1110 PIPE_SHADER_CAP_MAX_SHADER_BUFFERS, 1111 PIPE_SHADER_CAP_SUPPORTED_IRS, 1112 PIPE_SHADER_CAP_MAX_SHADER_IMAGES, 1113 PIPE_SHADER_CAP_LDEXP_SUPPORTED, 1114 PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS, 1115 PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS, 1116 }; 1117 1118 /** 1119 * Shader intermediate representation. 1120 * 1121 * Note that if the driver requests something other than TGSI, it must 1122 * always be prepared to receive TGSI in addition to its preferred IR. 1123 * If the driver requests TGSI as its preferred IR, it will *always* 1124 * get TGSI. 1125 * 1126 * Note that PIPE_SHADER_IR_TGSI should be zero for backwards compat with 1127 * gallium frontends that only understand TGSI. 1128 */ 1129 enum pipe_shader_ir 1130 { 1131 PIPE_SHADER_IR_TGSI = 0, 1132 PIPE_SHADER_IR_NATIVE, 1133 PIPE_SHADER_IR_NIR, 1134 PIPE_SHADER_IR_NIR_SERIALIZED, 1135 }; 1136 1137 /** 1138 * Compute-specific implementation capability. They can be queried 1139 * using pipe_screen::get_compute_param. 1140 */ 1141 enum pipe_compute_cap 1142 { 1143 PIPE_COMPUTE_CAP_ADDRESS_BITS, 1144 PIPE_COMPUTE_CAP_IR_TARGET, 1145 PIPE_COMPUTE_CAP_GRID_DIMENSION, 1146 PIPE_COMPUTE_CAP_MAX_GRID_SIZE, 1147 PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE, 1148 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK, 1149 PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE, 1150 PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE, 1151 PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE, 1152 PIPE_COMPUTE_CAP_MAX_INPUT_SIZE, 1153 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE, 1154 PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY, 1155 PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS, 1156 PIPE_COMPUTE_CAP_IMAGES_SUPPORTED, 1157 PIPE_COMPUTE_CAP_SUBGROUP_SIZE, 1158 PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK, 1159 }; 1160 1161 /** 1162 * Resource parameters. They can be queried using 1163 * pipe_screen::get_resource_param. 1164 */ 1165 enum pipe_resource_param 1166 { 1167 PIPE_RESOURCE_PARAM_NPLANES, 1168 PIPE_RESOURCE_PARAM_STRIDE, 1169 PIPE_RESOURCE_PARAM_OFFSET, 1170 PIPE_RESOURCE_PARAM_MODIFIER, 1171 PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED, 1172 PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS, 1173 PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD, 1174 PIPE_RESOURCE_PARAM_LAYER_STRIDE, 1175 }; 1176 1177 /** 1178 * Types of parameters for pipe_context::set_context_param. 1179 */ 1180 enum pipe_context_param 1181 { 1182 /* A hint for the driver that it should pin its execution threads to 1183 * a group of cores sharing a specific L3 cache if the CPU has multiple 1184 * L3 caches. This is needed for good multithreading performance on 1185 * AMD Zen CPUs. "value" is the L3 cache index. Drivers that don't have 1186 * any internal threads or don't run on affected CPUs can ignore this. 1187 */ 1188 PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE, 1189 }; 1190 1191 /** 1192 * Composite query types 1193 */ 1194 1195 /** 1196 * Query result for PIPE_QUERY_SO_STATISTICS. 1197 */ 1198 struct pipe_query_data_so_statistics 1199 { 1200 uint64_t num_primitives_written; 1201 uint64_t primitives_storage_needed; 1202 }; 1203 1204 /** 1205 * Query result for PIPE_QUERY_TIMESTAMP_DISJOINT. 1206 */ 1207 struct pipe_query_data_timestamp_disjoint 1208 { 1209 uint64_t frequency; 1210 bool disjoint; 1211 }; 1212 1213 /** 1214 * Query result for PIPE_QUERY_PIPELINE_STATISTICS. 1215 */ 1216 struct pipe_query_data_pipeline_statistics 1217 { 1218 union { 1219 struct { 1220 uint64_t ia_vertices; /**< Num vertices read by the vertex fetcher. */ 1221 uint64_t ia_primitives; /**< Num primitives read by the vertex fetcher. */ 1222 uint64_t vs_invocations; /**< Num vertex shader invocations. */ 1223 uint64_t gs_invocations; /**< Num geometry shader invocations. */ 1224 uint64_t gs_primitives; /**< Num primitives output by a geometry shader. */ 1225 uint64_t c_invocations; /**< Num primitives sent to the rasterizer. */ 1226 uint64_t c_primitives; /**< Num primitives that were rendered. */ 1227 uint64_t ps_invocations; /**< Num pixel shader invocations. */ 1228 uint64_t hs_invocations; /**< Num hull shader invocations. */ 1229 uint64_t ds_invocations; /**< Num domain shader invocations. */ 1230 uint64_t cs_invocations; /**< Num compute shader invocations. */ 1231 }; 1232 uint64_t counters[11]; 1233 }; 1234 }; 1235 1236 /** 1237 * For batch queries. 1238 */ 1239 union pipe_numeric_type_union 1240 { 1241 uint64_t u64; 1242 uint32_t u32; 1243 float f; 1244 }; 1245 1246 /** 1247 * Query result (returned by pipe_context::get_query_result). 1248 */ 1249 union pipe_query_result 1250 { 1251 /* PIPE_QUERY_OCCLUSION_PREDICATE */ 1252 /* PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE */ 1253 /* PIPE_QUERY_SO_OVERFLOW_PREDICATE */ 1254 /* PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE */ 1255 /* PIPE_QUERY_GPU_FINISHED */ 1256 bool b; 1257 1258 /* PIPE_QUERY_OCCLUSION_COUNTER */ 1259 /* PIPE_QUERY_TIMESTAMP */ 1260 /* PIPE_QUERY_TIME_ELAPSED */ 1261 /* PIPE_QUERY_PRIMITIVES_GENERATED */ 1262 /* PIPE_QUERY_PRIMITIVES_EMITTED */ 1263 /* PIPE_DRIVER_QUERY_TYPE_UINT64 */ 1264 /* PIPE_DRIVER_QUERY_TYPE_BYTES */ 1265 /* PIPE_DRIVER_QUERY_TYPE_MICROSECONDS */ 1266 /* PIPE_DRIVER_QUERY_TYPE_HZ */ 1267 uint64_t u64; 1268 1269 /* PIPE_DRIVER_QUERY_TYPE_UINT */ 1270 uint32_t u32; 1271 1272 /* PIPE_DRIVER_QUERY_TYPE_FLOAT */ 1273 /* PIPE_DRIVER_QUERY_TYPE_PERCENTAGE */ 1274 float f; 1275 1276 /* PIPE_QUERY_SO_STATISTICS */ 1277 struct pipe_query_data_so_statistics so_statistics; 1278 1279 /* PIPE_QUERY_TIMESTAMP_DISJOINT */ 1280 struct pipe_query_data_timestamp_disjoint timestamp_disjoint; 1281 1282 /* PIPE_QUERY_PIPELINE_STATISTICS */ 1283 struct pipe_query_data_pipeline_statistics pipeline_statistics; 1284 1285 /* batch queries (variable length) */ 1286 union pipe_numeric_type_union batch[1]; 1287 }; 1288 1289 enum pipe_query_value_type 1290 { 1291 PIPE_QUERY_TYPE_I32, 1292 PIPE_QUERY_TYPE_U32, 1293 PIPE_QUERY_TYPE_I64, 1294 PIPE_QUERY_TYPE_U64, 1295 }; 1296 1297 enum pipe_query_flags 1298 { 1299 PIPE_QUERY_WAIT = (1 << 0), 1300 PIPE_QUERY_PARTIAL = (1 << 1), 1301 }; 1302 1303 union pipe_color_union 1304 { 1305 float f[4]; 1306 int i[4]; 1307 unsigned int ui[4]; 1308 }; 1309 1310 enum pipe_driver_query_type 1311 { 1312 PIPE_DRIVER_QUERY_TYPE_UINT64, 1313 PIPE_DRIVER_QUERY_TYPE_UINT, 1314 PIPE_DRIVER_QUERY_TYPE_FLOAT, 1315 PIPE_DRIVER_QUERY_TYPE_PERCENTAGE, 1316 PIPE_DRIVER_QUERY_TYPE_BYTES, 1317 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS, 1318 PIPE_DRIVER_QUERY_TYPE_HZ, 1319 PIPE_DRIVER_QUERY_TYPE_DBM, 1320 PIPE_DRIVER_QUERY_TYPE_TEMPERATURE, 1321 PIPE_DRIVER_QUERY_TYPE_VOLTS, 1322 PIPE_DRIVER_QUERY_TYPE_AMPS, 1323 PIPE_DRIVER_QUERY_TYPE_WATTS, 1324 }; 1325 1326 /* Whether an average value per frame or a cumulative value should be 1327 * displayed. 1328 */ 1329 enum pipe_driver_query_result_type 1330 { 1331 PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 1332 PIPE_DRIVER_QUERY_RESULT_TYPE_CUMULATIVE, 1333 }; 1334 1335 /** 1336 * Some hardware requires some hardware-specific queries to be submitted 1337 * as batched queries. The corresponding query objects are created using 1338 * create_batch_query, and at most one such query may be active at 1339 * any time. 1340 */ 1341 #define PIPE_DRIVER_QUERY_FLAG_BATCH (1 << 0) 1342 1343 /* Do not list this query in the HUD. */ 1344 #define PIPE_DRIVER_QUERY_FLAG_DONT_LIST (1 << 1) 1345 1346 struct pipe_driver_query_info 1347 { 1348 const char *name; 1349 unsigned query_type; /* PIPE_QUERY_DRIVER_SPECIFIC + i */ 1350 union pipe_numeric_type_union max_value; /* max value that can be returned */ 1351 enum pipe_driver_query_type type; 1352 enum pipe_driver_query_result_type result_type; 1353 unsigned group_id; 1354 unsigned flags; 1355 }; 1356 1357 struct pipe_driver_query_group_info 1358 { 1359 const char *name; 1360 unsigned max_active_queries; 1361 unsigned num_queries; 1362 }; 1363 1364 enum pipe_fd_type 1365 { 1366 PIPE_FD_TYPE_NATIVE_SYNC, 1367 PIPE_FD_TYPE_SYNCOBJ, 1368 PIPE_FD_TYPE_TIMELINE_SEMAPHORE, 1369 }; 1370 1371 /** 1372 * counter type and counter data type enums used by INTEL_performance_query 1373 * APIs in gallium drivers. 1374 */ 1375 enum pipe_perf_counter_type 1376 { 1377 PIPE_PERF_COUNTER_TYPE_EVENT, 1378 PIPE_PERF_COUNTER_TYPE_DURATION_NORM, 1379 PIPE_PERF_COUNTER_TYPE_DURATION_RAW, 1380 PIPE_PERF_COUNTER_TYPE_THROUGHPUT, 1381 PIPE_PERF_COUNTER_TYPE_RAW, 1382 PIPE_PERF_COUNTER_TYPE_TIMESTAMP, 1383 }; 1384 1385 enum pipe_perf_counter_data_type 1386 { 1387 PIPE_PERF_COUNTER_DATA_TYPE_BOOL32, 1388 PIPE_PERF_COUNTER_DATA_TYPE_UINT32, 1389 PIPE_PERF_COUNTER_DATA_TYPE_UINT64, 1390 PIPE_PERF_COUNTER_DATA_TYPE_FLOAT, 1391 PIPE_PERF_COUNTER_DATA_TYPE_DOUBLE, 1392 }; 1393 1394 #define PIPE_UUID_SIZE 16 1395 #define PIPE_LUID_SIZE 8 1396 1397 #ifdef PIPE_OS_UNIX 1398 #define PIPE_MEMORY_FD 1399 #endif 1400 1401 #ifdef __cplusplus 1402 } 1403 #endif 1404 1405 #endif 1406