1 /* 2 * Copyright (c) 2021-2022 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 9 #ifndef HPM_QEI_H 10 #define HPM_QEI_H 11 12 typedef struct { 13 __RW uint32_t CR; /* 0x0: Control register */ 14 __RW uint32_t PHCFG; /* 0x4: Phase configure register */ 15 __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */ 16 __RW uint32_t PHIDX; /* 0xC: Phase index register */ 17 __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */ 18 __RW uint32_t READEN; /* 0x14: Read event enable register */ 19 __RW uint32_t ZCMP; /* 0x18: Z comparator */ 20 __RW uint32_t PHCMP; /* 0x1C: Phase comparator */ 21 __RW uint32_t SPDCMP; /* 0x20: Speed comparator */ 22 __RW uint32_t DMAEN; /* 0x24: DMA request enable register */ 23 __RW uint32_t SR; /* 0x28: Status register */ 24 __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */ 25 struct { 26 __RW uint32_t Z; /* 0x30: Z counter */ 27 __R uint32_t PH; /* 0x34: Phase counter */ 28 __RW uint32_t SPD; /* 0x38: Speed counter */ 29 __R uint32_t TMR; /* 0x3C: Timer counter */ 30 } COUNT[4]; 31 __R uint32_t SPDHIS[4]; /* 0x70 - 0x7C: Speed history */ 32 } QEI_Type; 33 34 35 /* Bitfield definition for register: CR */ 36 /* 37 * READ (WO) 38 * 39 * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0 40 */ 41 #define QEI_CR_READ_MASK (0x80000000UL) 42 #define QEI_CR_READ_SHIFT (31U) 43 #define QEI_CR_READ_SET(x) (((uint32_t)(x) << QEI_CR_READ_SHIFT) & QEI_CR_READ_MASK) 44 #define QEI_CR_READ_GET(x) (((uint32_t)(x) & QEI_CR_READ_MASK) >> QEI_CR_READ_SHIFT) 45 46 /* 47 * HRSTSPD (RW) 48 * 49 * 1- reset spdcnt when H assert 50 */ 51 #define QEI_CR_HRSTSPD_MASK (0x40000UL) 52 #define QEI_CR_HRSTSPD_SHIFT (18U) 53 #define QEI_CR_HRSTSPD_SET(x) (((uint32_t)(x) << QEI_CR_HRSTSPD_SHIFT) & QEI_CR_HRSTSPD_MASK) 54 #define QEI_CR_HRSTSPD_GET(x) (((uint32_t)(x) & QEI_CR_HRSTSPD_MASK) >> QEI_CR_HRSTSPD_SHIFT) 55 56 /* 57 * HRSTPH (RW) 58 * 59 * 1- reset phcnt when H assert 60 */ 61 #define QEI_CR_HRSTPH_MASK (0x20000UL) 62 #define QEI_CR_HRSTPH_SHIFT (17U) 63 #define QEI_CR_HRSTPH_SET(x) (((uint32_t)(x) << QEI_CR_HRSTPH_SHIFT) & QEI_CR_HRSTPH_MASK) 64 #define QEI_CR_HRSTPH_GET(x) (((uint32_t)(x) & QEI_CR_HRSTPH_MASK) >> QEI_CR_HRSTPH_SHIFT) 65 66 /* 67 * HRSTZ (RW) 68 * 69 * 1- reset zcnt when H assert 70 */ 71 #define QEI_CR_HRSTZ_MASK (0x10000UL) 72 #define QEI_CR_HRSTZ_SHIFT (16U) 73 #define QEI_CR_HRSTZ_SET(x) (((uint32_t)(x) << QEI_CR_HRSTZ_SHIFT) & QEI_CR_HRSTZ_MASK) 74 #define QEI_CR_HRSTZ_GET(x) (((uint32_t)(x) & QEI_CR_HRSTZ_MASK) >> QEI_CR_HRSTZ_SHIFT) 75 76 /* 77 * PAUSESPD (RW) 78 * 79 * 1- pause spdcnt when PAUSE assert 80 */ 81 #define QEI_CR_PAUSESPD_MASK (0x4000U) 82 #define QEI_CR_PAUSESPD_SHIFT (14U) 83 #define QEI_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEI_CR_PAUSESPD_SHIFT) & QEI_CR_PAUSESPD_MASK) 84 #define QEI_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEI_CR_PAUSESPD_MASK) >> QEI_CR_PAUSESPD_SHIFT) 85 86 /* 87 * PAUSEPH (RW) 88 * 89 * 1- pause phcnt when PAUSE assert 90 */ 91 #define QEI_CR_PAUSEPH_MASK (0x2000U) 92 #define QEI_CR_PAUSEPH_SHIFT (13U) 93 #define QEI_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEI_CR_PAUSEPH_SHIFT) & QEI_CR_PAUSEPH_MASK) 94 #define QEI_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEI_CR_PAUSEPH_MASK) >> QEI_CR_PAUSEPH_SHIFT) 95 96 /* 97 * PAUSEZ (RW) 98 * 99 * 1- pause zcnt when PAUSE assert 100 */ 101 #define QEI_CR_PAUSEZ_MASK (0x1000U) 102 #define QEI_CR_PAUSEZ_SHIFT (12U) 103 #define QEI_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEI_CR_PAUSEZ_SHIFT) & QEI_CR_PAUSEZ_MASK) 104 #define QEI_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEI_CR_PAUSEZ_MASK) >> QEI_CR_PAUSEZ_SHIFT) 105 106 /* 107 * HRDIR1 (RW) 108 * 109 * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction) 110 */ 111 #define QEI_CR_HRDIR1_MASK (0x800U) 112 #define QEI_CR_HRDIR1_SHIFT (11U) 113 #define QEI_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEI_CR_HRDIR1_SHIFT) & QEI_CR_HRDIR1_MASK) 114 #define QEI_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEI_CR_HRDIR1_MASK) >> QEI_CR_HRDIR1_SHIFT) 115 116 /* 117 * HRDIR0 (RW) 118 * 119 * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction) 120 */ 121 #define QEI_CR_HRDIR0_MASK (0x400U) 122 #define QEI_CR_HRDIR0_SHIFT (10U) 123 #define QEI_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEI_CR_HRDIR0_SHIFT) & QEI_CR_HRDIR0_MASK) 124 #define QEI_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEI_CR_HRDIR0_MASK) >> QEI_CR_HRDIR0_SHIFT) 125 126 /* 127 * HFDIR1 (RW) 128 * 129 * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction) 130 */ 131 #define QEI_CR_HFDIR1_MASK (0x200U) 132 #define QEI_CR_HFDIR1_SHIFT (9U) 133 #define QEI_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEI_CR_HFDIR1_SHIFT) & QEI_CR_HFDIR1_MASK) 134 #define QEI_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEI_CR_HFDIR1_MASK) >> QEI_CR_HFDIR1_SHIFT) 135 136 /* 137 * HFDIR0 (RW) 138 * 139 * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction) 140 */ 141 #define QEI_CR_HFDIR0_MASK (0x100U) 142 #define QEI_CR_HFDIR0_SHIFT (8U) 143 #define QEI_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEI_CR_HFDIR0_SHIFT) & QEI_CR_HFDIR0_MASK) 144 #define QEI_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEI_CR_HFDIR0_MASK) >> QEI_CR_HFDIR0_SHIFT) 145 146 /* 147 * SNAPEN (RW) 148 * 149 * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert 150 */ 151 #define QEI_CR_SNAPEN_MASK (0x20U) 152 #define QEI_CR_SNAPEN_SHIFT (5U) 153 #define QEI_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEI_CR_SNAPEN_SHIFT) & QEI_CR_SNAPEN_MASK) 154 #define QEI_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEI_CR_SNAPEN_MASK) >> QEI_CR_SNAPEN_SHIFT) 155 156 /* 157 * RSTCNT (RW) 158 * 159 * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx 160 */ 161 #define QEI_CR_RSTCNT_MASK (0x10U) 162 #define QEI_CR_RSTCNT_SHIFT (4U) 163 #define QEI_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEI_CR_RSTCNT_SHIFT) & QEI_CR_RSTCNT_MASK) 164 #define QEI_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEI_CR_RSTCNT_MASK) >> QEI_CR_RSTCNT_SHIFT) 165 166 /* 167 * ENCTYP (RW) 168 * 169 * 00-abz; 01-pd; 10-ud; 11-reserved 170 */ 171 #define QEI_CR_ENCTYP_MASK (0x3U) 172 #define QEI_CR_ENCTYP_SHIFT (0U) 173 #define QEI_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEI_CR_ENCTYP_SHIFT) & QEI_CR_ENCTYP_MASK) 174 #define QEI_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEI_CR_ENCTYP_MASK) >> QEI_CR_ENCTYP_SHIFT) 175 176 /* Bitfield definition for register: PHCFG */ 177 /* 178 * ZCNTCFG (RW) 179 * 180 * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0 181 * 0- zcnt will increment or decrement when Z input assert 182 */ 183 #define QEI_PHCFG_ZCNTCFG_MASK (0x400000UL) 184 #define QEI_PHCFG_ZCNTCFG_SHIFT (22U) 185 #define QEI_PHCFG_ZCNTCFG_SET(x) (((uint32_t)(x) << QEI_PHCFG_ZCNTCFG_SHIFT) & QEI_PHCFG_ZCNTCFG_MASK) 186 #define QEI_PHCFG_ZCNTCFG_GET(x) (((uint32_t)(x) & QEI_PHCFG_ZCNTCFG_MASK) >> QEI_PHCFG_ZCNTCFG_SHIFT) 187 188 /* 189 * PHCALIZ (RW) 190 * 191 * 1- phcnt will set to phidx when Z input assert 192 */ 193 #define QEI_PHCFG_PHCALIZ_MASK (0x200000UL) 194 #define QEI_PHCFG_PHCALIZ_SHIFT (21U) 195 #define QEI_PHCFG_PHCALIZ_SET(x) (((uint32_t)(x) << QEI_PHCFG_PHCALIZ_SHIFT) & QEI_PHCFG_PHCALIZ_MASK) 196 #define QEI_PHCFG_PHCALIZ_GET(x) (((uint32_t)(x) & QEI_PHCFG_PHCALIZ_MASK) >> QEI_PHCFG_PHCALIZ_SHIFT) 197 198 /* 199 * PHMAX (RW) 200 * 201 * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax 202 */ 203 #define QEI_PHCFG_PHMAX_MASK (0x1FFFFFUL) 204 #define QEI_PHCFG_PHMAX_SHIFT (0U) 205 #define QEI_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEI_PHCFG_PHMAX_SHIFT) & QEI_PHCFG_PHMAX_MASK) 206 #define QEI_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEI_PHCFG_PHMAX_MASK) >> QEI_PHCFG_PHMAX_SHIFT) 207 208 /* Bitfield definition for register: WDGCFG */ 209 /* 210 * WDGEN (RW) 211 * 212 * 1- enable wdog counter 213 */ 214 #define QEI_WDGCFG_WDGEN_MASK (0x80000000UL) 215 #define QEI_WDGCFG_WDGEN_SHIFT (31U) 216 #define QEI_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEI_WDGCFG_WDGEN_SHIFT) & QEI_WDGCFG_WDGEN_MASK) 217 #define QEI_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEI_WDGCFG_WDGEN_MASK) >> QEI_WDGCFG_WDGEN_SHIFT) 218 219 /* 220 * WDGTO (RW) 221 * 222 * watch dog timeout value 223 */ 224 #define QEI_WDGCFG_WDGTO_MASK (0x7FFFFFFFUL) 225 #define QEI_WDGCFG_WDGTO_SHIFT (0U) 226 #define QEI_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEI_WDGCFG_WDGTO_SHIFT) & QEI_WDGCFG_WDGTO_MASK) 227 #define QEI_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEI_WDGCFG_WDGTO_MASK) >> QEI_WDGCFG_WDGTO_SHIFT) 228 229 /* Bitfield definition for register: PHIDX */ 230 /* 231 * PHIDX (RW) 232 * 233 * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1 234 */ 235 #define QEI_PHIDX_PHIDX_MASK (0x1FFFFFUL) 236 #define QEI_PHIDX_PHIDX_SHIFT (0U) 237 #define QEI_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEI_PHIDX_PHIDX_SHIFT) & QEI_PHIDX_PHIDX_MASK) 238 #define QEI_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEI_PHIDX_PHIDX_MASK) >> QEI_PHIDX_PHIDX_SHIFT) 239 240 /* Bitfield definition for register: TRGOEN */ 241 /* 242 * WDGFEN (RW) 243 * 244 * 1- enable trigger output when wdg flag set 245 */ 246 #define QEI_TRGOEN_WDGFEN_MASK (0x80000000UL) 247 #define QEI_TRGOEN_WDGFEN_SHIFT (31U) 248 #define QEI_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_WDGFEN_SHIFT) & QEI_TRGOEN_WDGFEN_MASK) 249 #define QEI_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_WDGFEN_MASK) >> QEI_TRGOEN_WDGFEN_SHIFT) 250 251 /* 252 * HOMEFEN (RW) 253 * 254 * 1- enable trigger output when homef flag set 255 */ 256 #define QEI_TRGOEN_HOMEFEN_MASK (0x40000000UL) 257 #define QEI_TRGOEN_HOMEFEN_SHIFT (30U) 258 #define QEI_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_HOMEFEN_SHIFT) & QEI_TRGOEN_HOMEFEN_MASK) 259 #define QEI_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_HOMEFEN_MASK) >> QEI_TRGOEN_HOMEFEN_SHIFT) 260 261 /* 262 * POSCMPFEN (RW) 263 * 264 * 1- enable trigger output when poscmpf flag set 265 */ 266 #define QEI_TRGOEN_POSCMPFEN_MASK (0x20000000UL) 267 #define QEI_TRGOEN_POSCMPFEN_SHIFT (29U) 268 #define QEI_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_POSCMPFEN_SHIFT) & QEI_TRGOEN_POSCMPFEN_MASK) 269 #define QEI_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_POSCMPFEN_MASK) >> QEI_TRGOEN_POSCMPFEN_SHIFT) 270 271 /* 272 * ZPHFEN (RW) 273 * 274 * 1- enable trigger output when zphf flag set 275 */ 276 #define QEI_TRGOEN_ZPHFEN_MASK (0x10000000UL) 277 #define QEI_TRGOEN_ZPHFEN_SHIFT (28U) 278 #define QEI_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_TRGOEN_ZPHFEN_SHIFT) & QEI_TRGOEN_ZPHFEN_MASK) 279 #define QEI_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_TRGOEN_ZPHFEN_MASK) >> QEI_TRGOEN_ZPHFEN_SHIFT) 280 281 /* Bitfield definition for register: READEN */ 282 /* 283 * WDGFEN (RW) 284 * 285 * 1- load counters to their read registers when wdg flag set 286 */ 287 #define QEI_READEN_WDGFEN_MASK (0x80000000UL) 288 #define QEI_READEN_WDGFEN_SHIFT (31U) 289 #define QEI_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_READEN_WDGFEN_SHIFT) & QEI_READEN_WDGFEN_MASK) 290 #define QEI_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_READEN_WDGFEN_MASK) >> QEI_READEN_WDGFEN_SHIFT) 291 292 /* 293 * HOMEFEN (RW) 294 * 295 * 1- load counters to their read registers when homef flag set 296 */ 297 #define QEI_READEN_HOMEFEN_MASK (0x40000000UL) 298 #define QEI_READEN_HOMEFEN_SHIFT (30U) 299 #define QEI_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_READEN_HOMEFEN_SHIFT) & QEI_READEN_HOMEFEN_MASK) 300 #define QEI_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_READEN_HOMEFEN_MASK) >> QEI_READEN_HOMEFEN_SHIFT) 301 302 /* 303 * POSCMPFEN (RW) 304 * 305 * 1- load counters to their read registers when poscmpf flag set 306 */ 307 #define QEI_READEN_POSCMPFEN_MASK (0x20000000UL) 308 #define QEI_READEN_POSCMPFEN_SHIFT (29U) 309 #define QEI_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_READEN_POSCMPFEN_SHIFT) & QEI_READEN_POSCMPFEN_MASK) 310 #define QEI_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_READEN_POSCMPFEN_MASK) >> QEI_READEN_POSCMPFEN_SHIFT) 311 312 /* 313 * ZPHFEN (RW) 314 * 315 * 1- load counters to their read registers when zphf flag set 316 */ 317 #define QEI_READEN_ZPHFEN_MASK (0x10000000UL) 318 #define QEI_READEN_ZPHFEN_SHIFT (28U) 319 #define QEI_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_READEN_ZPHFEN_SHIFT) & QEI_READEN_ZPHFEN_MASK) 320 #define QEI_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_READEN_ZPHFEN_MASK) >> QEI_READEN_ZPHFEN_SHIFT) 321 322 /* Bitfield definition for register: ZCMP */ 323 /* 324 * ZCMP (RW) 325 * 326 * zcnt postion compare value 327 */ 328 #define QEI_ZCMP_ZCMP_MASK (0xFFFFFFFFUL) 329 #define QEI_ZCMP_ZCMP_SHIFT (0U) 330 #define QEI_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEI_ZCMP_ZCMP_SHIFT) & QEI_ZCMP_ZCMP_MASK) 331 #define QEI_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEI_ZCMP_ZCMP_MASK) >> QEI_ZCMP_ZCMP_SHIFT) 332 333 /* Bitfield definition for register: PHCMP */ 334 /* 335 * ZCMPDIS (RW) 336 * 337 * 1- postion compare not include zcnt 338 */ 339 #define QEI_PHCMP_ZCMPDIS_MASK (0x80000000UL) 340 #define QEI_PHCMP_ZCMPDIS_SHIFT (31U) 341 #define QEI_PHCMP_ZCMPDIS_SET(x) (((uint32_t)(x) << QEI_PHCMP_ZCMPDIS_SHIFT) & QEI_PHCMP_ZCMPDIS_MASK) 342 #define QEI_PHCMP_ZCMPDIS_GET(x) (((uint32_t)(x) & QEI_PHCMP_ZCMPDIS_MASK) >> QEI_PHCMP_ZCMPDIS_SHIFT) 343 344 /* 345 * DIRCMPDIS (RW) 346 * 347 * 1- postion compare not include rotation direction 348 */ 349 #define QEI_PHCMP_DIRCMPDIS_MASK (0x40000000UL) 350 #define QEI_PHCMP_DIRCMPDIS_SHIFT (30U) 351 #define QEI_PHCMP_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEI_PHCMP_DIRCMPDIS_SHIFT) & QEI_PHCMP_DIRCMPDIS_MASK) 352 #define QEI_PHCMP_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEI_PHCMP_DIRCMPDIS_MASK) >> QEI_PHCMP_DIRCMPDIS_SHIFT) 353 354 /* 355 * DIRCMP (RW) 356 * 357 * 0- position compare need positive rotation 358 * 1- position compare need negative rotation 359 */ 360 #define QEI_PHCMP_DIRCMP_MASK (0x20000000UL) 361 #define QEI_PHCMP_DIRCMP_SHIFT (29U) 362 #define QEI_PHCMP_DIRCMP_SET(x) (((uint32_t)(x) << QEI_PHCMP_DIRCMP_SHIFT) & QEI_PHCMP_DIRCMP_MASK) 363 #define QEI_PHCMP_DIRCMP_GET(x) (((uint32_t)(x) & QEI_PHCMP_DIRCMP_MASK) >> QEI_PHCMP_DIRCMP_SHIFT) 364 365 /* 366 * PHCMP (RW) 367 * 368 * phcnt position compare value 369 */ 370 #define QEI_PHCMP_PHCMP_MASK (0x1FFFFFUL) 371 #define QEI_PHCMP_PHCMP_SHIFT (0U) 372 #define QEI_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEI_PHCMP_PHCMP_SHIFT) & QEI_PHCMP_PHCMP_MASK) 373 #define QEI_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEI_PHCMP_PHCMP_MASK) >> QEI_PHCMP_PHCMP_SHIFT) 374 375 /* Bitfield definition for register: SPDCMP */ 376 /* 377 * SPDCMP (RW) 378 * 379 * spdcnt position compare value 380 */ 381 #define QEI_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL) 382 #define QEI_SPDCMP_SPDCMP_SHIFT (0U) 383 #define QEI_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEI_SPDCMP_SPDCMP_SHIFT) & QEI_SPDCMP_SPDCMP_MASK) 384 #define QEI_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEI_SPDCMP_SPDCMP_MASK) >> QEI_SPDCMP_SPDCMP_SHIFT) 385 386 /* Bitfield definition for register: DMAEN */ 387 /* 388 * WDGFEN (RW) 389 * 390 * 1- generate dma request when wdg flag set 391 */ 392 #define QEI_DMAEN_WDGFEN_MASK (0x80000000UL) 393 #define QEI_DMAEN_WDGFEN_SHIFT (31U) 394 #define QEI_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_WDGFEN_SHIFT) & QEI_DMAEN_WDGFEN_MASK) 395 #define QEI_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_WDGFEN_MASK) >> QEI_DMAEN_WDGFEN_SHIFT) 396 397 /* 398 * HOMEFEN (RW) 399 * 400 * 1- generate dma request when homef flag set 401 */ 402 #define QEI_DMAEN_HOMEFEN_MASK (0x40000000UL) 403 #define QEI_DMAEN_HOMEFEN_SHIFT (30U) 404 #define QEI_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_HOMEFEN_SHIFT) & QEI_DMAEN_HOMEFEN_MASK) 405 #define QEI_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_HOMEFEN_MASK) >> QEI_DMAEN_HOMEFEN_SHIFT) 406 407 /* 408 * POSCMPFEN (RW) 409 * 410 * 1- generate dma request when poscmpf flag set 411 */ 412 #define QEI_DMAEN_POSCMPFEN_MASK (0x20000000UL) 413 #define QEI_DMAEN_POSCMPFEN_SHIFT (29U) 414 #define QEI_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_POSCMPFEN_SHIFT) & QEI_DMAEN_POSCMPFEN_MASK) 415 #define QEI_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_POSCMPFEN_MASK) >> QEI_DMAEN_POSCMPFEN_SHIFT) 416 417 /* 418 * ZPHFEN (RW) 419 * 420 * 1- generate dma request when zphf flag set 421 */ 422 #define QEI_DMAEN_ZPHFEN_MASK (0x10000000UL) 423 #define QEI_DMAEN_ZPHFEN_SHIFT (28U) 424 #define QEI_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEI_DMAEN_ZPHFEN_SHIFT) & QEI_DMAEN_ZPHFEN_MASK) 425 #define QEI_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEI_DMAEN_ZPHFEN_MASK) >> QEI_DMAEN_ZPHFEN_SHIFT) 426 427 /* Bitfield definition for register: SR */ 428 /* 429 * WDGF (RW) 430 * 431 * watchdog flag 432 */ 433 #define QEI_SR_WDGF_MASK (0x80000000UL) 434 #define QEI_SR_WDGF_SHIFT (31U) 435 #define QEI_SR_WDGF_SET(x) (((uint32_t)(x) << QEI_SR_WDGF_SHIFT) & QEI_SR_WDGF_MASK) 436 #define QEI_SR_WDGF_GET(x) (((uint32_t)(x) & QEI_SR_WDGF_MASK) >> QEI_SR_WDGF_SHIFT) 437 438 /* 439 * HOMEF (RW) 440 * 441 * home flag 442 */ 443 #define QEI_SR_HOMEF_MASK (0x40000000UL) 444 #define QEI_SR_HOMEF_SHIFT (30U) 445 #define QEI_SR_HOMEF_SET(x) (((uint32_t)(x) << QEI_SR_HOMEF_SHIFT) & QEI_SR_HOMEF_MASK) 446 #define QEI_SR_HOMEF_GET(x) (((uint32_t)(x) & QEI_SR_HOMEF_MASK) >> QEI_SR_HOMEF_SHIFT) 447 448 /* 449 * POSCMPF (RW) 450 * 451 * postion compare match flag 452 */ 453 #define QEI_SR_POSCMPF_MASK (0x20000000UL) 454 #define QEI_SR_POSCMPF_SHIFT (29U) 455 #define QEI_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEI_SR_POSCMPF_SHIFT) & QEI_SR_POSCMPF_MASK) 456 #define QEI_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEI_SR_POSCMPF_MASK) >> QEI_SR_POSCMPF_SHIFT) 457 458 /* 459 * ZPHF (RW) 460 * 461 * z input flag 462 */ 463 #define QEI_SR_ZPHF_MASK (0x10000000UL) 464 #define QEI_SR_ZPHF_SHIFT (28U) 465 #define QEI_SR_ZPHF_SET(x) (((uint32_t)(x) << QEI_SR_ZPHF_SHIFT) & QEI_SR_ZPHF_MASK) 466 #define QEI_SR_ZPHF_GET(x) (((uint32_t)(x) & QEI_SR_ZPHF_MASK) >> QEI_SR_ZPHF_SHIFT) 467 468 /* Bitfield definition for register: IRQEN */ 469 /* 470 * WDGIE (RW) 471 * 472 * 1- generate interrupt when wdg flag set 473 */ 474 #define QEI_IRQEN_WDGIE_MASK (0x80000000UL) 475 #define QEI_IRQEN_WDGIE_SHIFT (31U) 476 #define QEI_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_WDGIE_SHIFT) & QEI_IRQEN_WDGIE_MASK) 477 #define QEI_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_WDGIE_MASK) >> QEI_IRQEN_WDGIE_SHIFT) 478 479 /* 480 * HOMEIE (RW) 481 * 482 * 1- generate interrupt when homef flag set 483 */ 484 #define QEI_IRQEN_HOMEIE_MASK (0x40000000UL) 485 #define QEI_IRQEN_HOMEIE_SHIFT (30U) 486 #define QEI_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_HOMEIE_SHIFT) & QEI_IRQEN_HOMEIE_MASK) 487 #define QEI_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_HOMEIE_MASK) >> QEI_IRQEN_HOMEIE_SHIFT) 488 489 /* 490 * POSCMPIE (RW) 491 * 492 * 1- generate interrupt when poscmpf flag set 493 */ 494 #define QEI_IRQEN_POSCMPIE_MASK (0x20000000UL) 495 #define QEI_IRQEN_POSCMPIE_SHIFT (29U) 496 #define QEI_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_POSCMPIE_SHIFT) & QEI_IRQEN_POSCMPIE_MASK) 497 #define QEI_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_POSCMPIE_MASK) >> QEI_IRQEN_POSCMPIE_SHIFT) 498 499 /* 500 * ZPHIE (RW) 501 * 502 * 1- generate interrupt when zphf flag set 503 */ 504 #define QEI_IRQEN_ZPHIE_MASK (0x10000000UL) 505 #define QEI_IRQEN_ZPHIE_SHIFT (28U) 506 #define QEI_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEI_IRQEN_ZPHIE_SHIFT) & QEI_IRQEN_ZPHIE_MASK) 507 #define QEI_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEI_IRQEN_ZPHIE_MASK) >> QEI_IRQEN_ZPHIE_SHIFT) 508 509 /* Bitfield definition for register of struct array COUNT: Z */ 510 /* 511 * ZCNT (RW) 512 * 513 * zcnt value 514 */ 515 #define QEI_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL) 516 #define QEI_COUNT_Z_ZCNT_SHIFT (0U) 517 #define QEI_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEI_COUNT_Z_ZCNT_SHIFT) & QEI_COUNT_Z_ZCNT_MASK) 518 #define QEI_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_Z_ZCNT_MASK) >> QEI_COUNT_Z_ZCNT_SHIFT) 519 520 /* Bitfield definition for register of struct array COUNT: PH */ 521 /* 522 * DIR (RO) 523 * 524 * 1- reverse rotation 525 * 0- forward rotation 526 */ 527 #define QEI_COUNT_PH_DIR_MASK (0x40000000UL) 528 #define QEI_COUNT_PH_DIR_SHIFT (30U) 529 #define QEI_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_DIR_MASK) >> QEI_COUNT_PH_DIR_SHIFT) 530 531 /* 532 * ASTAT (RO) 533 * 534 * 1- a input is high 535 * 0- a input is low 536 */ 537 #define QEI_COUNT_PH_ASTAT_MASK (0x4000000UL) 538 #define QEI_COUNT_PH_ASTAT_SHIFT (26U) 539 #define QEI_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_ASTAT_MASK) >> QEI_COUNT_PH_ASTAT_SHIFT) 540 541 /* 542 * BSTAT (RO) 543 * 544 * 1- b input is high 545 * 0- b input is low 546 */ 547 #define QEI_COUNT_PH_BSTAT_MASK (0x2000000UL) 548 #define QEI_COUNT_PH_BSTAT_SHIFT (25U) 549 #define QEI_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_BSTAT_MASK) >> QEI_COUNT_PH_BSTAT_SHIFT) 550 551 /* 552 * PHCNT (RO) 553 * 554 * phcnt value 555 */ 556 #define QEI_COUNT_PH_PHCNT_MASK (0x1FFFFFUL) 557 #define QEI_COUNT_PH_PHCNT_SHIFT (0U) 558 #define QEI_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_PH_PHCNT_MASK) >> QEI_COUNT_PH_PHCNT_SHIFT) 559 560 /* Bitfield definition for register of struct array COUNT: SPD */ 561 /* 562 * DIR (RO) 563 * 564 * 1- reverse rotation 565 * 0- forward rotation 566 */ 567 #define QEI_COUNT_SPD_DIR_MASK (0x80000000UL) 568 #define QEI_COUNT_SPD_DIR_SHIFT (31U) 569 #define QEI_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_DIR_MASK) >> QEI_COUNT_SPD_DIR_SHIFT) 570 571 /* 572 * ASTAT (RO) 573 * 574 * 1- a input is high 575 * 0- a input is low 576 */ 577 #define QEI_COUNT_SPD_ASTAT_MASK (0x40000000UL) 578 #define QEI_COUNT_SPD_ASTAT_SHIFT (30U) 579 #define QEI_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_ASTAT_MASK) >> QEI_COUNT_SPD_ASTAT_SHIFT) 580 581 /* 582 * BSTAT (RW) 583 * 584 * 1- b input is high 585 * 0- b input is low 586 */ 587 #define QEI_COUNT_SPD_BSTAT_MASK (0x20000000UL) 588 #define QEI_COUNT_SPD_BSTAT_SHIFT (29U) 589 #define QEI_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEI_COUNT_SPD_BSTAT_SHIFT) & QEI_COUNT_SPD_BSTAT_MASK) 590 #define QEI_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_BSTAT_MASK) >> QEI_COUNT_SPD_BSTAT_SHIFT) 591 592 /* 593 * SPDCNT (RO) 594 * 595 * spdcnt value 596 */ 597 #define QEI_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL) 598 #define QEI_COUNT_SPD_SPDCNT_SHIFT (0U) 599 #define QEI_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_SPD_SPDCNT_MASK) >> QEI_COUNT_SPD_SPDCNT_SHIFT) 600 601 /* Bitfield definition for register of struct array COUNT: TMR */ 602 /* 603 * TMRCNT (RO) 604 * 605 * 32 bit free run timer 606 */ 607 #define QEI_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL) 608 #define QEI_COUNT_TMR_TMRCNT_SHIFT (0U) 609 #define QEI_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEI_COUNT_TMR_TMRCNT_MASK) >> QEI_COUNT_TMR_TMRCNT_SHIFT) 610 611 /* Bitfield definition for register array: SPDHIS */ 612 /* 613 * SPDHIS0 (RO) 614 * 615 * copy of spdcnt, load from spdcnt after any transition from a = low, b = low 616 */ 617 #define QEI_SPDHIS_SPDHIS0_MASK (0xFFFFFFFFUL) 618 #define QEI_SPDHIS_SPDHIS0_SHIFT (0U) 619 #define QEI_SPDHIS_SPDHIS0_GET(x) (((uint32_t)(x) & QEI_SPDHIS_SPDHIS0_MASK) >> QEI_SPDHIS_SPDHIS0_SHIFT) 620 621 622 623 /* COUNT register group index macro definition */ 624 #define QEI_COUNT_CURRENT (0UL) 625 #define QEI_COUNT_READ (1UL) 626 #define QEI_COUNT_SNAP0 (2UL) 627 #define QEI_COUNT_SNAP1 (3UL) 628 629 /* SPDHIS register group index macro definition */ 630 #define QEI_SPDHIS_SPDHIS0 (0UL) 631 #define QEI_SPDHIS_SPDHIS1 (1UL) 632 #define QEI_SPDHIS_SPDHIS2 (2UL) 633 #define QEI_SPDHIS_SPDHIS3 (3UL) 634 635 636 #endif /* HPM_QEI_H */