1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors: Marek Olšák <maraeo@gmail.com>
24 *
25 */
26
27 /**
28 * This file contains common screen and context structures and functions
29 * for r600g and radeonsi.
30 */
31
32 #ifndef R600_PIPE_COMMON_H
33 #define R600_PIPE_COMMON_H
34
35 #include <stdio.h>
36
37 #include "winsys/radeon_winsys.h"
38
39 #include "util/disk_cache.h"
40 #include "util/u_blitter.h"
41 #include "util/list.h"
42 #include "util/u_range.h"
43 #include "util/slab.h"
44 #include "util/u_suballoc.h"
45 #include "util/u_transfer.h"
46 #include "util/u_threaded_context.h"
47
48 #include "compiler/nir/nir.h"
49
50 struct u_log_context;
51 #define ATI_VENDOR_ID 0x1002
52
53 #define R600_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
54 #define R600_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
55 #define R600_RESOURCE_FLAG_FORCE_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
56 #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
57
58 #define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0)
59 /* Pipeline & streamout query controls. */
60 #define R600_CONTEXT_START_PIPELINE_STATS (1u << 1)
61 #define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2)
62 #define R600_CONTEXT_FLUSH_FOR_RENDER_COND (1u << 3)
63 #define R600_CONTEXT_PRIVATE_FLAG (1u << 4)
64
65 /* special primitive types */
66 #define R600_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
67
68 #define R600_NOT_QUERY 0xffffffff
69
70 /* Debug flags. */
71 #define DBG_VS (1 << PIPE_SHADER_VERTEX)
72 #define DBG_PS (1 << PIPE_SHADER_FRAGMENT)
73 #define DBG_GS (1 << PIPE_SHADER_GEOMETRY)
74 #define DBG_TCS (1 << PIPE_SHADER_TESS_CTRL)
75 #define DBG_TES (1 << PIPE_SHADER_TESS_EVAL)
76 #define DBG_CS (1 << PIPE_SHADER_COMPUTE)
77 #define DBG_ALL_SHADERS (DBG_FS - 1)
78 #define DBG_FS (1 << 6) /* fetch shader */
79 #define DBG_TEX (1 << 7)
80 #define DBG_NIR (1 << 8)
81 #define DBG_COMPUTE (1 << 9)
82 /* gap */
83 #define DBG_VM (1 << 11)
84 #define DBG_PREOPT_IR (1 << 15)
85 #define DBG_CHECK_IR (1 << 16)
86 /* gaps */
87 #define DBG_TEST_DMA (1 << 20)
88 /* Bits 21-31 are reserved for the r600g driver. */
89 /* features */
90 #define DBG_NO_ASYNC_DMA (1ull << 32)
91 #define DBG_NO_HYPERZ (1ull << 33)
92 #define DBG_NO_DISCARD_RANGE (1ull << 34)
93 #define DBG_NO_2D_TILING (1ull << 35)
94 #define DBG_NO_TILING (1ull << 36)
95 #define DBG_SWITCH_ON_EOP (1ull << 37)
96 #define DBG_FORCE_DMA (1ull << 38)
97 #define DBG_INFO (1ull << 40)
98 #define DBG_NO_WC (1ull << 41)
99 #define DBG_CHECK_VM (1ull << 42)
100 /* gap */
101 #define DBG_TEST_VMFAULT_CP (1ull << 51)
102 #define DBG_TEST_VMFAULT_SDMA (1ull << 52)
103 #define DBG_TEST_VMFAULT_SHADER (1ull << 53)
104
105 #define R600_MAP_BUFFER_ALIGNMENT 64
106 #define R600_MAX_VIEWPORTS 16
107
108 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
109
110 enum r600_coherency {
111 R600_COHERENCY_NONE, /* no cache flushes needed */
112 R600_COHERENCY_SHADER,
113 R600_COHERENCY_CB_META,
114 };
115
116 #if UTIL_ARCH_BIG_ENDIAN
117 #define R600_BIG_ENDIAN 1
118 #else
119 #define R600_BIG_ENDIAN 0
120 #endif
121
122 struct r600_common_context;
123 struct r600_perfcounters;
124 struct tgsi_shader_info;
125 struct r600_qbo_state;
126
127 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
128 * at the moment.
129 */
130 struct r600_resource {
131 struct threaded_resource b;
132
133 /* Winsys objects. */
134 struct pb_buffer *buf;
135 uint64_t gpu_address;
136 /* Memory usage if the buffer placement is optimal. */
137 uint64_t vram_usage;
138 uint64_t gart_usage;
139
140 /* Resource properties. */
141 uint64_t bo_size;
142 unsigned bo_alignment;
143 enum radeon_bo_domain domains;
144 enum radeon_bo_flag flags;
145 unsigned bind_history;
146
147 /* The buffer range which is initialized (with a write transfer,
148 * streamout, DMA, or as a random access target). The rest of
149 * the buffer is considered invalid and can be mapped unsynchronized.
150 *
151 * This allows unsychronized mapping of a buffer range which hasn't
152 * been used yet. It's for applications which forget to use
153 * the unsynchronized map flag and expect the driver to figure it out.
154 */
155 struct util_range valid_buffer_range;
156
157 /* Whether the resource has been exported via resource_get_handle. */
158 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
159
160 /* Whether this resource is referenced by bindless handles. */
161 bool texture_handle_allocated;
162 bool image_handle_allocated;
163 bool compute_global_bo;
164
165 /*
166 * EG/Cayman only - for RAT operations hw need an immediate buffer
167 * to store results in.
168 */
169 struct r600_resource *immed_buffer;
170 };
171
172 struct r600_transfer {
173 struct threaded_transfer b;
174 struct r600_resource *staging;
175 };
176
177 struct r600_fmask_info {
178 uint64_t offset;
179 uint64_t size;
180 unsigned alignment;
181 unsigned pitch_in_pixels;
182 unsigned bank_height;
183 unsigned slice_tile_max;
184 unsigned tile_mode_index;
185 unsigned tile_swizzle;
186 };
187
188 struct r600_cmask_info {
189 uint64_t offset;
190 uint64_t size;
191 unsigned alignment;
192 unsigned slice_tile_max;
193 uint64_t base_address_reg;
194 };
195
196 struct r600_texture {
197 struct r600_resource resource;
198
199 uint64_t size;
200 unsigned num_level0_transfers;
201 enum pipe_format db_render_format;
202 bool is_depth;
203 bool db_compatible;
204 bool can_sample_z;
205 bool can_sample_s;
206 unsigned dirty_level_mask; /* each bit says if that mipmap is compressed */
207 unsigned stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
208 struct r600_texture *flushed_depth_texture;
209 struct radeon_surf surface;
210
211 /* Colorbuffer compression and fast clear. */
212 struct r600_fmask_info fmask;
213 struct r600_cmask_info cmask;
214 struct r600_resource *cmask_buffer;
215 unsigned cb_color_info; /* fast clear enable bit */
216 unsigned color_clear_value[2];
217 unsigned last_msaa_resolve_target_micro_mode;
218
219 /* Depth buffer compression and fast clear. */
220 uint64_t htile_offset;
221 bool depth_cleared; /* if it was cleared at least once */
222 float depth_clear_value;
223 bool stencil_cleared; /* if it was cleared at least once */
224 uint8_t stencil_clear_value;
225
226 bool non_disp_tiling; /* R600-Cayman only */
227
228 /* Counter that should be non-zero if the texture is bound to a
229 * framebuffer. Implemented in radeonsi only.
230 */
231 uint32_t framebuffers_bound;
232 };
233
234 struct r600_surface {
235 struct pipe_surface base;
236
237 /* These can vary with block-compressed textures. */
238 unsigned width0;
239 unsigned height0;
240
241 bool color_initialized;
242 bool depth_initialized;
243
244 /* Misc. color flags. */
245 bool alphatest_bypass;
246 bool export_16bpc;
247 bool color_is_int8;
248 bool color_is_int10;
249
250 /* Color registers. */
251 unsigned cb_color_info;
252 unsigned cb_color_base;
253 unsigned cb_color_view;
254 unsigned cb_color_size; /* R600 only */
255 unsigned cb_color_dim; /* EG only */
256 unsigned cb_color_pitch; /* EG and later */
257 unsigned cb_color_slice; /* EG and later */
258 unsigned cb_color_attrib; /* EG and later */
259 unsigned cb_color_fmask; /* CB_COLORn_FMASK (EG and later) or CB_COLORn_FRAG (r600) */
260 unsigned cb_color_fmask_slice; /* EG and later */
261 unsigned cb_color_cmask; /* CB_COLORn_TILE (r600 only) */
262 unsigned cb_color_mask; /* R600 only */
263 struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
264 struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
265
266 /* DB registers. */
267 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE (EG and later) or DB_DEPTH_BASE (r600) */
268 uint64_t db_stencil_base; /* EG and later */
269 uint64_t db_htile_data_base;
270 unsigned db_depth_info; /* R600 only, then SI and later */
271 unsigned db_z_info; /* EG and later */
272 unsigned db_depth_view;
273 unsigned db_depth_size;
274 unsigned db_depth_slice; /* EG and later */
275 unsigned db_stencil_info; /* EG and later */
276 unsigned db_prefetch_limit; /* R600 only */
277 unsigned db_htile_surface;
278 unsigned db_preload_control; /* EG and later */
279 };
280
281 struct r600_mmio_counter {
282 unsigned busy;
283 unsigned idle;
284 };
285
286 union r600_mmio_counters {
287 struct r600_mmio_counters_named {
288 /* For global GPU load including SDMA. */
289 struct r600_mmio_counter gpu;
290
291 /* GRBM_STATUS */
292 struct r600_mmio_counter spi;
293 struct r600_mmio_counter gui;
294 struct r600_mmio_counter ta;
295 struct r600_mmio_counter gds;
296 struct r600_mmio_counter vgt;
297 struct r600_mmio_counter ia;
298 struct r600_mmio_counter sx;
299 struct r600_mmio_counter wd;
300 struct r600_mmio_counter bci;
301 struct r600_mmio_counter sc;
302 struct r600_mmio_counter pa;
303 struct r600_mmio_counter db;
304 struct r600_mmio_counter cp;
305 struct r600_mmio_counter cb;
306
307 /* SRBM_STATUS2 */
308 struct r600_mmio_counter sdma;
309
310 /* CP_STAT */
311 struct r600_mmio_counter pfp;
312 struct r600_mmio_counter meq;
313 struct r600_mmio_counter me;
314 struct r600_mmio_counter surf_sync;
315 struct r600_mmio_counter cp_dma;
316 struct r600_mmio_counter scratch_ram;
317 } named;
318 unsigned array[sizeof(struct r600_mmio_counters_named) / sizeof(unsigned)];
319 };
320
321 struct r600_memory_object {
322 struct pipe_memory_object b;
323 struct pb_buffer *buf;
324 uint32_t stride;
325 uint32_t offset;
326 };
327
328 struct r600_common_screen {
329 struct pipe_screen b;
330 struct radeon_winsys *ws;
331 enum radeon_family family;
332 enum amd_gfx_level gfx_level;
333 struct radeon_info info;
334 uint64_t debug_flags;
335 bool has_cp_dma;
336 bool has_streamout;
337
338 struct disk_cache *disk_shader_cache;
339
340 struct slab_parent_pool pool_transfers;
341
342 /* Texture filter settings. */
343 int force_aniso; /* -1 = disabled */
344
345 /* Auxiliary context. Mainly used to initialize resources.
346 * It must be locked prior to using and flushed before unlocking. */
347 struct pipe_context *aux_context;
348 mtx_t aux_context_lock;
349
350 /* This must be in the screen, because UE4 uses one context for
351 * compilation and another one for rendering.
352 */
353 unsigned num_compilations;
354 /* Along with ST_DEBUG=precompile, this should show if applications
355 * are loading shaders on demand. This is a monotonic counter.
356 */
357 unsigned num_shaders_created;
358 unsigned num_shader_cache_hits;
359
360 /* GPU load thread. */
361 mtx_t gpu_load_mutex;
362 thrd_t gpu_load_thread;
363 bool gpu_load_thread_created;
364 union r600_mmio_counters mmio_counters;
365 volatile unsigned gpu_load_stop_thread; /* bool */
366
367 char renderer_string[100];
368
369 /* Performance counters. */
370 struct r600_perfcounters *perfcounters;
371
372 /* If pipe_screen wants to recompute and re-emit the framebuffer,
373 * sampler, and image states of all contexts, it should atomically
374 * increment this.
375 *
376 * Each context will compare this with its own last known value of
377 * the counter before drawing and re-emit the states accordingly.
378 */
379 unsigned dirty_tex_counter;
380
381 /* Atomically increment this counter when an existing texture's
382 * metadata is enabled or disabled in a way that requires changing
383 * contexts' compressed texture binding masks.
384 */
385 unsigned compressed_colortex_counter;
386
387 struct {
388 /* Context flags to set so that all writes from earlier jobs
389 * in the CP are seen by L2 clients.
390 */
391 unsigned cp_to_L2;
392
393 /* Context flags to set so that all writes from earlier jobs
394 * that end in L2 are seen by CP.
395 */
396 unsigned L2_to_cp;
397
398 /* Context flags to set so that all writes from earlier
399 * compute jobs are seen by L2 clients.
400 */
401 unsigned compute_to_L2;
402 } barrier_flags;
403
404 struct nir_shader_compiler_options nir_options;
405 struct nir_shader_compiler_options nir_options_fs;
406 };
407
408 /* This encapsulates a state or an operation which can emitted into the GPU
409 * command stream. */
410 struct r600_atom {
411 void (*emit)(struct r600_common_context *ctx, struct r600_atom *state);
412 unsigned num_dw;
413 unsigned short id;
414 };
415
416 struct r600_so_target {
417 struct pipe_stream_output_target b;
418
419 /* The buffer where BUFFER_FILLED_SIZE is stored. */
420 struct r600_resource *buf_filled_size;
421 unsigned buf_filled_size_offset;
422 bool buf_filled_size_valid;
423
424 unsigned stride_in_dw;
425 };
426
427 struct r600_streamout {
428 struct r600_atom begin_atom;
429 bool begin_emitted;
430 unsigned num_dw_for_end;
431
432 unsigned enabled_mask;
433 unsigned num_targets;
434 struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS];
435
436 unsigned append_bitmask;
437 bool suspended;
438
439 /* External state which comes from the vertex shader,
440 * it must be set explicitly when binding a shader. */
441 uint16_t *stride_in_dw;
442 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
443
444 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
445 unsigned hw_enabled_mask;
446
447 /* The state of VGT_STRMOUT_(CONFIG|EN). */
448 struct r600_atom enable_atom;
449 bool streamout_enabled;
450 bool prims_gen_query_enabled;
451 int num_prims_gen_queries;
452 };
453
454 struct r600_signed_scissor {
455 int minx;
456 int miny;
457 int maxx;
458 int maxy;
459 };
460
461 struct r600_scissors {
462 struct r600_atom atom;
463 unsigned dirty_mask;
464 struct pipe_scissor_state states[R600_MAX_VIEWPORTS];
465 };
466
467 struct r600_viewports {
468 struct r600_atom atom;
469 unsigned dirty_mask;
470 unsigned depth_range_dirty_mask;
471 struct pipe_viewport_state states[R600_MAX_VIEWPORTS];
472 struct r600_signed_scissor as_scissor[R600_MAX_VIEWPORTS];
473 };
474
475 struct r600_ring {
476 struct radeon_cmdbuf cs;
477 void (*flush)(void *ctx, unsigned flags,
478 struct pipe_fence_handle **fence);
479 };
480
481 /* Saved CS data for debugging features. */
482 struct radeon_saved_cs {
483 uint32_t *ib;
484 unsigned num_dw;
485
486 struct radeon_bo_list_item *bo_list;
487 unsigned bo_count;
488 };
489
490 struct r600_common_context {
491 struct pipe_context b; /* base class */
492
493 struct r600_common_screen *screen;
494 struct radeon_winsys *ws;
495 struct radeon_winsys_ctx *ctx;
496 enum radeon_family family;
497 enum amd_gfx_level gfx_level;
498 struct r600_ring gfx;
499 struct r600_ring dma;
500 struct pipe_fence_handle *last_gfx_fence;
501 struct pipe_fence_handle *last_sdma_fence;
502 struct r600_resource *eop_bug_scratch;
503 unsigned num_gfx_cs_flushes;
504 unsigned initial_gfx_cs_size;
505 unsigned last_dirty_tex_counter;
506 unsigned last_compressed_colortex_counter;
507 unsigned last_num_draw_calls;
508
509 struct threaded_context *tc;
510 struct u_suballocator allocator_zeroed_memory;
511 struct slab_child_pool pool_transfers;
512 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
513
514 /* Current unaccounted memory usage. */
515 uint64_t vram;
516 uint64_t gtt;
517
518 /* States. */
519 struct r600_streamout streamout;
520 struct r600_scissors scissors;
521 struct r600_viewports viewports;
522 bool scissor_enabled;
523 bool clip_halfz;
524 bool vs_writes_viewport_index;
525 bool vs_disables_clipping_viewport;
526
527 /* Additional context states. */
528 unsigned flags; /* flush flags */
529
530 /* Queries. */
531 /* Maintain the list of active queries for pausing between IBs. */
532 int num_occlusion_queries;
533 int num_perfect_occlusion_queries;
534 struct list_head active_queries;
535 unsigned num_cs_dw_queries_suspend;
536 /* Misc stats. */
537 unsigned num_draw_calls;
538 unsigned num_decompress_calls;
539 unsigned num_mrt_draw_calls;
540 unsigned num_prim_restart_calls;
541 unsigned num_spill_draw_calls;
542 unsigned num_compute_calls;
543 unsigned num_spill_compute_calls;
544 unsigned num_dma_calls;
545 unsigned num_cp_dma_calls;
546 unsigned num_vs_flushes;
547 unsigned num_ps_flushes;
548 unsigned num_cs_flushes;
549 unsigned num_cb_cache_flushes;
550 unsigned num_db_cache_flushes;
551 unsigned num_resident_handles;
552 uint64_t num_alloc_tex_transfer_bytes;
553
554 /* Render condition. */
555 struct r600_atom render_cond_atom;
556 struct pipe_query *render_cond;
557 unsigned render_cond_mode;
558 bool render_cond_invert;
559 bool render_cond_force_off; /* for u_blitter */
560
561 /* MSAA sample locations.
562 * The first index is the sample index.
563 * The second index is the coordinate: X, Y. */
564 float sample_locations_1x[1][2];
565 float sample_locations_2x[2][2];
566 float sample_locations_4x[4][2];
567 float sample_locations_8x[8][2];
568 float sample_locations_16x[16][2];
569
570 struct util_debug_callback debug;
571 struct pipe_device_reset_callback device_reset_callback;
572 struct u_log_context *log;
573
574 void *query_result_shader;
575
576 /* Copy one resource to another using async DMA. */
577 void (*dma_copy)(struct pipe_context *ctx,
578 struct pipe_resource *dst,
579 unsigned dst_level,
580 unsigned dst_x, unsigned dst_y, unsigned dst_z,
581 struct pipe_resource *src,
582 unsigned src_level,
583 const struct pipe_box *src_box);
584
585 void (*dma_clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
586 uint64_t offset, uint64_t size, unsigned value);
587
588 void (*clear_buffer)(struct pipe_context *ctx, struct pipe_resource *dst,
589 uint64_t offset, uint64_t size, unsigned value,
590 enum r600_coherency coher);
591
592 void (*blit_decompress_depth)(struct pipe_context *ctx,
593 struct r600_texture *texture,
594 struct r600_texture *staging,
595 unsigned first_level, unsigned last_level,
596 unsigned first_layer, unsigned last_layer,
597 unsigned first_sample, unsigned last_sample);
598
599 /* Reallocate the buffer and update all resource bindings where
600 * the buffer is bound, including all resource descriptors. */
601 void (*invalidate_buffer)(struct pipe_context *ctx, struct pipe_resource *buf);
602
603 /* Update all resource bindings where the buffer is bound, including
604 * all resource descriptors. This is invalidate_buffer without
605 * the invalidation. */
606 void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource *buf,
607 uint64_t old_gpu_address);
608
609 void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state *st);
610
611 /* This ensures there is enough space in the command stream. */
612 void (*need_gfx_cs_space)(struct pipe_context *ctx, unsigned num_dw,
613 bool include_draw_vbo);
614
615 void (*set_atom_dirty)(struct r600_common_context *ctx,
616 struct r600_atom *atom, bool dirty);
617
618 void (*check_vm_faults)(struct r600_common_context *ctx,
619 struct radeon_saved_cs *saved,
620 enum amd_ip_type ring);
621 };
622
623 /* r600_buffer_common.c */
624 bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
625 struct pb_buffer *buf,
626 unsigned usage);
627 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
628 struct r600_resource *resource,
629 unsigned usage);
630 void r600_buffer_subdata(struct pipe_context *ctx,
631 struct pipe_resource *buffer,
632 unsigned usage, unsigned offset,
633 unsigned size, const void *data);
634 void r600_init_resource_fields(struct r600_common_screen *rscreen,
635 struct r600_resource *res,
636 uint64_t size, unsigned alignment);
637 bool r600_alloc_resource(struct r600_common_screen *rscreen,
638 struct r600_resource *res);
639 void r600_buffer_destroy(struct pipe_screen *screen, struct pipe_resource *buf);
640 void r600_buffer_flush_region(struct pipe_context *ctx,
641 struct pipe_transfer *transfer,
642 const struct pipe_box *rel_box);
643 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
644 const struct pipe_resource *templ,
645 unsigned alignment);
646 struct pipe_resource * r600_aligned_buffer_create(struct pipe_screen *screen,
647 unsigned flags,
648 unsigned usage,
649 unsigned size,
650 unsigned alignment);
651 struct pipe_resource *
652 r600_buffer_from_user_memory(struct pipe_screen *screen,
653 const struct pipe_resource *templ,
654 void *user_memory);
655 void
656 r600_invalidate_resource(struct pipe_context *ctx,
657 struct pipe_resource *resource);
658 void r600_replace_buffer_storage(struct pipe_context *ctx,
659 struct pipe_resource *dst,
660 struct pipe_resource *src);
661 void *r600_buffer_transfer_map(struct pipe_context *ctx,
662 struct pipe_resource *resource,
663 unsigned level,
664 unsigned usage,
665 const struct pipe_box *box,
666 struct pipe_transfer **ptransfer);
667 void r600_buffer_transfer_unmap(struct pipe_context *ctx,
668 struct pipe_transfer *transfer);
669
670 /* r600_common_pipe.c */
671 void r600_gfx_write_event_eop(struct r600_common_context *ctx,
672 unsigned event, unsigned event_flags,
673 unsigned data_sel,
674 struct r600_resource *buf, uint64_t va,
675 uint32_t new_fence, unsigned query_type);
676 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
677 void r600_gfx_wait_fence(struct r600_common_context *ctx,
678 struct r600_resource *buf,
679 uint64_t va, uint32_t ref, uint32_t mask);
680 void r600_draw_rectangle(struct blitter_context *blitter,
681 void *vertex_elements_cso,
682 blitter_get_vs_func get_vs,
683 int x1, int y1, int x2, int y2,
684 float depth, unsigned num_instances,
685 enum blitter_attrib_type type,
686 const union blitter_attrib *attrib);
687 bool r600_common_screen_init(struct r600_common_screen *rscreen,
688 struct radeon_winsys *ws);
689 void r600_destroy_common_screen(struct r600_common_screen *rscreen);
690 void r600_preflush_suspend_features(struct r600_common_context *ctx);
691 void r600_postflush_resume_features(struct r600_common_context *ctx);
692 bool r600_common_context_init(struct r600_common_context *rctx,
693 struct r600_common_screen *rscreen,
694 unsigned context_flags);
695 void r600_common_context_cleanup(struct r600_common_context *rctx);
696 bool r600_can_dump_shader(struct r600_common_screen *rscreen,
697 unsigned processor);
698 bool r600_extra_shader_checks(struct r600_common_screen *rscreen,
699 unsigned processor);
700 void r600_screen_clear_buffer(struct r600_common_screen *rscreen, struct pipe_resource *dst,
701 uint64_t offset, uint64_t size, unsigned value);
702 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
703 const struct pipe_resource *templ);
704 const char *r600_get_llvm_processor_name(enum radeon_family family);
705 void r600_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
706 struct r600_resource *dst, struct r600_resource *src);
707 void radeon_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
708 struct radeon_saved_cs *saved, bool get_buffer_list);
709 void radeon_clear_saved_cs(struct radeon_saved_cs *saved);
710 bool r600_check_device_reset(struct r600_common_context *rctx);
711
712 /* r600_gpu_load.c */
713 void r600_gpu_load_kill_thread(struct r600_common_screen *rscreen);
714 uint64_t r600_begin_counter(struct r600_common_screen *rscreen, unsigned type);
715 unsigned r600_end_counter(struct r600_common_screen *rscreen, unsigned type,
716 uint64_t begin);
717
718 /* r600_perfcounters.c */
719 void r600_perfcounters_destroy(struct r600_common_screen *rscreen);
720
721 /* r600_query.c */
722 void r600_init_screen_query_functions(struct r600_common_screen *rscreen);
723 void r600_query_init(struct r600_common_context *rctx);
724 void r600_suspend_queries(struct r600_common_context *ctx);
725 void r600_resume_queries(struct r600_common_context *ctx);
726 void r600_query_fix_enabled_rb_mask(struct r600_common_screen *rscreen);
727
728 /* r600_streamout.c */
729 void r600_streamout_buffers_dirty(struct r600_common_context *rctx);
730 void r600_set_streamout_targets(struct pipe_context *ctx,
731 unsigned num_targets,
732 struct pipe_stream_output_target **targets,
733 const unsigned *offset);
734 void r600_emit_streamout_end(struct r600_common_context *rctx);
735 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
736 unsigned type, int diff);
737 void r600_streamout_init(struct r600_common_context *rctx);
738
739 /* r600_test_dma.c */
740 void r600_test_dma(struct r600_common_screen *rscreen);
741
742 /* r600_texture.c */
743 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
744 struct r600_texture *rdst,
745 unsigned dst_level, unsigned dstx,
746 unsigned dsty, unsigned dstz,
747 struct r600_texture *rsrc,
748 unsigned src_level,
749 const struct pipe_box *src_box);
750 void r600_texture_destroy(struct pipe_screen *screen, struct pipe_resource *ptex);
751 void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
752 struct r600_texture *rtex,
753 unsigned nr_samples,
754 struct r600_fmask_info *out);
755 void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
756 struct r600_texture *rtex,
757 struct r600_cmask_info *out);
758 bool r600_init_flushed_depth_texture(struct pipe_context *ctx,
759 struct pipe_resource *texture,
760 struct r600_texture **staging);
761 void r600_print_texture_info(struct r600_common_screen *rscreen,
762 struct r600_texture *rtex, struct u_log_context *log);
763 struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
764 const struct pipe_resource *templ);
765 struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe,
766 struct pipe_resource *texture,
767 const struct pipe_surface *templ,
768 unsigned width0, unsigned height0,
769 unsigned width, unsigned height);
770 unsigned r600_translate_colorswap(enum pipe_format format, bool do_endian_swap);
771 void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
772 struct pipe_framebuffer_state *fb,
773 struct r600_atom *fb_state,
774 unsigned *buffers, ubyte *dirty_cbufs,
775 const union pipe_color_union *color);
776 void r600_init_screen_texture_functions(struct r600_common_screen *rscreen);
777 void r600_init_context_texture_functions(struct r600_common_context *rctx);
778 void eg_resource_alloc_immed(struct r600_common_screen *rscreen,
779 struct r600_resource *res,
780 unsigned immed_size);
781 void *r600_texture_transfer_map(struct pipe_context *ctx,
782 struct pipe_resource *texture,
783 unsigned level,
784 unsigned usage,
785 const struct pipe_box *box,
786 struct pipe_transfer **ptransfer);
787 void r600_texture_transfer_unmap(struct pipe_context *ctx,
788 struct pipe_transfer* transfer);
789
790 /* r600_viewport.c */
791 void evergreen_apply_scissor_bug_workaround(struct r600_common_context *rctx,
792 struct pipe_scissor_state *scissor);
793 void r600_viewport_set_rast_deps(struct r600_common_context *rctx,
794 bool scissor_enable, bool clip_halfz);
795 void r600_update_vs_writes_viewport_index(struct r600_common_context *rctx,
796 struct tgsi_shader_info *info);
797 void r600_init_viewport_functions(struct r600_common_context *rctx);
798
799 /* cayman_msaa.c */
800 extern const uint32_t eg_sample_locs_2x[4];
801 extern const unsigned eg_max_dist_2x;
802 extern const uint32_t eg_sample_locs_4x[4];
803 extern const unsigned eg_max_dist_4x;
804 void cayman_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
805 unsigned sample_index, float *out_value);
806 void cayman_init_msaa(struct pipe_context *ctx);
807 void cayman_emit_msaa_state(struct radeon_cmdbuf *cs, int nr_samples,
808 int ps_iter_samples, int overrast_samples);
809
810
811 /* Inline helpers. */
812
r600_resource(struct pipe_resource * r)813 static inline struct r600_resource *r600_resource(struct pipe_resource *r)
814 {
815 return (struct r600_resource*)r;
816 }
817
818 static inline void
r600_resource_reference(struct r600_resource ** ptr,struct r600_resource * res)819 r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
820 {
821 pipe_resource_reference((struct pipe_resource **)ptr,
822 (struct pipe_resource *)res);
823 }
824
825 static inline void
r600_texture_reference(struct r600_texture ** ptr,struct r600_texture * res)826 r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
827 {
828 pipe_resource_reference((struct pipe_resource **)ptr, &res->resource.b.b);
829 }
830
831 static inline void
r600_context_add_resource_size(struct pipe_context * ctx,struct pipe_resource * r)832 r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r)
833 {
834 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
835 struct r600_resource *res = (struct r600_resource *)r;
836
837 if (res) {
838 /* Add memory usage for need_gfx_cs_space */
839 rctx->vram += res->vram_usage;
840 rctx->gtt += res->gart_usage;
841 }
842 }
843
r600_get_strmout_en(struct r600_common_context * rctx)844 static inline bool r600_get_strmout_en(struct r600_common_context *rctx)
845 {
846 return rctx->streamout.streamout_enabled ||
847 rctx->streamout.prims_gen_query_enabled;
848 }
849
850 #define SQ_TEX_XY_FILTER_POINT 0x00
851 #define SQ_TEX_XY_FILTER_BILINEAR 0x01
852 #define SQ_TEX_XY_FILTER_ANISO_POINT 0x02
853 #define SQ_TEX_XY_FILTER_ANISO_BILINEAR 0x03
854
eg_tex_filter(unsigned filter,unsigned max_aniso)855 static inline unsigned eg_tex_filter(unsigned filter, unsigned max_aniso)
856 {
857 if (filter == PIPE_TEX_FILTER_LINEAR)
858 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_BILINEAR
859 : SQ_TEX_XY_FILTER_BILINEAR;
860 else
861 return max_aniso > 1 ? SQ_TEX_XY_FILTER_ANISO_POINT
862 : SQ_TEX_XY_FILTER_POINT;
863 }
864
r600_tex_aniso_filter(unsigned filter)865 static inline unsigned r600_tex_aniso_filter(unsigned filter)
866 {
867 if (filter < 2)
868 return 0;
869 if (filter < 4)
870 return 1;
871 if (filter < 8)
872 return 2;
873 if (filter < 16)
874 return 3;
875 return 4;
876 }
877
r600_wavefront_size(enum radeon_family family)878 static inline unsigned r600_wavefront_size(enum radeon_family family)
879 {
880 switch (family) {
881 case CHIP_RV610:
882 case CHIP_RS780:
883 case CHIP_RV620:
884 case CHIP_RS880:
885 return 16;
886 case CHIP_RV630:
887 case CHIP_RV635:
888 case CHIP_RV730:
889 case CHIP_RV710:
890 case CHIP_PALM:
891 case CHIP_CEDAR:
892 return 32;
893 default:
894 return 64;
895 }
896 }
897
898 static inline unsigned
r600_get_sampler_view_priority(struct r600_resource * res)899 r600_get_sampler_view_priority(struct r600_resource *res)
900 {
901 if (res->b.b.target == PIPE_BUFFER)
902 return RADEON_PRIO_SAMPLER_BUFFER;
903
904 if (res->b.b.nr_samples > 1)
905 return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
906
907 return RADEON_PRIO_SAMPLER_TEXTURE;
908 }
909
910 static inline bool
r600_can_sample_zs(struct r600_texture * tex,bool stencil_sampler)911 r600_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
912 {
913 return (stencil_sampler && tex->can_sample_s) ||
914 (!stencil_sampler && tex->can_sample_z);
915 }
916
917 static inline bool
r600_htile_enabled(struct r600_texture * tex,unsigned level)918 r600_htile_enabled(struct r600_texture *tex, unsigned level)
919 {
920 return tex->htile_offset && level == 0;
921 }
922
923 #define COMPUTE_DBG(rscreen, fmt, args...) \
924 do { \
925 if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
926 } while (0);
927
928 #define R600_ERR(fmt, args...) \
929 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
930
931 /* For MSAA sample positions. */
932 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
933 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
934 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
935 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
936 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
937
S_FIXED(float value,unsigned frac_bits)938 static inline int S_FIXED(float value, unsigned frac_bits)
939 {
940 return value * (1 << frac_bits);
941 }
942
943 #endif
944