1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * Based on radeon_winsys.h which is:
6 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com>
7 * Copyright 2010 Marek Olšák <maraeo@gmail.com>
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * IN THE SOFTWARE.
27 */
28
29 #ifndef RADV_RADEON_WINSYS_H
30 #define RADV_RADEON_WINSYS_H
31
32 #include <stdbool.h>
33 #include <stdint.h>
34 #include <stdio.h>
35 #include <stdlib.h>
36 #include <string.h>
37 #include "util/u_math.h"
38 #include "util/u_memory.h"
39 #include <vulkan/vulkan.h>
40 #include "amd_family.h"
41
42 struct radeon_info;
43 struct ac_surf_info;
44 struct radeon_surf;
45 struct vk_sync_type;
46 struct vk_sync_wait;
47 struct vk_sync_signal;
48
49 enum radeon_bo_domain { /* bitfield */
50 RADEON_DOMAIN_GTT = 2,
51 RADEON_DOMAIN_VRAM = 4,
52 RADEON_DOMAIN_VRAM_GTT = RADEON_DOMAIN_VRAM | RADEON_DOMAIN_GTT,
53 RADEON_DOMAIN_GDS = 8,
54 RADEON_DOMAIN_OA = 16,
55 };
56
57 enum radeon_bo_flag { /* bitfield */
58 RADEON_FLAG_GTT_WC = (1 << 0),
59 RADEON_FLAG_CPU_ACCESS = (1 << 1),
60 RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
61 RADEON_FLAG_VIRTUAL = (1 << 3),
62 RADEON_FLAG_VA_UNCACHED = (1 << 4),
63 RADEON_FLAG_IMPLICIT_SYNC = (1 << 5),
64 RADEON_FLAG_NO_INTERPROCESS_SHARING = (1 << 6),
65 RADEON_FLAG_READ_ONLY = (1 << 7),
66 RADEON_FLAG_32BIT = (1 << 8),
67 RADEON_FLAG_PREFER_LOCAL_BO = (1 << 9),
68 RADEON_FLAG_ZERO_VRAM = (1 << 10),
69 RADEON_FLAG_REPLAYABLE = (1 << 11),
70 };
71
72 enum radeon_ctx_priority {
73 RADEON_CTX_PRIORITY_INVALID = -1,
74 RADEON_CTX_PRIORITY_LOW = 0,
75 RADEON_CTX_PRIORITY_MEDIUM,
76 RADEON_CTX_PRIORITY_HIGH,
77 RADEON_CTX_PRIORITY_REALTIME,
78 };
79
80 enum radeon_ctx_pstate {
81 RADEON_CTX_PSTATE_NONE = 0,
82 RADEON_CTX_PSTATE_STANDARD,
83 RADEON_CTX_PSTATE_MIN_SCLK,
84 RADEON_CTX_PSTATE_MIN_MCLK,
85 RADEON_CTX_PSTATE_PEAK,
86 };
87
88 enum radeon_value_id {
89 RADEON_ALLOCATED_VRAM,
90 RADEON_ALLOCATED_VRAM_VIS,
91 RADEON_ALLOCATED_GTT,
92 RADEON_TIMESTAMP,
93 RADEON_NUM_BYTES_MOVED,
94 RADEON_NUM_EVICTIONS,
95 RADEON_NUM_VRAM_CPU_PAGE_FAULTS,
96 RADEON_VRAM_USAGE,
97 RADEON_VRAM_VIS_USAGE,
98 RADEON_GTT_USAGE,
99 RADEON_GPU_TEMPERATURE,
100 RADEON_CURRENT_SCLK,
101 RADEON_CURRENT_MCLK,
102 };
103
104 struct radeon_cmdbuf {
105 unsigned cdw; /* Number of used dwords. */
106 unsigned max_dw; /* Maximum number of dwords. */
107 uint32_t *buf; /* The base pointer of the chunk. */
108 };
109
110 #define RADEON_SURF_TYPE_MASK 0xFF
111 #define RADEON_SURF_TYPE_SHIFT 0
112 #define RADEON_SURF_TYPE_1D 0
113 #define RADEON_SURF_TYPE_2D 1
114 #define RADEON_SURF_TYPE_3D 2
115 #define RADEON_SURF_TYPE_CUBEMAP 3
116 #define RADEON_SURF_TYPE_1D_ARRAY 4
117 #define RADEON_SURF_TYPE_2D_ARRAY 5
118 #define RADEON_SURF_MODE_MASK 0xFF
119 #define RADEON_SURF_MODE_SHIFT 8
120
121 #define RADEON_SURF_GET(v, field) \
122 (((v) >> RADEON_SURF_##field##_SHIFT) & RADEON_SURF_##field##_MASK)
123 #define RADEON_SURF_SET(v, field) (((v)&RADEON_SURF_##field##_MASK) << RADEON_SURF_##field##_SHIFT)
124 #define RADEON_SURF_CLR(v, field) \
125 ((v) & ~(RADEON_SURF_##field##_MASK << RADEON_SURF_##field##_SHIFT))
126
127 enum radeon_bo_layout {
128 RADEON_LAYOUT_LINEAR = 0,
129 RADEON_LAYOUT_TILED,
130 RADEON_LAYOUT_SQUARETILED,
131
132 RADEON_LAYOUT_UNKNOWN
133 };
134
135 /* Tiling info for display code, DRI sharing, and other data. */
136 struct radeon_bo_metadata {
137 /* Tiling flags describing the texture layout for display code
138 * and DRI sharing.
139 */
140 union {
141 struct {
142 enum radeon_bo_layout microtile;
143 enum radeon_bo_layout macrotile;
144 unsigned pipe_config;
145 unsigned bankw;
146 unsigned bankh;
147 unsigned tile_split;
148 unsigned mtilea;
149 unsigned num_banks;
150 unsigned stride;
151 bool scanout;
152 } legacy;
153
154 struct {
155 /* surface flags */
156 unsigned swizzle_mode : 5;
157 bool scanout;
158 uint32_t dcc_offset_256b;
159 uint32_t dcc_pitch_max;
160 bool dcc_independent_64b_blocks;
161 bool dcc_independent_128b_blocks;
162 unsigned dcc_max_compressed_block_size;
163 } gfx9;
164 } u;
165
166 /* Additional metadata associated with the buffer, in bytes.
167 * The maximum size is 64 * 4. This is opaque for the winsys & kernel.
168 * Supported by amdgpu only.
169 */
170 uint32_t size_metadata;
171 uint32_t metadata[64];
172 };
173
174 struct radeon_winsys_ctx;
175
176 struct radeon_winsys_bo {
177 uint64_t va;
178 bool is_local;
179 bool vram_no_cpu_access;
180 bool use_global_list;
181 enum radeon_bo_domain initial_domain;
182 };
183
184 struct radv_winsys_bo_list {
185 struct radeon_winsys_bo **bos;
186 unsigned count;
187 };
188
189 struct radv_winsys_submit_info {
190 enum amd_ip_type ip_type;
191 int queue_index;
192 unsigned cs_count;
193 struct radeon_cmdbuf **cs_array;
194 struct radeon_cmdbuf *initial_preamble_cs;
195 struct radeon_cmdbuf *continue_preamble_cs;
196 };
197
198 /* Kernel effectively allows 0-31. This sets some priorities for fixed
199 * functionality buffers */
200 enum {
201 RADV_BO_PRIORITY_APPLICATION_MAX = 28,
202
203 /* virtual buffers have 0 priority since the priority is not used. */
204 RADV_BO_PRIORITY_VIRTUAL = 0,
205
206 RADV_BO_PRIORITY_METADATA = 10,
207 /* This should be considerably lower than most of the stuff below,
208 * but how much lower is hard to say since we don't know application
209 * assignments. Put it pretty high since it is GTT anyway. */
210 RADV_BO_PRIORITY_QUERY_POOL = 29,
211
212 RADV_BO_PRIORITY_DESCRIPTOR = 30,
213 RADV_BO_PRIORITY_UPLOAD_BUFFER = 30,
214 RADV_BO_PRIORITY_FENCE = 30,
215 RADV_BO_PRIORITY_SHADER = 31,
216 RADV_BO_PRIORITY_SCRATCH = 31,
217 RADV_BO_PRIORITY_CS = 31,
218 };
219
220 struct radeon_winsys {
221 void (*destroy)(struct radeon_winsys *ws);
222
223 void (*query_info)(struct radeon_winsys *ws, struct radeon_info *info);
224
225 uint64_t (*query_value)(struct radeon_winsys *ws, enum radeon_value_id value);
226
227 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers,
228 uint32_t *out);
229
230 const char *(*get_chip_name)(struct radeon_winsys *ws);
231
232 VkResult (*buffer_create)(struct radeon_winsys *ws, uint64_t size, unsigned alignment,
233 enum radeon_bo_domain domain, enum radeon_bo_flag flags,
234 unsigned priority, uint64_t address, struct radeon_winsys_bo **out_bo);
235
236 void (*buffer_destroy)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo);
237 void *(*buffer_map)(struct radeon_winsys_bo *bo);
238
239 VkResult (*buffer_from_ptr)(struct radeon_winsys *ws, void *pointer, uint64_t size,
240 unsigned priority, struct radeon_winsys_bo **out_bo);
241
242 VkResult (*buffer_from_fd)(struct radeon_winsys *ws, int fd, unsigned priority,
243 struct radeon_winsys_bo **out_bo, uint64_t *alloc_size);
244
245 bool (*buffer_get_fd)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, int *fd);
246
247 bool (*buffer_get_flags_from_fd)(struct radeon_winsys *ws, int fd,
248 enum radeon_bo_domain *domains, enum radeon_bo_flag *flags);
249
250 void (*buffer_unmap)(struct radeon_winsys_bo *bo);
251
252 void (*buffer_set_metadata)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo,
253 struct radeon_bo_metadata *md);
254 void (*buffer_get_metadata)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo,
255 struct radeon_bo_metadata *md);
256
257 VkResult (*buffer_virtual_bind)(struct radeon_winsys *ws, struct radeon_winsys_bo *parent,
258 uint64_t offset, uint64_t size, struct radeon_winsys_bo *bo,
259 uint64_t bo_offset);
260
261 VkResult (*buffer_make_resident)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo,
262 bool resident);
263
264 VkResult (*ctx_create)(struct radeon_winsys *ws, enum radeon_ctx_priority priority,
265 struct radeon_winsys_ctx **ctx);
266 void (*ctx_destroy)(struct radeon_winsys_ctx *ctx);
267
268 bool (*ctx_wait_idle)(struct radeon_winsys_ctx *ctx, enum amd_ip_type amd_ip_type, int ring_index);
269
270 int (*ctx_set_pstate)(struct radeon_winsys_ctx *ctx, uint32_t pstate);
271
272 enum radeon_bo_domain (*cs_domain)(const struct radeon_winsys *ws);
273
274 struct radeon_cmdbuf *(*cs_create)(struct radeon_winsys *ws, enum amd_ip_type amd_ip_type);
275
276 void (*cs_destroy)(struct radeon_cmdbuf *cs);
277
278 void (*cs_reset)(struct radeon_cmdbuf *cs);
279
280 VkResult (*cs_finalize)(struct radeon_cmdbuf *cs);
281
282 void (*cs_grow)(struct radeon_cmdbuf *cs, size_t min_size);
283
284 VkResult (*cs_submit)(struct radeon_winsys_ctx *ctx, uint32_t submit_count,
285 const struct radv_winsys_submit_info *submits, uint32_t wait_count,
286 const struct vk_sync_wait *waits, uint32_t signal_count,
287 const struct vk_sync_signal *signals, bool can_patch);
288
289 void (*cs_add_buffer)(struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo);
290
291 void (*cs_add_buffers)(struct radeon_cmdbuf *to, struct radeon_cmdbuf *from);
292
293 void (*cs_execute_secondary)(struct radeon_cmdbuf *parent, struct radeon_cmdbuf *child,
294 bool allow_ib2);
295
296 void (*cs_dump)(struct radeon_cmdbuf *cs, FILE *file, const int *trace_ids, int trace_id_count);
297
298 void (*dump_bo_ranges)(struct radeon_winsys *ws, FILE *file);
299
300 void (*dump_bo_log)(struct radeon_winsys *ws, FILE *file);
301
302 int (*surface_init)(struct radeon_winsys *ws, const struct ac_surf_info *surf_info,
303 struct radeon_surf *surf);
304
305 int (*get_fd)(struct radeon_winsys *ws);
306
307 const struct vk_sync_type *const *(*get_sync_types)(struct radeon_winsys *ws);
308 };
309
310 static inline void
radeon_emit(struct radeon_cmdbuf * cs,uint32_t value)311 radeon_emit(struct radeon_cmdbuf *cs, uint32_t value)
312 {
313 cs->buf[cs->cdw++] = value;
314 }
315
316 static inline void
radeon_emit_array(struct radeon_cmdbuf * cs,const uint32_t * values,unsigned count)317 radeon_emit_array(struct radeon_cmdbuf *cs, const uint32_t *values, unsigned count)
318 {
319 memcpy(cs->buf + cs->cdw, values, count * 4);
320 cs->cdw += count;
321 }
322
323 static inline uint64_t
radv_buffer_get_va(struct radeon_winsys_bo * bo)324 radv_buffer_get_va(struct radeon_winsys_bo *bo)
325 {
326 return bo->va;
327 }
328
329 static inline void
radv_cs_add_buffer(struct radeon_winsys * ws,struct radeon_cmdbuf * cs,struct radeon_winsys_bo * bo)330 radv_cs_add_buffer(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, struct radeon_winsys_bo *bo)
331 {
332 if (bo->use_global_list)
333 return;
334
335 ws->cs_add_buffer(cs, bo);
336 }
337
338 #endif /* RADV_RADEON_WINSYS_H */
339