| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonBitTracker.cpp | 92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
125 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
133 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
283 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
290 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
291 -> BT::RegisterCell { in evaluate()
300 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
335 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
351 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
358 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() local
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| D | HexagonConstPropagation.cpp | 720 LatticeCell RC = Cells.get(DefR.Reg); in visitNonBranch() local
1082 LatticeCell &RC) { in getCell()
1392 LatticeCell RC; in evaluateANDrr() local
1408 LatticeCell RC; in evaluateANDri() local
1459 LatticeCell RC; in evaluateORrr() local
1475 LatticeCell RC; in evaluateORri() local
1524 LatticeCell RC; in evaluateXORrr() local
1943 LatticeCell RC; in evaluate() local
1965 LatticeCell RC; in evaluate() local
1999 LatticeCell RC = Outputs.get(DefR.Reg); in evaluate() local
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| D | HexagonBitSimplify.cpp | 330 bool HexagonBitSimplify::isZero(const BitTracker::RegisterCell &RC, in isZero()
339 bool HexagonBitSimplify::getConst(const BitTracker::RegisterCell &RC, in getConst()
407 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg); in getSubregMask() local
899 auto *RC = MRI.getRegClass(RR.Reg); in getFinalVRegClass() local
905 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void { in getFinalVRegClass()
1261 const TargetRegisterClass *RC = HBS::getFinalVRegClass(RR, MRI); in computeUsedBits() local
1411 unsigned ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C, in genTfrConst()
1549 const BitTracker::RegisterCell &RC = BT.lookup(R); in findMatch() local
1686 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); in propagateRegCopy() local
1696 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg); in propagateRegCopy() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 73 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
89 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
96 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
106 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
122 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
130 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
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| D | TargetRegisterInfo.h | 118 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
123 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
130 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
135 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
271 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
277 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
283 unsigned getSpillAlignment(const TargetRegisterClass &RC) const { in getSpillAlignment()
288 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
297 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
301 vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const { in legalclasstypes_end()
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| D | ExecutionDomainFix.h | 111 const TargetRegisterClass *const RC; variable
130 ExecutionDomainFix(char &PassID, const TargetRegisterClass &RC) in ExecutionDomainFix()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyExplicitLocals.cpp | 83 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode()
100 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode()
117 static unsigned getLocalSetOpcode(const TargetRegisterClass *RC) { in getLocalSetOpcode()
134 static unsigned getLocalTeeOpcode(const TargetRegisterClass *RC) { in getLocalTeeOpcode()
151 static MVT typeForRegClass(const TargetRegisterClass *RC) { in typeForRegClass()
243 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
278 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
353 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 129 bool isSGPRClass(const TargetRegisterClass *RC) const { in isSGPRClass()
139 const TargetRegisterClass *RC; in isSGPRReg() local
148 bool isAGPRClass(const TargetRegisterClass *RC) const { in isAGPRClass()
159 bool hasVectorRegisters(const TargetRegisterClass *RC) const { in hasVectorRegisters()
216 isDivergentRegClass(const TargetRegisterClass *RC) const override { in isDivergentRegClass()
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| D | SILowerSGPRSpills.cpp | 103 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSaves() local
136 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRRestores() local
209 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegs() local
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| D | SIRegisterInfo.cpp | 637 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg); in buildSpillLoadStore() local
775 const TargetRegisterClass *RC = getPhysRegClass(SuperReg); in spillSGPR() local
880 const TargetRegisterClass *RC = getPhysRegClass(SuperReg); in restoreSGPR() local
1394 const TargetRegisterClass *RC, unsigned SubIdx) const { in getSubRegClass() argument
1495 const TargetRegisterClass *RC, in findUnusedRegister()
1504 ArrayRef<int16_t> SIRegisterInfo::getRegSplitParts(const TargetRegisterClass *RC, in getRegSplitParts()
1689 const TargetRegisterClass * RC = getRegClassForReg(MRI, Reg); in isVGPR() local
1696 const TargetRegisterClass * RC = getRegClassForReg(MRI, Reg); in isAGPR() local
1722 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
1821 const TargetRegisterClass *RC = RCOrRB.get<const TargetRegisterClass*>(); in getConstrainedRegClassForOperand() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/ |
| D | XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
56 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
69 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsMachineFunction.cpp | 72 const TargetRegisterClass *RC; in initGlobalBaseReg() local
153 const TargetRegisterClass &RC = in createEhDataRegsFI() local
168 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI() local
192 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
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| D | MipsSEFrameLowering.cpp | 173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
383 const TargetRegisterClass *RC = in expandExtractElementF64() local
421 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
719 const TargetRegisterClass *RC = in emitEpilogue() local
834 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
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| D | MipsInstrInfo.h | 115 const TargetRegisterClass *RC, in storeRegToStackSlot()
123 const TargetRegisterClass *RC, in loadRegFromStackSlot()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 455 const TargetRegisterClass *RC, in PPCEmitLoad()
612 const TargetRegisterClass *RC = in SelectLoad() local
629 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
990 auto RC = MRI.getRegClass(SrcReg); in SelectFPTrunc() local
1053 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1132 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1176 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1227 auto RC = MRI.getRegClass(SrcReg); in SelectFPToI() local
1281 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1443 const TargetRegisterClass *RC = in processCallArgs() local
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| /third_party/cef/tools/ |
| D | msvs_env.bat | 9 set RC= variable
66 endlocal & set RC=%ERRORLEVEL% variable
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | LiveStacks.cpp | 57 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { in getOrCreateInterval()
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot); in print() local
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| D | SwiftErrorValueTracking.cpp | 36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVReg() local
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateVRegDefAt() local
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createEntriesInEntryBlock() local
241 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateVRegs() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXRegisterInfo.cpp | 28 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { in getNVPTXRegClassName()
72 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { in getNVPTXRegClassStr()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBank.cpp | 34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify() local
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 59 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue() local
360 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta() local
364 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta() local
478 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | IRBuilder.h | 1168 auto *RC = dyn_cast<Constant>(R); in foldConstant() local
1214 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1231 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1248 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1265 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1279 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1303 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1324 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1344 if (auto *RC = dyn_cast<Constant>(RHS)) variable
1362 if (auto *RC = dyn_cast<Constant>(RHS)) { variable
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb1InstrInfo.cpp | 80 const TargetRegisterClass *RC, in storeRegToStackSlot()
108 const TargetRegisterClass *RC, in loadRegFromStackSlot()
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| D | ARMFastISel.cpp | 302 const TargetRegisterClass *RC, in fastEmitInst_r()
324 const TargetRegisterClass *RC, in fastEmitInst_rr()
352 const TargetRegisterClass *RC, in fastEmitInst_ri()
378 const TargetRegisterClass *RC, in fastEmitInst_i()
473 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt() local
489 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : in ARMMaterializeInt() local
546 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass in ARMMaterializeGV() local
675 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca() local
849 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass in ARMSimplifyAddress() local
921 const TargetRegisterClass *RC; in ARMEmitLoad() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64SIMDInstrOpt.cpp | 90 const TargetRegisterClass RC; member
93 #define RuleST2(OpcOrg, OpcR0, OpcR1, OpcR2, RC) \ argument
96 OpcR7, OpcR8, OpcR9, RC) \ argument
352 const TargetRegisterClass *RC = &AArch64::FPR128RegClass; in optimizeVectElement() local
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