1 /* 2 * Copyright (c) 2023 Huawei Device Co., Ltd. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #ifndef DFX_REGS_DEFINE_H 16 #define DFX_REGS_DEFINE_H 17 18 #include <cstdint> 19 20 namespace OHOS { 21 namespace HiviewDFX { 22 const int REGS_PRINT_LEN_SPECIAL = 128; 23 const int REGS_PRINT_LEN_ARM = 256; 24 const int REGS_PRINT_LEN_ARM64 = 1024; 25 const int REGS_PRINT_LEN_X86 = 512; 26 27 enum RegisterArm : uint16_t { 28 REG_ARM_R0 = 0, 29 REG_ARM_R1, 30 REG_ARM_R2, 31 REG_ARM_R3, 32 REG_ARM_R4, 33 REG_ARM_R5, 34 REG_ARM_R6, 35 REG_ARM_R7, 36 REG_ARM_R8, 37 REG_ARM_R9, 38 REG_ARM_R10, 39 REG_ARM_R11, 40 REG_ARM_R12, 41 REG_ARM_R13, 42 REG_ARM_R14, 43 REG_ARM_R15, 44 REG_ARM_LAST, 45 46 REG_ARM_FP = REG_ARM_R11, 47 REG_ARM_IP = REG_ARM_R12, 48 REG_ARM_SP = REG_ARM_R13, 49 REG_ARM_LR = REG_ARM_R14, 50 REG_ARM_PC = REG_ARM_R15, 51 }; 52 53 enum RegisterArm64 : uint16_t { 54 REG_AARCH64_X0 = 0, 55 REG_AARCH64_X1, 56 REG_AARCH64_X2, 57 REG_AARCH64_X3, 58 REG_AARCH64_X4, 59 REG_AARCH64_X5, 60 REG_AARCH64_X6, 61 REG_AARCH64_X7, 62 REG_AARCH64_X8, 63 REG_AARCH64_X9, 64 REG_AARCH64_X10, 65 REG_AARCH64_X11, 66 REG_AARCH64_X12, 67 REG_AARCH64_X13, 68 REG_AARCH64_X14, 69 REG_AARCH64_X15, 70 REG_AARCH64_X16, 71 REG_AARCH64_X17, 72 REG_AARCH64_X18, 73 REG_AARCH64_X19, 74 REG_AARCH64_X20, 75 REG_AARCH64_X21, 76 REG_AARCH64_X22, 77 REG_AARCH64_X23, 78 REG_AARCH64_X24, 79 REG_AARCH64_X25, 80 REG_AARCH64_X26, 81 REG_AARCH64_X27, 82 REG_AARCH64_X28, 83 REG_AARCH64_X29, 84 REG_AARCH64_X30, 85 REG_AARCH64_X31, 86 REG_AARCH64_PC, 87 REG_AARCH64_PSTATE, 88 REG_AARCH64_LAST, 89 90 REG_AARCH64_SP = REG_AARCH64_X31, 91 REG_AARCH64_LR = REG_AARCH64_X30, 92 REG_AARCH64_FP = REG_AARCH64_X29, 93 }; 94 95 enum RegisterX86 : uint16_t { 96 REG_X86_EAX = 0, 97 REG_X86_EDX = 1, 98 REG_X86_ECX = 2, 99 REG_X86_EBX = 3, 100 REG_X86_ESI = 4, 101 REG_X86_EDI = 5, 102 REG_X86_EBP = 6, 103 REG_X86_ESP = 7, 104 REG_X86_EIP = 8, 105 REG_X86_LAST, 106 107 REG_X86_SP = REG_X86_ESP, 108 REG_X86_PC = REG_X86_EIP, 109 }; 110 111 enum RegisterX86_64 : uint16_t { 112 REG_X86_64_RAX = 0, 113 REG_X86_64_RDX = 1, 114 REG_X86_64_RCX = 2, 115 REG_X86_64_RBX = 3, 116 REG_X86_64_RSI = 4, 117 REG_X86_64_RDI = 5, 118 REG_X86_64_RBP = 6, 119 REG_X86_64_RSP = 7, 120 REG_X86_64_R8 = 8, 121 REG_X86_64_R9 = 9, 122 REG_X86_64_R10 = 10, 123 REG_X86_64_R11 = 11, 124 REG_X86_64_R12 = 12, 125 REG_X86_64_R13 = 13, 126 REG_X86_64_R14 = 14, 127 REG_X86_64_R15 = 15, 128 REG_X86_64_RIP = 16, 129 REG_X86_64_LAST, 130 131 REG_X86_64_SP = REG_X86_64_RSP, 132 REG_X86_64_PC = REG_X86_64_RIP, 133 }; 134 } // namespace HiviewDFX 135 } // namespace OHOS 136 #endif 137