1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7 #ifndef _ROCKCHIP_DRM_VOP_H
8 #define _ROCKCHIP_DRM_VOP_H
9
10 #include <drm/drm_plane.h>
11 #include <drm/drm_modes.h>
12
13 /*
14 * major: IP major version, used for IP structure
15 * minor: big feature change under same structure
16 */
17 #define VOP_VERSION(major, minor) ((major) << 8 | (minor))
18 #define VOP_MAJOR(version) ((version) >> 8)
19 #define VOP_MINOR(version) ((version)&0xff)
20
21 #define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
22 #define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
23
24 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
25 #define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
26 #define ROCKCHIP_OUTPUT_DATA_SWAP BIT(2)
27 /* MIPI DSI DataStream(cmd) mode on rk3588 */
28 #define ROCKCHIP_OUTPUT_MIPI_DS_MODE BIT(3)
29
30 #define AFBDC_FMT_RGB565 0x0
31 #define AFBDC_FMT_U8U8U8U8 0x5
32 #define AFBDC_FMT_U8U8U8 0x4
33
34 #define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
35 #define VOP_FEATURE_INTERNAL_RGB BIT(1)
36 #define VOP_FEATURE_ALPHA_SCALE BIT(2)
37 #define VOP_FEATURE_HDR10 BIT(3)
38 #define VOP_FEATURE_NEXT_HDR BIT(4)
39 /* a feature to splice two windows and two vps to support resolution > 4096 */
40 #define VOP_FEATURE_SPLICE BIT(5)
41 #define VOP_FEATURE_OVERSCAN BIT(6)
42
43 #define VOP_FEATURE_OUTPUT_10BIT VOP_FEATURE_OUTPUT_RGB10
44
45 #define WIN_FEATURE_HDR2SDR BIT(0)
46 #define WIN_FEATURE_SDR2HDR BIT(1)
47 #define WIN_FEATURE_PRE_OVERLAY BIT(2)
48 #define WIN_FEATURE_AFBDC BIT(3)
49 #define WIN_FEATURE_CLUSTER_MAIN BIT(4)
50 #define WIN_FEATURE_CLUSTER_SUB BIT(5)
51 /* Left win in splice mode */
52 #define WIN_FEATURE_SPLICE_LEFT BIT(6)
53 /* a mirror win can only get fb address
54 * from source win:
55 * Cluster1---->Cluster0
56 * Esmart1 ---->Esmart0
57 * Smart1 ---->Smart0
58 * This is a feather on rk3566
59 */
60 #define WIN_FEATURE_MIRROR BIT(6)
61 #define WIN_FEATURE_MULTI_AREA BIT(7)
62
63 #define VOP2_SOC_VARIANT 4
64
65 #define ROCKCHIP_DSC_PPS_SIZE_BYTE 88
66
67 enum vop_win_phy_id {
68 ROCKCHIP_VOP_WIN0 = 0,
69 ROCKCHIP_VOP_WIN1,
70 ROCKCHIP_VOP_WIN2,
71 ROCKCHIP_VOP_WIN3,
72 ROCKCHIP_VOP_PHY_ID_INVALID = -1,
73 };
74
75 enum bcsh_out_mode {
76 BCSH_OUT_MODE_BLACK,
77 BCSH_OUT_MODE_BLUE,
78 BCSH_OUT_MODE_COLOR_BAR,
79 BCSH_OUT_MODE_NORMAL_VIDEO,
80 };
81
82 enum cabc_stage_mode { LAST_FRAME_PWM_VAL = 0x0, CUR_FRAME_PWM_VAL = 0x1, STAGE_BY_STAGE = 0x2 };
83
84 enum cabc_stage_up_mode {
85 MUL_MODE,
86 ADD_MODE,
87 };
88
89 /*
90 * the delay number of a window in different mode.
91 */
92 enum vop2_win_dly_mode {
93 VOP2_DLY_MODE_DEFAULT, /**< default mode */
94 VOP2_DLY_MODE_HISO_S, /** HDR in SDR out mode, as a SDR window */
95 VOP2_DLY_MODE_HIHO_H, /** HDR in HDR out mode, as a HDR window */
96 VOP2_DLY_MODE_MAX,
97 };
98
99 /*
100 * vop2 internal power domain id,
101 * should be all none zero, 0 will be
102 * treat as invalid;
103 */
104 #define VOP2_PD_CLUSTER0 BIT(0)
105 #define VOP2_PD_CLUSTER1 BIT(1)
106 #define VOP2_PD_CLUSTER2 BIT(2)
107 #define VOP2_PD_CLUSTER3 BIT(3)
108 #define VOP2_PD_DSC_8K BIT(5)
109 #define VOP2_PD_DSC_4K BIT(6)
110 #define VOP2_PD_ESMART0 BIT(7)
111
112 /*
113 * vop2 submem power gate,
114 * should be all none zero, 0 will be
115 * treat as invalid;
116 */
117 #define VOP2_MEM_PG_VP0 BIT(0)
118 #define VOP2_MEM_PG_VP1 BIT(1)
119 #define VOP2_MEM_PG_VP2 BIT(2)
120 #define VOP2_MEM_PG_VP3 BIT(3)
121 #define VOP2_MEM_PG_DB0 BIT(4)
122 #define VOP2_MEM_PG_DB1 BIT(5)
123 #define VOP2_MEM_PG_DB2 BIT(6)
124 #define VOP2_MEM_PG_WB BIT(7)
125
126 #define DSP_BG_SWAP 0x1
127 #define DSP_RB_SWAP 0x2
128 #define DSP_RG_SWAP 0x4
129 #define DSP_DELTA_SWAP 0x8
130
131 enum vop_csc_format {
132 CSC_BT601L,
133 CSC_BT709L,
134 CSC_BT601F,
135 CSC_BT2020,
136 };
137
138 enum vop_csc_mode {
139 CSC_RGB,
140 CSC_YUV,
141 };
142
143 enum vop_data_format {
144 VOP_FMT_ARGB8888 = 0,
145 VOP_FMT_RGB888,
146 VOP_FMT_RGB565 = 2,
147 VOP_FMT_YUYV = 2,
148 VOP_FMT_YUV420SP = 4,
149 VOP_FMT_YUV422SP,
150 VOP_FMT_YUV444SP,
151 };
152
153 enum vop_dsc_interface_mode {
154 VOP_DSC_IF_DISABLE = 0,
155 VOP_DSC_IF_HDMI = 1,
156 VOP_DSC_IF_MIPI_DS_MODE = 2,
157 VOP_DSC_IF_MIPI_VIDEO_MODE = 3,
158 };
159
160 struct vop_reg_data {
161 uint32_t offset;
162 uint32_t value;
163 };
164
165 struct vop_reg {
166 uint32_t mask;
167 uint32_t offset : 17;
168 uint32_t shift : 5;
169 uint32_t begin_minor : 4;
170 uint32_t end_minor : 4;
171 uint32_t reserved : 2;
172 uint32_t major : 3;
173 uint32_t write_mask : 1;
174 };
175
176 struct vop_csc {
177 struct vop_reg y2r_en;
178 struct vop_reg r2r_en;
179 struct vop_reg r2y_en;
180 struct vop_reg csc_mode;
181
182 uint32_t y2r_offset;
183 uint32_t r2r_offset;
184 uint32_t r2y_offset;
185 };
186
187 struct vop_rect {
188 int width;
189 int height;
190 };
191
192 struct vop_ctrl {
193 struct vop_reg version;
194 struct vop_reg standby;
195 struct vop_reg dma_stop;
196 struct vop_reg axi_outstanding_max_num;
197 struct vop_reg axi_max_outstanding_en;
198 struct vop_reg htotal_pw;
199 struct vop_reg hact_st_end;
200 struct vop_reg vtotal_pw;
201 struct vop_reg vact_st_end;
202 struct vop_reg vact_st_end_f1;
203 struct vop_reg vs_st_end_f1;
204 struct vop_reg hpost_st_end;
205 struct vop_reg vpost_st_end;
206 struct vop_reg vpost_st_end_f1;
207 struct vop_reg post_scl_factor;
208 struct vop_reg post_scl_ctrl;
209 struct vop_reg dsp_interlace;
210 struct vop_reg global_regdone_en;
211 struct vop_reg auto_gate_en;
212 struct vop_reg post_lb_mode;
213 struct vop_reg dsp_layer_sel;
214 struct vop_reg overlay_mode;
215 struct vop_reg core_dclk_div;
216 struct vop_reg dclk_ddr;
217 struct vop_reg p2i_en;
218 struct vop_reg hdmi_dclk_out_en;
219 struct vop_reg rgb_en;
220 struct vop_reg lvds_en;
221 struct vop_reg edp_en;
222 struct vop_reg hdmi_en;
223 struct vop_reg mipi_en;
224 struct vop_reg data01_swap;
225 struct vop_reg mipi_dual_channel_en;
226 struct vop_reg dp_en;
227 struct vop_reg dclk_pol;
228 struct vop_reg pin_pol;
229 struct vop_reg rgb_dclk_pol;
230 struct vop_reg rgb_pin_pol;
231 struct vop_reg lvds_dclk_pol;
232 struct vop_reg lvds_pin_pol;
233 struct vop_reg hdmi_dclk_pol;
234 struct vop_reg hdmi_pin_pol;
235 struct vop_reg edp_dclk_pol;
236 struct vop_reg edp_pin_pol;
237 struct vop_reg mipi_dclk_pol;
238 struct vop_reg mipi_pin_pol;
239 struct vop_reg dp_dclk_pol;
240 struct vop_reg dp_pin_pol;
241 struct vop_reg dither_down_sel;
242 struct vop_reg dither_down_mode;
243 struct vop_reg dither_down_en;
244 struct vop_reg pre_dither_down_en;
245 struct vop_reg dither_up_en;
246
247 struct vop_reg sw_dac_sel;
248 struct vop_reg tve_sw_mode;
249 struct vop_reg tve_dclk_pol;
250 struct vop_reg tve_dclk_en;
251 struct vop_reg sw_genlock;
252 struct vop_reg sw_uv_offset_en;
253 struct vop_reg dsp_out_yuv;
254 struct vop_reg dsp_data_swap;
255 struct vop_reg yuv_clip;
256 struct vop_reg dsp_ccir656_avg;
257 struct vop_reg dsp_black;
258 struct vop_reg dsp_blank;
259 struct vop_reg dsp_outzero;
260 struct vop_reg update_gamma_lut;
261 struct vop_reg lut_buffer_index;
262 struct vop_reg dsp_lut_en;
263
264 struct vop_reg out_mode;
265
266 struct vop_reg xmirror;
267 struct vop_reg ymirror;
268 struct vop_reg dsp_background;
269
270 /* AFBDC */
271 struct vop_reg afbdc_en;
272 struct vop_reg afbdc_sel;
273 struct vop_reg afbdc_format;
274 struct vop_reg afbdc_hreg_block_split;
275 struct vop_reg afbdc_pic_size;
276 struct vop_reg afbdc_hdr_ptr;
277 struct vop_reg afbdc_rstn;
278 struct vop_reg afbdc_pic_vir_width;
279 struct vop_reg afbdc_pic_offset;
280 struct vop_reg afbdc_axi_ctrl;
281
282 /* BCSH */
283 struct vop_reg bcsh_brightness;
284 struct vop_reg bcsh_contrast;
285 struct vop_reg bcsh_sat_con;
286 struct vop_reg bcsh_sin_hue;
287 struct vop_reg bcsh_cos_hue;
288 struct vop_reg bcsh_r2y_csc_mode;
289 struct vop_reg bcsh_r2y_en;
290 struct vop_reg bcsh_y2r_csc_mode;
291 struct vop_reg bcsh_y2r_en;
292 struct vop_reg bcsh_color_bar;
293 struct vop_reg bcsh_out_mode;
294 struct vop_reg bcsh_en;
295
296 /* HDR */
297 struct vop_reg level2_overlay_en;
298 struct vop_reg alpha_hard_calc;
299 struct vop_reg hdr2sdr_en;
300 struct vop_reg hdr2sdr_en_win0_csc;
301 struct vop_reg hdr2sdr_src_min;
302 struct vop_reg hdr2sdr_src_max;
303 struct vop_reg hdr2sdr_normfaceetf;
304 struct vop_reg hdr2sdr_dst_min;
305 struct vop_reg hdr2sdr_dst_max;
306 struct vop_reg hdr2sdr_normfacgamma;
307
308 struct vop_reg bt1886eotf_pre_conv_en;
309 struct vop_reg rgb2rgb_pre_conv_en;
310 struct vop_reg rgb2rgb_pre_conv_mode;
311 struct vop_reg st2084oetf_pre_conv_en;
312 struct vop_reg bt1886eotf_post_conv_en;
313 struct vop_reg rgb2rgb_post_conv_en;
314 struct vop_reg rgb2rgb_post_conv_mode;
315 struct vop_reg st2084oetf_post_conv_en;
316 struct vop_reg win_csc_mode_sel;
317
318 /* MCU OUTPUT */
319 struct vop_reg mcu_pix_total;
320 struct vop_reg mcu_cs_pst;
321 struct vop_reg mcu_cs_pend;
322 struct vop_reg mcu_rw_pst;
323 struct vop_reg mcu_rw_pend;
324 struct vop_reg mcu_clk_sel;
325 struct vop_reg mcu_hold_mode;
326 struct vop_reg mcu_frame_st;
327 struct vop_reg mcu_rs;
328 struct vop_reg mcu_bypass;
329 struct vop_reg mcu_type;
330 struct vop_reg mcu_rw_bypass_port;
331
332 /* bt1120 */
333 struct vop_reg bt1120_yc_swap;
334 struct vop_reg bt1120_en;
335
336 struct vop_reg reg_done_frm;
337 struct vop_reg cfg_done;
338 };
339
340 struct vop_intr {
341 const int *intrs;
342 uint32_t nintrs;
343 struct vop_reg line_flag_num[2];
344 struct vop_reg enable;
345 struct vop_reg clear;
346 struct vop_reg status;
347 };
348
349 struct vop_scl_extension {
350 struct vop_reg cbcr_vsd_mode;
351 struct vop_reg cbcr_vsu_mode;
352 struct vop_reg cbcr_hsd_mode;
353 struct vop_reg cbcr_ver_scl_mode;
354 struct vop_reg cbcr_hor_scl_mode;
355 struct vop_reg yrgb_vsd_mode;
356 struct vop_reg yrgb_vsu_mode;
357 struct vop_reg yrgb_hsd_mode;
358 struct vop_reg yrgb_ver_scl_mode;
359 struct vop_reg yrgb_hor_scl_mode;
360 struct vop_reg line_load_mode;
361 struct vop_reg cbcr_axi_gather_num;
362 struct vop_reg yrgb_axi_gather_num;
363 struct vop_reg vsd_cbcr_gt2;
364 struct vop_reg vsd_cbcr_gt4;
365 struct vop_reg vsd_yrgb_gt2;
366 struct vop_reg vsd_yrgb_gt4;
367 struct vop_reg bic_coe_sel;
368 struct vop_reg cbcr_axi_gather_en;
369 struct vop_reg yrgb_axi_gather_en;
370 struct vop_reg lb_mode;
371 };
372
373 struct vop_scl_regs {
374 const struct vop_scl_extension *ext;
375
376 struct vop_reg scale_yrgb_x;
377 struct vop_reg scale_yrgb_y;
378 struct vop_reg scale_cbcr_x;
379 struct vop_reg scale_cbcr_y;
380 };
381
382 struct vop_afbc {
383 struct vop_reg enable;
384 struct vop_reg win_sel;
385 struct vop_reg format;
386 struct vop_reg rb_swap;
387 struct vop_reg uv_swap;
388 struct vop_reg auto_gating_en;
389 struct vop_reg rotate;
390 struct vop_reg block_split_en;
391 struct vop_reg pic_vir_width;
392 struct vop_reg tile_num;
393 struct vop_reg pic_offset;
394 struct vop_reg pic_size;
395 struct vop_reg dsp_offset;
396 struct vop_reg transform_offset;
397 struct vop_reg hdr_ptr;
398 struct vop_reg half_block_en;
399 struct vop_reg xmirror;
400 struct vop_reg ymirror;
401 struct vop_reg rotate_270;
402 struct vop_reg rotate_90;
403 struct vop_reg rstn;
404 };
405
406 struct vop_csc_table {
407 const uint32_t *y2r_bt601;
408 const uint32_t *y2r_bt601_12_235;
409 const uint32_t *y2r_bt601_10bit;
410 const uint32_t *y2r_bt601_10bit_12_235;
411 const uint32_t *r2y_bt601;
412 const uint32_t *r2y_bt601_12_235;
413 const uint32_t *r2y_bt601_10bit;
414 const uint32_t *r2y_bt601_10bit_12_235;
415
416 const uint32_t *y2r_bt709;
417 const uint32_t *y2r_bt709_10bit;
418 const uint32_t *r2y_bt709;
419 const uint32_t *r2y_bt709_10bit;
420
421 const uint32_t *y2r_bt2020;
422 const uint32_t *r2y_bt2020;
423
424 const uint32_t *r2r_bt709_to_bt2020;
425 const uint32_t *r2r_bt2020_to_bt709;
426 };
427
428 struct vop_hdr_table {
429 const uint32_t hdr2sdr_eetf_oetf_y0_offset;
430 const uint32_t hdr2sdr_eetf_oetf_y1_offset;
431 const uint32_t *hdr2sdr_eetf_yn;
432 const uint32_t *hdr2sdr_bt1886oetf_yn;
433 const uint32_t hdr2sdr_sat_y0_offset;
434 const uint32_t hdr2sdr_sat_y1_offset;
435 const uint32_t *hdr2sdr_sat_yn;
436
437 const uint32_t hdr2sdr_src_range_min;
438 const uint32_t hdr2sdr_src_range_max;
439 const uint32_t hdr2sdr_normfaceetf;
440 const uint32_t hdr2sdr_dst_range_min;
441 const uint32_t hdr2sdr_dst_range_max;
442 const uint32_t hdr2sdr_normfacgamma;
443
444 const uint32_t sdr2hdr_eotf_oetf_y0_offset;
445 const uint32_t sdr2hdr_eotf_oetf_y1_offset;
446 const uint32_t *sdr2hdr_bt1886eotf_yn_for_hlg_hdr;
447 const uint32_t *sdr2hdr_bt1886eotf_yn_for_bt2020;
448 const uint32_t *sdr2hdr_bt1886eotf_yn_for_hdr;
449 const uint32_t *sdr2hdr_st2084oetf_yn_for_hlg_hdr;
450 const uint32_t *sdr2hdr_st2084oetf_yn_for_bt2020;
451 const uint32_t *sdr2hdr_st2084oetf_yn_for_hdr;
452 const uint32_t sdr2hdr_oetf_dx_dxpow1_offset;
453 const uint32_t *sdr2hdr_st2084oetf_dxn_pow2;
454 const uint32_t *sdr2hdr_st2084oetf_dxn;
455 const uint32_t sdr2hdr_oetf_xn1_offset;
456 const uint32_t *sdr2hdr_st2084oetf_xn;
457 };
458
459 enum {
460 VOP_CSC_Y2R_BT601,
461 VOP_CSC_Y2R_BT709,
462 VOP_CSC_Y2R_BT2020,
463 VOP_CSC_R2Y_BT601,
464 VOP_CSC_R2Y_BT709,
465 VOP_CSC_R2Y_BT2020,
466 VOP_CSC_R2R_BT2020_TO_BT709,
467 VOP_CSC_R2R_BT709_TO_2020,
468 };
469
470 enum _vop_overlay_mode { VOP_RGB_DOMAIN, VOP_YUV_DOMAIN };
471
472 enum _vop_sdr2hdr_func {
473 SDR2HDR_FOR_BT2020,
474 SDR2HDR_FOR_HDR,
475 SDR2HDR_FOR_HLG_HDR,
476 };
477
478 enum _vop_rgb2rgb_conv_mode {
479 BT709_TO_BT2020,
480 BT2020_TO_BT709,
481 };
482
483 enum _MCU_IOCTL {
484 MCU_WRCMD = 0,
485 MCU_WRDATA,
486 MCU_SETBYPASS,
487 };
488
489 struct vop_win_phy {
490 const struct vop_scl_regs *scl;
491 const uint32_t *data_formats;
492 uint32_t nformats;
493
494 struct vop_reg gate;
495 struct vop_reg enable;
496 struct vop_reg format;
497 struct vop_reg fmt_10;
498 struct vop_reg fmt_yuyv;
499 struct vop_reg csc_mode;
500 struct vop_reg xmirror;
501 struct vop_reg ymirror;
502 struct vop_reg rb_swap;
503 struct vop_reg act_info;
504 struct vop_reg dsp_info;
505 struct vop_reg dsp_st;
506 struct vop_reg yrgb_mst;
507 struct vop_reg uv_mst;
508 struct vop_reg yrgb_vir;
509 struct vop_reg uv_vir;
510
511 struct vop_reg channel;
512 struct vop_reg dst_alpha_ctl;
513 struct vop_reg src_alpha_ctl;
514 struct vop_reg alpha_mode;
515 struct vop_reg alpha_en;
516 struct vop_reg alpha_pre_mul;
517 struct vop_reg global_alpha_val;
518 struct vop_reg key_color;
519 struct vop_reg key_en;
520 };
521
522 struct vop_win_data {
523 uint32_t base;
524 enum drm_plane_type type;
525 const struct vop_win_phy *phy;
526 const struct vop_win_phy **area;
527 const uint64_t *format_modifiers;
528 const struct vop_csc *csc;
529 unsigned int area_size;
530 u64 feature;
531 };
532
533 struct vop2_cluster_regs {
534 struct vop_reg enable;
535 struct vop_reg afbc_enable;
536 struct vop_reg lb_mode;
537 };
538
539 struct vop2_scl_regs {
540 struct vop_reg scale_yrgb_x;
541 struct vop_reg scale_yrgb_y;
542 struct vop_reg scale_cbcr_x;
543 struct vop_reg scale_cbcr_y;
544 struct vop_reg yrgb_hor_scl_mode;
545 struct vop_reg yrgb_hscl_filter_mode;
546 struct vop_reg yrgb_ver_scl_mode;
547 struct vop_reg yrgb_vscl_filter_mode;
548 struct vop_reg cbcr_ver_scl_mode;
549 struct vop_reg cbcr_hscl_filter_mode;
550 struct vop_reg cbcr_hor_scl_mode;
551 struct vop_reg cbcr_vscl_filter_mode;
552 struct vop_reg vsd_cbcr_gt2;
553 struct vop_reg vsd_cbcr_gt4;
554 struct vop_reg vsd_yrgb_gt2;
555 struct vop_reg vsd_yrgb_gt4;
556 struct vop_reg bic_coe_sel;
557 };
558
559 struct vop2_win_regs {
560 const struct vop2_scl_regs *scl;
561 const struct vop2_cluster_regs *cluster;
562 const struct vop_afbc *afbc;
563
564 struct vop_reg gate;
565 struct vop_reg enable;
566 struct vop_reg format;
567 struct vop_reg csc_mode;
568 struct vop_reg xmirror;
569 struct vop_reg ymirror;
570 struct vop_reg rb_swap;
571 struct vop_reg uv_swap;
572 struct vop_reg act_info;
573 struct vop_reg dsp_info;
574 struct vop_reg dsp_st;
575 struct vop_reg yrgb_mst;
576 struct vop_reg uv_mst;
577 struct vop_reg yrgb_vir;
578 struct vop_reg uv_vir;
579 struct vop_reg yuv_clip;
580 struct vop_reg lb_mode;
581 struct vop_reg y2r_en;
582 struct vop_reg r2y_en;
583 struct vop_reg channel;
584 struct vop_reg dst_alpha_ctl;
585 struct vop_reg src_alpha_ctl;
586 struct vop_reg alpha_mode;
587 struct vop_reg alpha_en;
588 struct vop_reg global_alpha_val;
589 struct vop_reg color_key;
590 struct vop_reg color_key_en;
591 struct vop_reg dither_up;
592 struct vop_reg axi_id;
593 struct vop_reg axi_yrgb_id;
594 struct vop_reg axi_uv_id;
595 };
596
597 struct vop2_video_port_regs {
598 struct vop_reg cfg_done;
599 struct vop_reg overlay_mode;
600 struct vop_reg dsp_background;
601 struct vop_reg port_mux;
602 struct vop_reg out_mode;
603 struct vop_reg standby;
604 struct vop_reg dsp_interlace;
605 struct vop_reg dsp_filed_pol;
606 struct vop_reg dsp_data_swap;
607 struct vop_reg post_dsp_out_r2y;
608 struct vop_reg pre_scan_htiming;
609 struct vop_reg htotal_pw;
610 struct vop_reg hact_st_end;
611 struct vop_reg vtotal_pw;
612 struct vop_reg vact_st_end;
613 struct vop_reg vact_st_end_f1;
614 struct vop_reg vs_st_end_f1;
615 struct vop_reg hpost_st_end;
616 struct vop_reg vpost_st_end;
617 struct vop_reg vpost_st_end_f1;
618 struct vop_reg post_scl_factor;
619 struct vop_reg post_scl_ctrl;
620 struct vop_reg dither_down_sel;
621 struct vop_reg dither_down_mode;
622 struct vop_reg dither_down_en;
623 struct vop_reg pre_dither_down_en;
624 struct vop_reg dither_up_en;
625 struct vop_reg bg_dly;
626
627 struct vop_reg core_dclk_div;
628 struct vop_reg p2i_en;
629 struct vop_reg dual_channel_en;
630 struct vop_reg dual_channel_swap;
631 struct vop_reg dsp_lut_en;
632
633 struct vop_reg dclk_div2;
634 struct vop_reg dclk_div2_phase_lock;
635
636 struct vop_reg hdr10_en;
637 struct vop_reg hdr_lut_update_en;
638 struct vop_reg hdr_lut_mode;
639 struct vop_reg hdr_lut_mst;
640 struct vop_reg sdr2hdr_eotf_en;
641 struct vop_reg sdr2hdr_r2r_en;
642 struct vop_reg sdr2hdr_r2r_mode;
643 struct vop_reg sdr2hdr_oetf_en;
644 struct vop_reg sdr2hdr_bypass_en;
645 struct vop_reg sdr2hdr_auto_gating_en;
646 struct vop_reg sdr2hdr_path_en;
647 struct vop_reg hdr2sdr_en;
648 struct vop_reg hdr2sdr_bypass_en;
649 struct vop_reg hdr2sdr_auto_gating_en;
650 struct vop_reg hdr2sdr_src_min;
651 struct vop_reg hdr2sdr_src_max;
652 struct vop_reg hdr2sdr_normfaceetf;
653 struct vop_reg hdr2sdr_dst_min;
654 struct vop_reg hdr2sdr_dst_max;
655 struct vop_reg hdr2sdr_normfacgamma;
656 uint32_t hdr2sdr_eetf_oetf_y0_offset;
657 uint32_t hdr2sdr_sat_y0_offset;
658 uint32_t sdr2hdr_eotf_oetf_y0_offset;
659 uint32_t sdr2hdr_oetf_dx_pow1_offset;
660 uint32_t sdr2hdr_oetf_xn1_offset;
661 struct vop_reg hdr_src_color_ctrl;
662 struct vop_reg hdr_dst_color_ctrl;
663 struct vop_reg hdr_src_alpha_ctrl;
664 struct vop_reg hdr_dst_alpha_ctrl;
665 struct vop_reg bg_mix_ctrl;
666
667 /* BCSH */
668 struct vop_reg bcsh_brightness;
669 struct vop_reg bcsh_contrast;
670 struct vop_reg bcsh_sat_con;
671 struct vop_reg bcsh_sin_hue;
672 struct vop_reg bcsh_cos_hue;
673 struct vop_reg bcsh_r2y_csc_mode;
674 struct vop_reg bcsh_r2y_en;
675 struct vop_reg bcsh_y2r_csc_mode;
676 struct vop_reg bcsh_y2r_en;
677 struct vop_reg bcsh_out_mode;
678 struct vop_reg bcsh_en;
679
680 /* 3d lut */
681 struct vop_reg cubic_lut_en;
682 struct vop_reg cubic_lut_update_en;
683 struct vop_reg cubic_lut_mst;
684
685 /* cru */
686 struct vop_reg dclk_core_div;
687 struct vop_reg dclk_out_div;
688 struct vop_reg dclk_src_sel;
689
690 struct vop_reg splice_en;
691
692 struct vop_reg edpi_wms_hold_en;
693 struct vop_reg edpi_te_en;
694 struct vop_reg edpi_wms_fs;
695 struct vop_reg gamma_update_en;
696 struct vop_reg lut_dma_rid;
697 };
698
699 struct vop2_power_domain_regs {
700 struct vop_reg pd;
701 struct vop_reg status;
702 struct vop_reg bisr_en_status;
703 struct vop_reg pmu_status;
704 };
705
706 struct vop2_dsc_regs {
707 /* DSC SYS CTRL */
708 struct vop_reg dsc_port_sel;
709 struct vop_reg dsc_man_mode;
710 struct vop_reg dsc_interface_mode;
711 struct vop_reg dsc_pixel_num;
712 struct vop_reg dsc_pxl_clk_div;
713 struct vop_reg dsc_cds_clk_div;
714 struct vop_reg dsc_txp_clk_div;
715 struct vop_reg dsc_init_dly_mode;
716 struct vop_reg dsc_scan_en;
717 struct vop_reg dsc_halt_en;
718 struct vop_reg rst_deassert;
719 struct vop_reg dsc_flush;
720 struct vop_reg dsc_cfg_done;
721 struct vop_reg dsc_init_dly_num;
722 struct vop_reg scan_timing_para_imd_en;
723 struct vop_reg dsc_htotal_pw;
724 struct vop_reg dsc_hact_st_end;
725 struct vop_reg dsc_vtotal_pw;
726 struct vop_reg dsc_vact_st_end;
727 struct vop_reg dsc_error_status;
728
729 /* DSC encoder */
730 struct vop_reg dsc_pps0_3;
731 struct vop_reg dsc_en;
732 struct vop_reg dsc_rbit;
733 struct vop_reg dsc_rbyt;
734 struct vop_reg dsc_flal;
735 struct vop_reg dsc_mer;
736 struct vop_reg dsc_epb;
737 struct vop_reg dsc_epl;
738 struct vop_reg dsc_nslc;
739 struct vop_reg dsc_sbo;
740 struct vop_reg dsc_ifep;
741 struct vop_reg dsc_pps_upd;
742 struct vop_reg dsc_status;
743 struct vop_reg dsc_ecw;
744 };
745
746 struct vop2_wb_regs {
747 struct vop_reg enable;
748 struct vop_reg format;
749 struct vop_reg dither_en;
750 struct vop_reg r2y_en;
751 struct vop_reg yrgb_mst;
752 struct vop_reg uv_mst;
753 struct vop_reg vp_id;
754 struct vop_reg fifo_throd;
755 struct vop_reg scale_x_factor;
756 struct vop_reg scale_x_en;
757 struct vop_reg scale_y_en;
758 struct vop_reg axi_yrgb_id;
759 struct vop_reg axi_uv_id;
760 };
761
762 struct vop2_power_domain_data {
763 uint8_t id;
764 uint8_t parent_id;
765 const struct vop2_power_domain_regs *regs;
766 };
767
768 /*
769 * connector interface(RGB/HDMI/eDP/DP/MIPI) data
770 */
771 struct vop2_connector_if_data {
772 u32 id;
773 const char *clk_src_name;
774 const char *clk_parent_name;
775 const char *pixclk_name;
776 const char *dclk_name;
777 u32 post_proc_div_shift;
778 u32 if_div_shift;
779 u32 if_div_yuv420_shift;
780 u32 bus_div_shift;
781 u32 pixel_clk_div_shift;
782 };
783
784 struct vop2_win_data {
785 const char *name;
786 uint8_t phys_id;
787 uint8_t splice_win_id;
788 uint8_t pd_id;
789 uint8_t axi_id;
790 uint8_t axi_yrgb_id;
791 uint8_t axi_uv_id;
792
793 uint32_t base;
794 enum drm_plane_type type;
795
796 uint32_t nformats;
797 const uint32_t *formats;
798 const uint64_t *format_modifiers;
799 const unsigned int supported_rotations;
800
801 const struct vop2_win_regs *regs;
802 const struct vop2_win_regs **area;
803 unsigned int area_size;
804
805 /*
806 * vertical/horizontal scale up/down filter mode
807 */
808 const u8 hsu_filter_mode;
809 const u8 hsd_filter_mode;
810 const u8 vsu_filter_mode;
811 const u8 vsd_filter_mode;
812 /**
813 * @layer_sel_id: defined by register OVERLAY_LAYER_SEL of VOP2
814 */
815 int layer_sel_id;
816 uint64_t feature;
817
818 unsigned int max_upscale_factor;
819 unsigned int max_downscale_factor;
820 const uint8_t dly[VOP2_DLY_MODE_MAX];
821 };
822
823 struct dsc_error_info {
824 u32 dsc_error_val;
825 char dsc_error_info[50];
826 };
827
828 struct vop2_dsc_data {
829 uint8_t id;
830 uint8_t pd_id;
831 uint8_t max_slice_num;
832 uint8_t max_linebuf_depth; /* used to generate the bitstream */
833 uint8_t min_bits_per_pixel; /* bit num after encoder compress */
834 const char *dsc_txp_clk_src_name;
835 const char *dsc_txp_clk_name;
836 const char *dsc_pxl_clk_name;
837 const char *dsc_cds_clk_name;
838 const struct vop2_dsc_regs *regs;
839 };
840
841 struct vop2_wb_data {
842 uint32_t nformats;
843 const uint32_t *formats;
844 struct vop_rect max_output;
845 const struct vop2_wb_regs *regs;
846 uint32_t fifo_depth;
847 };
848
849 struct vop2_video_port_data {
850 char id;
851 uint8_t splice_vp_id;
852 uint16_t lut_dma_rid;
853 uint32_t feature;
854 uint64_t soc_id[VOP2_SOC_VARIANT];
855 uint16_t gamma_lut_len;
856 uint16_t cubic_lut_len;
857 unsigned long dclk_max;
858 struct vop_rect max_output;
859 const u8 pre_scan_max_dly[4];
860 const struct vop_intr *intr;
861 const struct vop_hdr_table *hdr_table;
862 const struct vop2_video_port_regs *regs;
863 };
864
865 struct vop2_layer_regs {
866 struct vop_reg layer_sel;
867 };
868
869 /**
870 * struct vop2_layer_data - The logic graphic layer in vop2
871 *
872 * The zorder:
873 * LAYERn
874 * LAYERn-1
875 * .
876 * .
877 * .
878 * LAYER5
879 * LAYER4
880 * LAYER3
881 * LAYER2
882 * LAYER1
883 * LAYER0
884 *
885 * Each layer can select a unused window as input than feed to
886 * mixer for overlay.
887 *
888 * The pipeline in vop2:
889 *
890 * win-->layer-->mixer-->vp--->connector(RGB/LVDS/HDMI/MIPI)
891 *
892 */
893 struct vop2_layer_data {
894 char id;
895 const struct vop2_layer_regs *regs;
896 };
897
898 struct vop_grf_ctrl {
899 struct vop_reg grf_dclk_inv;
900 struct vop_reg grf_bt1120_clk_inv;
901 struct vop_reg grf_bt656_clk_inv;
902 struct vop_reg grf_edp0_en;
903 struct vop_reg grf_edp1_en;
904 struct vop_reg grf_hdmi0_en;
905 struct vop_reg grf_hdmi1_en;
906 struct vop_reg grf_hdmi0_dsc_en;
907 struct vop_reg grf_hdmi1_dsc_en;
908 struct vop_reg grf_hdmi0_pin_pol;
909 struct vop_reg grf_hdmi1_pin_pol;
910 };
911
912 struct vop_data {
913 const struct vop_reg_data *init_table;
914 unsigned int table_size;
915 const struct vop_ctrl *ctrl;
916 const struct vop_intr *intr;
917 const struct vop_win_data *win;
918 const struct vop_csc_table *csc_table;
919 const struct vop_hdr_table *hdr_table;
920 const struct vop_grf_ctrl *grf_ctrl;
921 unsigned int win_size;
922 uint32_t version;
923 struct vop_rect max_input;
924 struct vop_rect max_output;
925 u64 feature;
926 u64 soc_id;
927 u8 vop_id;
928 };
929
930 struct vop2_ctrl {
931 struct vop_reg cfg_done_en;
932 struct vop_reg wb_cfg_done;
933 struct vop_reg auto_gating_en;
934 struct vop_reg ovl_cfg_done_port;
935 struct vop_reg ovl_port_mux_cfg_done_imd;
936 struct vop_reg ovl_port_mux_cfg;
937 struct vop_reg if_ctrl_cfg_done_imd;
938 struct vop_reg version;
939 struct vop_reg standby;
940 struct vop_reg dma_stop;
941 struct vop_reg lut_dma_en;
942 struct vop_reg axi_outstanding_max_num;
943 struct vop_reg axi_max_outstanding_en;
944 struct vop_reg hdmi_dclk_out_en;
945 struct vop_reg rgb_en;
946 struct vop_reg hdmi0_en;
947 struct vop_reg hdmi1_en;
948 struct vop_reg dp0_en;
949 struct vop_reg dp1_en;
950 struct vop_reg edp0_en;
951 struct vop_reg edp1_en;
952 struct vop_reg mipi0_en;
953 struct vop_reg mipi1_en;
954 struct vop_reg lvds0_en;
955 struct vop_reg lvds1_en;
956 struct vop_reg bt656_en;
957 struct vop_reg bt1120_en;
958 struct vop_reg dclk_pol;
959 struct vop_reg pin_pol;
960 struct vop_reg rgb_dclk_pol;
961 struct vop_reg rgb_pin_pol;
962 struct vop_reg lvds_dclk_pol;
963 struct vop_reg lvds_pin_pol;
964 struct vop_reg hdmi_dclk_pol;
965 struct vop_reg hdmi_pin_pol;
966 struct vop_reg edp_dclk_pol;
967 struct vop_reg edp_pin_pol;
968 struct vop_reg mipi_dclk_pol;
969 struct vop_reg mipi_pin_pol;
970 struct vop_reg dp0_dclk_pol;
971 struct vop_reg dp0_pin_pol;
972 struct vop_reg dp1_dclk_pol;
973 struct vop_reg dp1_pin_pol;
974
975 /* This will be reference by win_phy_id */
976 struct vop_reg win_vp_id[16];
977 struct vop_reg win_dly[16];
978
979 /* connector mux */
980 struct vop_reg rgb_mux;
981 struct vop_reg hdmi0_mux;
982 struct vop_reg hdmi1_mux;
983 struct vop_reg dp0_mux;
984 struct vop_reg dp1_mux;
985 struct vop_reg edp0_mux;
986 struct vop_reg edp1_mux;
987 struct vop_reg mipi0_mux;
988 struct vop_reg mipi1_mux;
989 struct vop_reg lvds0_mux;
990 struct vop_reg lvds1_mux;
991
992 struct vop_reg lvds_dual_en;
993 struct vop_reg lvds_dual_mode;
994 struct vop_reg lvds_dual_channel_swap;
995
996 struct vop_reg dp_dual_en;
997 struct vop_reg edp_dual_en;
998 struct vop_reg hdmi_dual_en;
999 struct vop_reg mipi_dual_en;
1000
1001 struct vop_reg hdmi0_dclk_div;
1002 struct vop_reg hdmi0_pixclk_div;
1003 struct vop_reg edp0_dclk_div;
1004 struct vop_reg edp0_pixclk_div;
1005
1006 struct vop_reg hdmi1_dclk_div;
1007 struct vop_reg hdmi1_pixclk_div;
1008 struct vop_reg edp1_dclk_div;
1009 struct vop_reg edp1_pixclk_div;
1010
1011 struct vop_reg mipi0_pixclk_div;
1012 struct vop_reg mipi1_pixclk_div;
1013 struct vop_reg mipi0_ds_mode;
1014 struct vop_reg mipi1_ds_mode;
1015
1016 struct vop_reg cluster0_src_color_ctrl;
1017 struct vop_reg cluster0_dst_color_ctrl;
1018 struct vop_reg cluster0_src_alpha_ctrl;
1019 struct vop_reg cluster0_dst_alpha_ctrl;
1020 struct vop_reg src_color_ctrl;
1021 struct vop_reg dst_color_ctrl;
1022 struct vop_reg src_alpha_ctrl;
1023 struct vop_reg dst_alpha_ctrl;
1024
1025 struct vop_reg bt1120_yc_swap;
1026 struct vop_reg bt656_yc_swap;
1027 struct vop_reg gamma_port_sel;
1028 struct vop_reg pd_off_imd;
1029
1030 struct vop_reg otp_en;
1031 struct vop_reg reg_done_frm;
1032 struct vop_reg cfg_done;
1033 };
1034
1035 /**
1036 * VOP2 data structe
1037 *
1038 * @version: VOP IP version
1039 * @win_size: hardware win number
1040 */
1041 struct vop2_data {
1042 uint32_t version;
1043 uint32_t feature;
1044 uint8_t nr_dscs;
1045 uint8_t nr_dsc_ecw;
1046 uint8_t nr_dsc_buffer_flow;
1047 uint8_t nr_vps;
1048 uint8_t nr_mixers;
1049 uint8_t nr_layers;
1050 uint8_t nr_axi_intr;
1051 uint8_t nr_gammas;
1052 uint8_t nr_conns;
1053 uint8_t nr_pds;
1054 uint8_t nr_mem_pgs;
1055 bool delayed_pd;
1056 const struct vop_intr *axi_intr;
1057 const struct vop2_ctrl *ctrl;
1058 const struct vop2_dsc_data *dsc;
1059 const struct dsc_error_info *dsc_error_ecw;
1060 const struct dsc_error_info *dsc_error_buffer_flow;
1061 const struct vop2_win_data *win;
1062 const struct vop2_video_port_data *vp;
1063 const struct vop2_connector_if_data *conn;
1064 const struct vop2_wb_data *wb;
1065 const struct vop2_layer_data *layer;
1066 const struct vop2_power_domain_data *pd;
1067 const struct vop2_power_domain_data *mem_pg;
1068 const struct vop_csc_table *csc_table;
1069 const struct vop_hdr_table *hdr_table;
1070 const struct vop_grf_ctrl *sys_grf;
1071 const struct vop_grf_ctrl *grf;
1072 const struct vop_grf_ctrl *vo0_grf;
1073 const struct vop_grf_ctrl *vo1_grf;
1074 struct vop_rect max_input;
1075 struct vop_rect max_output;
1076
1077 unsigned int win_size;
1078 };
1079
1080 #define CVBS_PAL_VDISPLAY 288
1081
1082 /* interrupt define */
1083 #define DSP_HOLD_VALID_INTR BIT(0)
1084 #define FS_INTR BIT(1)
1085 #define LINE_FLAG_INTR BIT(2)
1086 #define BUS_ERROR_INTR BIT(3)
1087 #define FS_NEW_INTR BIT(4)
1088 #define ADDR_SAME_INTR BIT(5)
1089 #define LINE_FLAG1_INTR BIT(6)
1090 #define WIN0_EMPTY_INTR BIT(7)
1091 #define WIN1_EMPTY_INTR BIT(8)
1092 #define WIN2_EMPTY_INTR BIT(9)
1093 #define WIN3_EMPTY_INTR BIT(10)
1094 #define HWC_EMPTY_INTR BIT(11)
1095 #define POST_BUF_EMPTY_INTR BIT(12)
1096 #define PWM_GEN_INTR BIT(13)
1097 #define DMA_FINISH_INTR BIT(14)
1098 #define FS_FIELD_INTR BIT(15)
1099 #define FE_INTR BIT(16)
1100 #define WB_UV_FIFO_FULL_INTR BIT(17)
1101 #define WB_YRGB_FIFO_FULL_INTR BIT(18)
1102 #define WB_COMPLETE_INTR BIT(19)
1103
1104 #define INTR_MASK \
1105 (DSP_HOLD_VALID_INTR | FS_INTR | LINE_FLAG_INTR | BUS_ERROR_INTR | FS_NEW_INTR | LINE_FLAG1_INTR | \
1106 WIN0_EMPTY_INTR | WIN1_EMPTY_INTR | WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | HWC_EMPTY_INTR | POST_BUF_EMPTY_INTR | \
1107 DMA_FINISH_INTR | FS_FIELD_INTR | FE_INTR)
1108 #define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
1109 #define FS_INTR_EN(x) ((x) << 5)
1110 #define LINE_FLAG_INTR_EN(x) ((x) << 6)
1111 #define BUS_ERROR_INTR_EN(x) ((x) << 7)
1112 #define DSP_HOLD_VALID_INTR_MASK (1 << 4)
1113 #define FS_INTR_MASK (1 << 5)
1114 #define LINE_FLAG_INTR_MASK (1 << 6)
1115 #define BUS_ERROR_INTR_MASK (1 << 7)
1116
1117 #define INTR_CLR_SHIFT 8
1118 #define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
1119 #define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
1120 #define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
1121 #define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
1122
1123 #define DSP_LINE_NUM(x) (((x)&0x1fff) << 12)
1124 #define DSP_LINE_NUM_MASK (0x1fff << 12)
1125
1126 /* src alpha ctrl define */
1127 #define SRC_FADING_VALUE(x) (((x)&0xff) << 24)
1128 #define SRC_GLOBAL_ALPHA(x) (((x)&0xff) << 16)
1129 #define SRC_FACTOR_M0(x) (((x)&0x7) << 6)
1130 #define SRC_ALPHA_CAL_M0(x) (((x)&0x1) << 5)
1131 #define SRC_BLEND_M0(x) (((x)&0x3) << 3)
1132 #define SRC_ALPHA_M0(x) (((x)&0x1) << 2)
1133 #define SRC_COLOR_M0(x) (((x)&0x1) << 1)
1134 #define SRC_ALPHA_EN(x) (((x)&0x1) << 0)
1135 /* dst alpha ctrl define */
1136 #define DST_FACTOR_M0(x) (((x)&0x7) << 6)
1137
1138 /*
1139 * display output interface supported by rockchip lcdc
1140 */
1141 #define ROCKCHIP_OUT_MODE_P888 0
1142 #define ROCKCHIP_OUT_MODE_BT1120 0
1143 #define ROCKCHIP_OUT_MODE_P666 1
1144 #define ROCKCHIP_OUT_MODE_P565 2
1145 #define ROCKCHIP_OUT_MODE_BT656 5
1146 #define ROCKCHIP_OUT_MODE_S888 8
1147 #define ROCKCHIP_OUT_MODE_S888_DUMMY 12
1148 #define ROCKCHIP_OUT_MODE_YUV420 14
1149 /* for use special outface */
1150 #define ROCKCHIP_OUT_MODE_AAAA 15
1151
1152 #define ROCKCHIP_OUT_MODE_TYPE(x) ((x) >> 16)
1153 #define ROCKCHIP_OUT_MODE(x) ((x)&0xffff)
1154
1155 enum alpha_mode {
1156 ALPHA_STRAIGHT,
1157 ALPHA_INVERSE,
1158 };
1159
1160 enum global_blend_mode {
1161 ALPHA_GLOBAL,
1162 ALPHA_PER_PIX,
1163 ALPHA_PER_PIX_GLOBAL,
1164 };
1165
1166 enum alpha_cal_mode {
1167 ALPHA_SATURATION,
1168 ALPHA_NO_SATURATION,
1169 };
1170
1171 enum color_mode {
1172 ALPHA_SRC_PRE_MUL,
1173 ALPHA_SRC_NO_PRE_MUL,
1174 };
1175
1176 enum factor_mode {
1177 ALPHA_ZERO,
1178 ALPHA_ONE,
1179 ALPHA_SRC,
1180 ALPHA_SRC_INVERSE,
1181 ALPHA_SRC_GLOBAL,
1182 ALPHA_DST_GLOBAL,
1183 };
1184
1185 enum src_factor_mode {
1186 SRC_FAC_ALPHA_ZERO,
1187 SRC_FAC_ALPHA_ONE,
1188 SRC_FAC_ALPHA_DST,
1189 SRC_FAC_ALPHA_DST_INVERSE,
1190 SRC_FAC_ALPHA_SRC,
1191 SRC_FAC_ALPHA_SRC_GLOBAL,
1192 };
1193
1194 enum dst_factor_mode {
1195 DST_FAC_ALPHA_ZERO,
1196 DST_FAC_ALPHA_ONE,
1197 DST_FAC_ALPHA_SRC,
1198 DST_FAC_ALPHA_SRC_INVERSE,
1199 DST_FAC_ALPHA_DST,
1200 DST_FAC_ALPHA_DST_GLOBAL,
1201 };
1202
1203 enum scale_mode { SCALE_NONE = 0x0, SCALE_UP = 0x1, SCALE_DOWN = 0x2 };
1204
1205 enum lb_mode {
1206 LB_YUV_3840X5 = 0x0,
1207 LB_YUV_2560X8 = 0x1,
1208 LB_RGB_3840X2 = 0x2,
1209 LB_RGB_2560X4 = 0x3,
1210 LB_RGB_1920X5 = 0x4,
1211 LB_RGB_1280X8 = 0x5
1212 };
1213
1214 enum sacle_up_mode { SCALE_UP_BIL = 0x0, SCALE_UP_BIC = 0x1 };
1215
1216 enum scale_down_mode { SCALE_DOWN_BIL = 0x0, SCALE_DOWN_AVG = 0x1 };
1217
1218 enum vop2_scale_up_mode {
1219 VOP2_SCALE_UP_NRST_NBOR,
1220 VOP2_SCALE_UP_BIL,
1221 VOP2_SCALE_UP_BIC,
1222 };
1223
1224 enum vop2_scale_down_mode {
1225 VOP2_SCALE_DOWN_NRST_NBOR,
1226 VOP2_SCALE_DOWN_BIL,
1227 VOP2_SCALE_DOWN_AVG,
1228 };
1229
1230 enum dither_down_mode { RGB888_TO_RGB565 = 0x0, RGB888_TO_RGB666 = 0x1 };
1231
1232 enum dither_down_mode_sel { DITHER_DOWN_ALLEGRO = 0x0, DITHER_DOWN_FRC = 0x1 };
1233
1234 enum vop_pol { HSYNC_POSITIVE = 0, VSYNC_POSITIVE = 1, DEN_NEGATIVE = 2, DCLK_INVERT = 3 };
1235
1236 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
1237 #define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
1238 #define SCL_MAX_VSKIPLINES 4
1239 #define MIN_SCL_FT_AFTER_VSKIP 1
1240
scl_cal_scale(int src,int dst,int shift)1241 static inline uint16_t scl_cal_scale(int src, int dst, int shift)
1242 {
1243 return ((src * 0x2 - 0x3) << (shift - 1)) / (dst - 1);
1244 }
1245
scl_cal_scale2(int src,int dst)1246 static inline uint16_t scl_cal_scale2(int src, int dst)
1247 {
1248 return ((src - 1) << 0xc) / (dst - 1);
1249 }
1250
1251 #define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 0xc)
1252 #define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 0x10)
1253 #define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 0x10)
1254
scl_get_bili_dn_vskip(int src_h,int dst_h,int vskiplines)1255 static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h, int vskiplines)
1256 {
1257 int act_height;
1258
1259 act_height = (src_h + vskiplines - 1) / vskiplines;
1260
1261 if (act_height == dst_h) {
1262 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
1263 }
1264
1265 return GET_SCL_FT_BILI_DN(act_height, dst_h);
1266 }
1267
scl_get_scl_mode(int src,int dst)1268 static inline enum scale_mode scl_get_scl_mode(int src, int dst)
1269 {
1270 if (src < dst) {
1271 return SCALE_UP;
1272 } else if (src > dst) {
1273 return SCALE_DOWN;
1274 }
1275
1276 return SCALE_NONE;
1277 }
1278
scl_get_vskiplines(uint32_t srch,uint32_t dsth)1279 static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
1280 {
1281 uint32_t vskiplines;
1282
1283 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 0x2) {
1284 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP) {
1285 break;
1286 }
1287 }
1288
1289 return vskiplines;
1290 }
1291
scl_vop_cal_lb_mode(int width,bool is_yuv)1292 static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
1293 {
1294 int lb_mode;
1295
1296 if (is_yuv) {
1297 if (width > 0x500) {
1298 lb_mode = LB_YUV_3840X5;
1299 } else {
1300 lb_mode = LB_YUV_2560X8;
1301 }
1302 } else {
1303 if (width > 0xa00) {
1304 lb_mode = LB_RGB_3840X2;
1305 } else if (width > 0x780) {
1306 lb_mode = LB_RGB_2560X4;
1307 } else {
1308 lb_mode = LB_RGB_1920X5;
1309 }
1310 }
1311
1312 return lb_mode;
1313 }
1314
us_to_vertical_line(struct drm_display_mode * mode,int us)1315 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us)
1316 {
1317 return us * mode->clock / mode->htotal / 0x3e8;
1318 }
1319
interpolate(int x1,int y1,int x2,int y2,int x)1320 static inline int interpolate(int x1, int y1, int x2, int y2, int x)
1321 {
1322 return y1 + (y2 - y1) * (x - x1) / (x2 - x1);
1323 }
1324
1325 extern void vop2_standby(struct drm_crtc *crtc, bool standby);
1326 extern const struct component_ops vop_component_ops;
1327 extern const struct component_ops vop2_component_ops;
1328 #endif /* _ROCKCHIP_DRM_VOP_H */
1329