1 /* 2 * Copyright © 2022 Imagination Technologies Ltd. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 #ifndef PVR_ROGUE_FWIF_H 25 #define PVR_ROGUE_FWIF_H 26 27 #include <assert.h> 28 #include <stddef.h> 29 #include <stdint.h> 30 31 #include "hwdef/rogue_hw_defs.h" 32 #include "pvr_rogue_fwif_shared.h" 33 #include "pvr_winsys.h" 34 35 /** 36 * \name Frag DM command flags. 37 * Flags supported by the Frag DM command i.e. /ref rogue_fwif_cmd_3d . 38 */ 39 /**@{*/ 40 /** Render needs flipped sample positions. */ 41 #define ROGUE_FWIF_RENDERFLAGS_FLIP_SAMPLE_POSITIONS 0x00000001UL 42 /** 43 * The scene has been aborted, free the parameters and dummy process to 44 * completion. 45 */ 46 #define ROGUE_FWIF_RENDERFLAGS_ABORT 0x00000002UL 47 /** The TA before this was not marked as LAST. */ 48 #define ROGUE_FWIF_RENDERFLAGS_3D_ONLY 0x00000004UL 49 /** Use single core in a multi core setup. */ 50 #define ROGUE_FWIF_RENDERFLAGS_SINGLE_CORE 0x00000008UL 51 /** 52 * This render has visibility result associated with it. Setting this flag will 53 * cause the firmware to collect the visibility results. 54 */ 55 #define ROGUE_FWIF_RENDERFLAGS_GETVISRESULTS 0x00000020UL 56 /** Indicates whether a depth buffer is present. */ 57 #define ROGUE_FWIF_RENDERFLAGS_DEPTHBUFFER 0x00000080UL 58 /** Indicates whether a stencil buffer is present. */ 59 #define ROGUE_FWIF_RENDERFLAGS_STENCILBUFFER 0x00000100UL 60 /** This render needs DRM Security. */ 61 #define ROGUE_FWIF_RENDERFLAGS_SECURE 0x00002000UL 62 /** 63 * This flags goes in hand with ABORT and explicitly ensures no mem free is 64 * issued in case of first TA job. 65 */ 66 #define ROGUE_FWIF_RENDERFLAGS_ABORT_NOFREE 0x00004000UL 67 /** Force disabling of pixel merging. */ 68 #define ROGUE_FWIF_RENDERFLAGS_DISABLE_PIXELMERGE 0x00008000UL 69 70 /** Force 4 lines of coeffs on render. */ 71 #define ROGUE_FWIF_RENDERFLAGS_CSRM_MAX_COEFFS 0x00020000UL 72 73 /** Partial render must write to scratch buffer. */ 74 #define ROGUE_FWIF_RENDERFLAGS_SPMSCRATCHBUFFER 0x00080000UL 75 76 /** Render uses paired tile feature, empty tiles must always be enabled. */ 77 #define ROGUE_FWIF_RENDERFLAGS_PAIRED_TILES 0x00100000UL 78 79 #define ROGUE_FWIF_RENDERFLAGS_RESERVED 0x01000000UL 80 81 /** Disallow compute overlapped with this render. */ 82 #define ROGUE_FWIF_RENDERFLAGS_PREVENT_CDM_OVERLAP 0x04000000UL 83 /**@}*/ 84 /* End of \name Frag DM command flags. */ 85 86 /** 87 * The host must indicate if this is the first and/or last command to be issued 88 * for the specified task. 89 */ 90 91 /** 92 * \name Geom DM command flags. 93 * Flags supported by the Geom DM command i.e. \ref rogue_fwif_cmd_ta . 94 */ 95 /**@{*/ 96 #define ROGUE_FWIF_TAFLAGS_FIRSTKICK 0x00000001UL 97 #define ROGUE_FWIF_TAFLAGS_LASTKICK 0x00000002UL 98 #define ROGUE_FWIF_TAFLAGS_FLIP_SAMPLE_POSITIONS 0x00000004UL 99 /** Use single core in a multi core setup. */ 100 #define ROGUE_FWIF_TAFLAGS_SINGLE_CORE 0x00000008UL 101 102 /** Enable Tile Region Protection for this TA. */ 103 #define ROGUE_FWIF_TAFLAGS_TRP 0x00000010UL 104 105 /** 106 * Indicates the particular TA needs to be aborted. 107 * The scene has been aborted, discard this TA command. 108 */ 109 #define ROGUE_FWIF_TAFLAGS_TA_ABORT 0x00000100UL 110 #define ROGUE_FWIF_TAFLAGS_SECURE 0x00080000UL 111 112 /** 113 * Indicates that the CSRM should be reconfigured to support maximum coeff 114 * space before this command is scheduled. 115 */ 116 #define ROGUE_FWIF_TAFLAGS_CSRM_MAX_COEFFS 0x00200000UL 117 118 #define ROGUE_FWIF_TAFLAGS_PHR_TRIGGER 0x02000000UL 119 /**@}/ 120 * End of \name Geom DM command flags. */ 121 122 /* Flags for transfer queue commands. */ 123 #define ROGUE_FWIF_CMDTRANSFER_FLAG_SECURE 0x00000001U 124 /** Use single core in a multi core setup. */ 125 #define ROGUE_FWIF_CMDTRANSFER_SINGLE_CORE 0x00000002U 126 #define ROGUE_FWIF_CMDTRANSFER_TRP 0x00000004U 127 128 /* Flags for 2D commands. */ 129 #define ROGUE_FWIF_CMD2D_FLAG_SECURE 0x00000001U 130 131 #define ROGUE_FWIF_CMD3DTQ_SLICE_WIDTH_MASK 0x00000038UL 132 #define ROGUE_FWIF_CMD3DTQ_SLICE_WIDTH_SHIFT (3) 133 #define ROGUE_FWIF_CMD3DTQ_SLICE_GRANULARITY (0x10U) 134 135 /* Flags for compute commands. */ 136 #define ROGUE_FWIF_COMPUTE_FLAG_SECURE 0x00000001U 137 #define ROGUE_FWIF_COMPUTE_FLAG_PREVENT_ALL_OVERLAP 0x00000002U 138 #define ROGUE_FWIF_COMPUTE_FLAG_FORCE_TPU_CLK 0x00000004U 139 140 #define ROGUE_FWIF_COMPUTE_FLAG_PREVENT_ALL_NON_TAOOM_OVERLAP 0x00000010U 141 142 /** Use single core in a multi core setup. */ 143 #define ROGUE_FWIF_COMPUTE_FLAG_SINGLE_CORE 0x00000020U 144 145 /*********************************************** 146 Parameter/HWRTData control structures. 147 ***********************************************/ 148 149 /** 150 * \brief Configuration registers which need to be loaded by the firmware before 151 * a TA job can be started. 152 */ 153 struct rogue_fwif_ta_regs { 154 uint64_t vdm_ctrl_stream_base; 155 uint64_t tpu_border_colour_table; 156 157 /* Only used when feature VDM_DRAWINDIRECT present. */ 158 uint64_t vdm_draw_indirect0; 159 /* Only used when feature VDM_DRAWINDIRECT present. */ 160 uint32_t vdm_draw_indirect1; 161 162 uint32_t ppp_ctrl; 163 uint32_t te_psg; 164 /* Only used when BRN 49927 present. */ 165 uint32_t tpu; 166 167 uint32_t vdm_context_resume_task0_size; 168 /* Only used when feature VDM_OBJECT_LEVEL_LLS present. */ 169 uint32_t vdm_context_resume_task3_size; 170 171 /* Only used when BRN 56279 or BRN 67381 present. */ 172 uint32_t pds_ctrl; 173 174 uint32_t view_idx; 175 176 /* Only used when feature TESSELLATION present */ 177 uint32_t pds_coeff_free_prog; 178 179 uint32_t padding; 180 }; 181 182 /** 183 * \brief Dummy region header registers. 184 */ 185 /* Only used when BRN 44455 or BRN 63027 present. */ 186 struct rogue_fwif_dummy_rgnhdr_init_geom_regs { 187 uint64_t te_psgregion_addr; 188 }; 189 190 /** 191 * \brief DM command for geometry processing phase of a render/3D operation. 192 * Represents the command data for a ROGUE_FWIF_CCB_CMD_TYPE_GEOM type client 193 * CCB command. 194 * 195 * The Rogue TA can be used to tile a whole scene's objects as per TA behavior 196 * on ROGUE. 197 */ 198 struct rogue_fwif_cmd_ta { 199 /** 200 * rogue_fwif_cmd_ta_3d_shared field must always be at the beginning of the 201 * struct. 202 * 203 * The command struct (rogue_fwif_cmd_ta) is shared between Client and 204 * Firmware. Kernel is unable to perform read/write operations on the 205 * command struct, the SHARED region is the only exception from this rule. 206 * This region must be the first member so that Kernel can easily access it. 207 * For more info, see pvr_cmd_ta_3d definition. 208 */ 209 struct rogue_fwif_cmd_ta_3d_shared cmd_shared; 210 211 struct rogue_fwif_ta_regs ALIGN_ATTR(8) geom_regs; 212 uint32_t ALIGN_ATTR(8) flags; 213 /** 214 * Holds the TA/3D fence value to allow the 3D partial render command 215 * to go through. 216 */ 217 struct rogue_fwif_ufo partial_render_ta_3d_fence; 218 219 /* Only used when BRN 44455 or BRN 63027 present. */ 220 struct rogue_fwif_dummy_rgnhdr_init_geom_regs 221 ALIGN_ATTR(8) dummy_rgnhdr_init_geom_regs; 222 223 /* Only used when BRN 61484 or BRN 66333 present. */ 224 uint32_t brn61484_66333_live_rt; 225 226 uint32_t padding; 227 }; 228 229 static_assert( 230 offsetof(struct rogue_fwif_cmd_ta, cmd_shared) == 0U, 231 "rogue_fwif_cmd_ta_3d_shared must be the first member of rogue_fwif_cmd_ta"); 232 233 static_assert( 234 sizeof(struct rogue_fwif_cmd_ta) <= ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE, 235 "kernel expects command size be increased to match current TA command size"); 236 237 /** 238 * \brief Configuration registers which need to be loaded by the firmware before 239 * ISP can be started. 240 */ 241 struct rogue_fwif_3d_regs { 242 /** 243 * All 32 bit values should be added in the top section. This then requires 244 * only a single ALIGN_ATTR(8) to align all the 64 bit values in the second 245 * section. 246 */ 247 uint32_t usc_pixel_output_ctrl; 248 249 #define ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL 8U 250 uint32_t usc_clear_register[ROGUE_MAXIMUM_OUTPUT_REGISTERS_PER_PIXEL]; 251 252 uint32_t isp_bgobjdepth; 253 uint32_t isp_bgobjvals; 254 uint32_t isp_aa; 255 /* Only used when feature S7_TOP_INFRASTRUCTURE present. */ 256 uint32_t isp_xtp_pipe_enable; 257 258 uint32_t isp_ctl; 259 260 /* Only used when feature CLUSTER_GROUPING present. */ 261 uint32_t tpu; 262 263 uint32_t event_pixel_pds_info; 264 265 uint32_t pixel_phantom; 266 267 uint32_t view_idx; 268 269 uint32_t event_pixel_pds_data; 270 271 /* Only used when BRN 65101 present. */ 272 uint32_t brn65101_event_pixel_pds_data; 273 274 /* Only used when feature GPU_MULTICORE_SUPPORT or BRN 47217 present. */ 275 uint32_t isp_oclqry_stride; 276 277 /* All values below the ALIGN_ATTR(8) must be 64 bit. */ 278 uint64_t ALIGN_ATTR(8) isp_scissor_base; 279 uint64_t isp_dbias_base; 280 uint64_t isp_oclqry_base; 281 uint64_t isp_zlsctl; 282 uint64_t isp_zload_store_base; 283 uint64_t isp_stencil_load_store_base; 284 285 /* Only used when feature ZLS_SUBTILE present. */ 286 uint64_t isp_zls_pixels; 287 288 /* 289 * Only used when feature FBCDC_ALGORITHM present and value < 3 or feature 290 * FB_CDC_V4 present. Additionally, BRNs 48754, 60227, 72310 and 72311 must 291 * not be present. 292 */ 293 uint64_t fb_cdc_zls; 294 295 #define ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS 3U 296 uint64_t pbe_word[8U][ROGUE_PBE_WORDS_REQUIRED_FOR_RENDERS]; 297 uint64_t tpu_border_colour_table; 298 uint64_t pds_bgnd[3U]; 299 300 /* Only used when BRN 65101 present. */ 301 uint64_t pds_bgnd_brn65101[3U]; 302 303 uint64_t pds_pr_bgnd[3U]; 304 305 /* Only used when feature ISP_ZLS_D24_S8_PACKING_OGL_MODE present. */ 306 uint64_t rgx_cr_blackpearl_fix; 307 308 /* Only used when BRN 62850 or 62865 present. */ 309 uint64_t isp_dummy_stencil_store_base; 310 311 /* Only used when BRN 66193 present. */ 312 uint64_t isp_dummy_depth_store_base; 313 314 /* Only used when BRN 67182 present. */ 315 uint32_t rgnhdr_single_rt_size; 316 /* Only used when BRN 67182 present. */ 317 uint32_t rgnhdr_scratch_offset; 318 }; 319 320 /** 321 * \brief DM command for fragment processing phase of a render/3D operation. 322 * Represents the command data for a ROGUE_FWIF_CCB_CMD_TYPE_FRAG type client 323 * CCB command. 324 */ 325 struct rogue_fwif_cmd_3d { 326 /** 327 * This struct is shared between Client and Firmware. 328 * Kernel is unable to perform read/write operations on the command struct, 329 * the SHARED region is our only exception from that rule. 330 * This region must be the first member so Kernel can easily access it. 331 * For more info, see rogue_fwif_cmd_ta_3d_shared definition. 332 */ 333 struct rogue_fwif_cmd_ta_3d_shared ALIGN_ATTR(8) cmd_shared; 334 335 struct rogue_fwif_3d_regs ALIGN_ATTR(8) regs; 336 /** command control flags. */ 337 uint32_t flags; 338 /** Stride IN BYTES for Z-Buffer in case of RTAs. */ 339 uint32_t zls_stride; 340 /** Stride IN BYTES for S-Buffer in case of RTAs. */ 341 uint32_t sls_stride; 342 343 /* Only used when SUPPORT_STRIP_RENDERING present. */ 344 uint8_t ui8FrameStripBuffer; 345 /* Only used when SUPPORT_STRIP_RENDERING present. */ 346 uint8_t ui8FrameStripIndex; 347 /* Only used when SUPPORT_STRIP_RENDERING present. */ 348 uint8_t ui8FrameStripMode; 349 350 /* Number of tiles to submit to GPU<N> before moving to GPU<N+1>. */ 351 uint32_t execute_count; 352 353 uint32_t padding; 354 }; 355 356 static_assert( 357 offsetof(struct rogue_fwif_cmd_3d, cmd_shared) == 0U, 358 "rogue_fwif_cmd_ta_3d_shared must be the first member of rogue_fwif_cmd_3d"); 359 360 static_assert( 361 sizeof(struct rogue_fwif_cmd_3d) <= ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE, 362 "kernel expects command size be increased to match current 3D command size"); 363 364 struct rogue_fwif_transfer_regs { 365 /** 366 * All 32 bit values should be added in the top section. This then requires 367 * only a single ALIGN_ATTR(8) to align all the 8 byte values in the second 368 * section. 369 */ 370 uint32_t isp_bgobjvals; 371 372 uint32_t usc_pixel_output_ctrl; 373 uint32_t usc_clear_register0; 374 uint32_t usc_clear_register1; 375 uint32_t usc_clear_register2; 376 uint32_t usc_clear_register3; 377 378 uint32_t isp_mtile_size; 379 uint32_t isp_render_origin; 380 uint32_t isp_ctl; 381 382 uint32_t isp_aa; 383 384 uint32_t event_pixel_pds_info; 385 386 uint32_t event_pixel_pds_code; 387 uint32_t event_pixel_pds_data; 388 389 uint32_t isp_render; 390 uint32_t isp_rgn; 391 /* FIXME: HIGH: RGX_FEATURE_GPU_MULTICORE_SUPPORT changes the structure's 392 * layout. Commenting out for now as it's not supported by 4.V.2.51. 393 */ 394 /* uint32_t frag_screen; */ 395 /** All values below the ALIGN_ATTR must be 64 bit. */ 396 uint64_t ALIGN_ATTR(8) pds_bgnd0_base; 397 uint64_t pds_bgnd1_base; 398 uint64_t pds_bgnd3_sizeinfo; 399 400 uint64_t isp_mtile_base; 401 /* FIXME: HIGH: RGX_PBE_WORDS_REQUIRED_FOR_TQS changes the structure's 402 * layout. 403 */ 404 /* TQ_MAX_RENDER_TARGETS * PBE_STATE_SIZE */ 405 uint64_t pbe_wordx_mrty[PVR_TRANSFER_MAX_RENDER_TARGETS * 406 ROGUE_NUM_PBESTATE_REG_WORDS]; 407 }; 408 409 /** 410 * \brief DM command for TQ/2D operation. Represents the command data for a 411 * ROGUE_FWIF_CCB_CMD_TYPE_TQ_3D type client CCB command. 412 */ 413 struct rogue_fwif_cmd_transfer { 414 struct rogue_fwif_cmd_common ALIGN_ATTR(8) cmn; 415 struct rogue_fwif_transfer_regs ALIGN_ATTR(8) regs; 416 417 uint32_t flags; 418 }; 419 420 static_assert( 421 offsetof(struct rogue_fwif_cmd_transfer, cmn) == 0U, 422 "rogue_fwif_cmd_common must be the first member of rogue_fwif_cmd_transfer"); 423 424 static_assert( 425 sizeof(struct rogue_fwif_cmd_transfer) <= 426 ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE, 427 "kernel expects command size be increased to match current TRANSFER command size"); 428 429 struct rogue_fwif_2d_regs { 430 uint64_t tla_cmd_stream; 431 uint64_t deprecated_0; 432 uint64_t deprecated_1; 433 uint64_t deprecated_2; 434 uint64_t deprecated_3; 435 /* FIXME: HIGH: FIX_HW_BRN_57193 changes the structure's layout. */ 436 uint64_t brn57193_tla_cmd_stream; 437 }; 438 439 struct rogue_fwif_cmd_2d { 440 struct rogue_fwif_cmd_common ALIGN_ATTR(8) cmn; 441 struct rogue_fwif_2d_regs ALIGN_ATTR(8) regs; 442 443 uint32_t flags; 444 }; 445 446 static_assert( 447 offsetof(struct rogue_fwif_cmd_2d, cmn) == 0U, 448 "rogue_fwif_cmd_common must be the first member of rogue_fwif_cmd_2d"); 449 450 static_assert( 451 sizeof(struct rogue_fwif_cmd_2d) <= ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE, 452 "kernel expects command size be increased to match current 2D command size"); 453 454 /** Command to handle aborts. */ 455 struct rogue_fwif_cmd_abort { 456 struct rogue_fwif_cmd_ta_3d_shared ALIGN_ATTR(8) cmd_shared; 457 }; 458 459 /*********************************************** 460 Host interface structures. 461 ***********************************************/ 462 463 /** 464 * Configuration registers which need to be loaded by the firmware before CDM 465 * can be started. 466 */ 467 struct rogue_fwif_cdm_regs { 468 uint64_t tpu_border_colour_table; 469 470 /* Only used when feature COMPUTE_MORTON_CAPABLE present. */ 471 uint64_t cdm_item; 472 473 /* Only used when feature CLUSTER_GROUPING present. */ 474 uint64_t compute_cluster; 475 476 /* Only used when feature TPU_DM_GLOBAL_REGISTERS present. */ 477 uint64_t tpu_tag_cdm_ctrl; 478 479 /* Only used when feature CDM_USER_MODE_QUEUE present. */ 480 uint64_t cdm_cb_queue; 481 482 /* 483 * Only used when feature CDM_USER_MODE_QUEUE is present and 484 * SUPPORT_TRUSTED_DEVICE is present and SUPPORT_SECURE_ALLOC_KM is not 485 * present. 486 */ 487 uint64_t cdm_cb_secure_queue; 488 489 /* Only used when feature CDM_USER_MODE_QUEUE present. */ 490 uint64_t cdm_cb_base; 491 /* Only used when feature CDM_USER_MODE_QUEUE present. */ 492 uint64_t cdm_cb; 493 494 /* Only used when feature CDM_USER_MODE_QUEUE is not present. */ 495 uint64_t cdm_ctrl_stream_base; 496 497 uint64_t cdm_context_state_base_addr; 498 499 /* Only used when BRN 49927 is present. */ 500 uint32_t tpu; 501 502 uint32_t cdm_resume_pds1; 503 }; 504 505 /** 506 * \brief DM command for Compute operation. Represents the command data for a 507 * ROGUE_FWIF_CCB_CMD_TYPE_CDM type client CCB command. 508 * 509 * Rouge Compute command. 510 */ 511 struct rogue_fwif_cmd_compute { 512 struct rogue_fwif_cmd_common ALIGN_ATTR(8) cmn; 513 struct rogue_fwif_cdm_regs ALIGN_ATTR(8) regs; 514 uint32_t ALIGN_ATTR(8) flags; 515 516 /* Only used when feature UNIFIED_STORE_VIRTUAL_PARTITIONING present. */ 517 uint32_t num_temp_regions; 518 519 /* Only used when feature CDM_USER_MODE_QUEUE present. */ 520 uint32_t stream_start_offset; 521 522 /* Number of tiles to submit to GPU<N> before moving to GPU<N+1>. */ 523 /* Only used when feature GPU_MULTICORE_SUPPORT present. */ 524 uint32_t execute_count; 525 }; 526 527 static_assert( 528 offsetof(struct rogue_fwif_cmd_compute, cmn) == 0U, 529 "rogue_fwif_cmd_common must be the first member of rogue_fwif_cmd_compute"); 530 531 static_assert( 532 sizeof(struct rogue_fwif_cmd_compute) <= 533 ROGUE_FWIF_DM_INDEPENDENT_KICK_CMD_SIZE, 534 "kernel expects command size be increased to match current COMPUTE command size"); 535 536 /* TODO: Rename the RGX_* macros in the comments once they are imported. */ 537 /* Applied to RGX_CR_VDM_SYNC_PDS_DATA_BASE. */ 538 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_PDS_HEAP_VDM_SYNC_OFFSET_BYTES 0U 539 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_PDS_HEAP_VDM_SYNC_MAX_SIZE_BYTES 128U 540 541 /** Applied to RGX_CR_EVENT_PIXEL_PDS_CODE. */ 542 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_PDS_HEAP_EOT_OFFSET_BYTES 128U 543 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_PDS_HEAP_EOT_MAX_SIZE_BYTES 128U 544 545 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_PDS_HEAP_TOTAL_BYTES 4096U 546 547 /** Pointed to by PDS code at RGX_CR_VDM_SYNC_PDS_DATA_BASE. */ 548 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_USC_HEAP_VDM_SYNC_OFFSET_BYTES 0U 549 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_USC_HEAP_VDM_SYNC_MAX_SIZE_BYTES 128U 550 551 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_USC_HEAP_TOTAL_BYTES 4096U 552 553 /** 554 * Applied to RGX_CR_MCU_FENCE, and RGX_CR_PM_MTILE_ARRAY 555 * (defined(RGX_FEATURE_SIMPLE_INTERNAL_PARAMETER_FORMAT)). 556 */ 557 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_GENERAL_HEAP_FENCE_OFFSET_BYTES 0U 558 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_GENERAL_HEAP_FENCE_MAX_SIZE_BYTES 128U 559 560 /** Applied to RGX_CR_TPU_YUV_CSC_COEFFICIENTS. */ 561 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_GENERAL_HEAP_YUV_CSC_OFFSET_BYTES 128U 562 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_GENERAL_HEAP_YUV_CSC_MAX_SIZE_BYTES 1024U 563 564 #define ROGUE_FWIF_HEAP_FIXED_OFFSET_GENERAL_HEAP_TOTAL_BYTES 4096U 565 566 #endif /* PVR_ROGUE_FWIF_H */ 567