1 /* 2 * Copyright (c) 2021 HPMicro 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef HPM_RTL8211_REGS_H 9 #define HPM_RTL8211_REGS_H 10 11 /* RTL Register Definitions */ 12 #define RTL8211_REG_BMCR (0U) /* Basic Mode Control Register */ 13 #define RTL8211_REG_BMSR (1U) /* Basic Mode Status Register */ 14 #define RTL8211_REG_PHYID1 (2U) /* PHY Identifier Register 1 */ 15 #define RTL8211_REG_PHYID2 (3U) /* PHY Identifier Register 2 */ 16 #define RTL8211_REG_ANAR (4U) /* Auto-Negotiation Advertising Register */ 17 #define RTL8211_REG_ANLPAR (5U) /* Auto-Negotiation Link Partner Ability Register */ 18 #define RTL8211_REG_ANER (6U) /* Auto-Negotiation Expansion Register */ 19 #define RTL8211_REG_ANNPTR (7U) /* Auto-Negotiation Next Page Transmit Register */ 20 #define RTL8211_REG_ANNPRR (8U) /* Auto-Negotiation Next Page Receive Register */ 21 #define RTL8211_REG_GBCR (9U) /* 1000Base-T Control Register */ 22 #define RTL8211_REG_GBSR (10U) /* 1000Base-T Status Register */ 23 24 #define RTL8211_REG_MACR (13U) /* MMD Access Control Register */ 25 #define RTL8211_REG_MAADR (14U) /* MMD Access Address Data Register */ 26 #define RTL8211_REG_GBESR (15U) /* 1000Base-T Extended Status Register */ 27 #define RTL8211_REG_PHYCR (16U) /* PHY Specific Control Register */ 28 #define RTL8211_REG_PHYSR (17U) /* PHY Specific Status Register */ 29 #define RTL8211_REG_INER (18U) /* Interrupt Enable Register */ 30 #define RTL8211_REG_INSR (19U) /* Interrupt Status Register */ 31 #define RTL8211_REG_RXERC (24U) /* Receive Error Counter */ 32 #define RTL8211_REG_PAGSEL (31U) /* Page Select Register */ 33 34 /* RTL MMD Register Definitions */ 35 #define RTL8211_MMD_REG_PC1R (0U) /* PCS Control 1 Register */ 36 #define RTL8211_MMD_REG_PS1R (1U) /* PCS Status 1 Register */ 37 #define RTL8211_MMD_REG_EEECR (20U) /* EEE Capability Register */ 38 #define RTL8211_MMD_REG_EEEWER (22U) /* EEE Wake Error Register */ 39 #define RTL8211_MMD_REG_EEEAR (60U) /* EEE Advertisement Register */ 40 #define RTL8211_MMD_REG_EEELPAR (61U) /* EEE Link Partner Ability Register */ 41 42 /* Bitfield definition for register: BMCR */ 43 /* 44 * Reset (RW) 45 * 46 * 1: PHY reset 47 * 0: Normal operation 48 * Register 0 (BMCR) and register 1 (BMSR) will return to default 49 * values after a software reset (set Bit15 to 1). 50 * This action may change the internal PHY state and the state of the 51 * physical link associated with the PHY. 52 */ 53 #define RTL8211_BMCR_RESET_MASK (0x8000U) 54 #define RTL8211_BMCR_RESET_SHIFT (15U) 55 #define RTL8211_BMCR_RESET_SET(x) (((uint32_t)(x) << RTL8211_BMCR_RESET_SHIFT) & RTL8211_BMCR_RESET_MASK) 56 #define RTL8211_BMCR_RESET_GET(x) (((uint32_t)(x) & RTL8211_BMCR_RESET_MASK) >> RTL8211_BMCR_RESET_SHIFT) 57 58 /* 59 * Loopback (RW) 60 * 61 * Loopback Mode. 62 * 1: Enable PCS loopback mode 63 * 0: Disable PCS loopback mode 64 */ 65 #define RTL8211_BMCR_LOOPBACK_MASK (0x4000U) 66 #define RTL8211_BMCR_LOOPBACK_SHIFT (14U) 67 #define RTL8211_BMCR_LOOPBACK_SET(x) (((uint32_t)(x) << RTL8211_BMCR_LOOPBACK_SHIFT) & RTL8211_BMCR_LOOPBACK_MASK) 68 #define RTL8211_BMCR_LOOPBACK_GET(x) (((uint32_t)(x) & RTL8211_BMCR_LOOPBACK_MASK) >> RTL8211_BMCR_LOOPBACK_SHIFT) 69 70 /* 71 * Speed[0] (RW) 72 * 73 * Speed Select Bit 0. 74 * In forced mode, i.e., when Auto-Negotiation is disabled, bits 6 and 13 75 * determine device speed selection. 76 */ 77 #define RTL8211_BMCR_SPEED0_MASK (0x2000U) 78 #define RTL8211_BMCR_SPEED0_SHIFT (13U) 79 #define RTL8211_BMCR_SPEED0_SET(x) (((uint32_t)(x) << RTL8211_BMCR_SPEED0_SHIFT) & RTL8211_BMCR_SPEED0_MASK) 80 #define RTL8211_BMCR_SPEED0_GET(x) (((uint32_t)(x) & RTL8211_BMCR_SPEED0_MASK) >> RTL8211_BMCR_SPEED0_SHIFT) 81 82 /* 83 * ANE (RW) 84 * 85 * Auto-Negotiation Enable. 86 * 1: Enable Auto-Negotiation 87 * 0: Disable Auto-Negotiation 88 */ 89 #define RTL8211_BMCR_ANE_MASK (0x1000U) 90 #define RTL8211_BMCR_ANE_SHIFT (12U) 91 #define RTL8211_BMCR_ANE_SET(x) (((uint32_t)(x) << RTL8211_BMCR_ANE_SHIFT) & RTL8211_BMCR_ANE_MASK) 92 #define RTL8211_BMCR_ANE_GET(x) (((uint32_t)(x) & RTL8211_BMCR_ANE_MASK) >> RTL8211_BMCR_ANE_SHIFT) 93 94 /* 95 * PWD (RW) 96 * 97 * Power Down. 98 * 1: Power down (only Management Interface and logic are active; link 99 * is down) 100 * 0: Normal operation 101 */ 102 #define RTL8211_BMCR_PWD_MASK (0x0800U) 103 #define RTL8211_BMCR_PWD_SHIFT (11U) 104 #define RTL8211_BMCR_PWD_SET(x) (((uint32_t)(x) << RTL8211_BMCR_PWD_SHIFT) & RTL8211_BMCR_PWD_MASK) 105 #define RTL8211_BMCR_PWD_GET(x) (((uint32_t)(x) & RTL8211_BMCR_PWD_MASK) >> RTL8211_BMCR_PWD_SHIFT) 106 107 /* 108 * Isolate (RW) 109 * 110 * Isolate. 111 * 1: RGMII/GMII interface is isolated; the serial management interface 112 * (MDC, MDIO) is still active. When this bit is asserted, the 113 * RTL8211E/RTL8211EG ignores TXD[7:0], and TXCLT inputs, and 114 * presents a high impedance on TXC, RXC, RXCLT, RXD[7:0]. 115 * 0: Normal operation 116 */ 117 #define RTL8211_BMCR_ISOLATE_MASK (0x0400U) 118 #define RTL8211_BMCR_ISOLATE_SHIFT (10U) 119 #define RTL8211_BMCR_ISOLATE_SET(x) (((uint32_t)(x) << RTL8211_BMCR_ISOLATE_SHIFT) & RTL8211_BMCR_ISOLATE_MASK) 120 #define RTL8211_BMCR_ISOLATE_GET(x) (((uint32_t)(x) & RTL8211_BMCR_ISOLATE_MASK) >> RTL8211_BMCR_ISOLATE_SHIFT) 121 122 /* 123 * Restart_AN (RW) 124 * 125 * Restart Auto-Negotiation. 126 * 1: Restart Auto-Negotiation 127 * 0: Normal operation 128 */ 129 #define RTL8211_BMCR_RESTART_AN_MASK (0x0200U) 130 #define RTL8211_BMCR_RESTART_AN_SHIFT (9U) 131 #define RTL8211_BMCR_RESTART_AN_SET(x) (((uint32_t)(x) << RTL8211_BMCR_RESTART_AN_SHIFT) & RTL8211_BMCR_RESTART_AN_MASK) 132 #define RTL8211_BMCR_RESTART_AN_GET(x) (((uint32_t)(x) & RTL8211_BMCR_RESTART_AN_MASK) >> RTL8211_BMCR_RESTART_AN_SHIFT) 133 134 /* 135 * Duplex (RW) 136 * 137 * Duplex Mode. 138 * 1: Full Duplex operation 139 * 0: Half Duplex operation 140 * This bit is valid only in force mode, i.e., NWay is disabled. 141 */ 142 #define RTL8211_BMCR_DUPLEX_MASK (0x0100U) 143 #define RTL8211_BMCR_DUPLEX_SHIFT (8U) 144 #define RTL8211_BMCR_DUPLEX_SET(x) (((uint32_t)(x) << RTL8211_BMCR_DUPLEX_SHIFT) & RTL8211_BMCR_DUPLEX_MASK) 145 #define RTL8211_BMCR_DUPLEX_GET(x) (((uint32_t)(x) & RTL8211_BMCR_DUPLEX_MASK) >> RTL8211_BMCR_DUPLEX_SHIFT) 146 147 /* 148 * Collision Test (RW) 149 * 150 * Collision Test. 151 * 1: Collision test enabled 152 * 0: Normal operation 153 * When set, this bit will cause the COL signal to be asserted in response 154 * to the assertion of TXEN within 512-bit times. The COL signal will be 155 * de-asserted within 4-bit times in response to the de-assertion of 156 * TXEN. 157 */ 158 #define RTL8211_BMCR_COLLISION_TEST_MASK (0x0080U) 159 #define RTL8211_BMCR_COLLISION_TEST_SHIFT (7U) 160 #define RTL8211_BMCR_COLLISION_TEST_SET(x) (((uint32_t)(x) << RTL8211_BMCR_COLLISION_TEST_SHIFT) & RTL8211_BMCR_COLLISION_TEST_MASK) 161 #define RTL8211_BMCR_COLLISION_TEST_GET(x) (((uint32_t)(x) & RTL8211_BMCR_COLLISION_TEST_MASK) >> RTL8211_BMCR_COLLISION_TEST_SHIFT) 162 163 /* 164 * Speed[1] (RW) 165 * 166 * Speed Select Bit 1. 167 * Refer to bit 0.13. 168 */ 169 #define RTL8211_BMCR_SPEED1_MASK (0x0040U) 170 #define RTL8211_BMCR_SPEED1_SHIFT (6U) 171 #define RTL8211_BMCR_SPEED1_SET(x) (((uint32_t)(x) << RTL8211_BMCR_SPEED1_SHIFT) & RTL8211_BMCR_SPEED1_MASK) 172 #define RTL8211_BMCR_SPEED1_GET(x) (((uint32_t)(x) & RTL8211_BMCR_SPEED1_MASK) >> RTL8211_BMCR_SPEED1_SHIFT) 173 174 /* Bitfield definition for register: PHYID1 */ 175 /* 176 * OUI_MSB (RO) 177 * 178 * Organizationally Unique Identifier Bit 3:18. 179 * Always 0000000000011100. 180 */ 181 #define RTL8211_PHYID1_OUI_MSB_MASK (0xFFFFU) 182 #define RTL8211_PHYID1_OUI_MSB_SHIFT (0U) 183 #define RTL8211_PHYID1_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8211_PHYID1_OUI_MSB_MASK) >> RTL8211_PHYID1_OUI_MSB_SHIFT) 184 185 /* Bitfield definition for register: PHYID2 */ 186 /* 187 * OUI_LSB (RO) 188 * 189 * Organizationally Unique Identifier Bit 19:24. 190 * Always 110010. 191 */ 192 #define RTL8211_PHYID2_OUI_MSB_MASK (0xFC00U) 193 #define RTL8211_PHYID2_OUI_MSB_SHIFT (10U) 194 #define RTL8211_PHYID2_OUI_MSB_GET(x) (((uint32_t)(x) & RTL8211_PHYID2_OUI_MSB_MASK) >> RTL8211_PHYID2_OUI_MSB_SHIFT) 195 196 #endif /* HPM_RTL8211_REGS_H */