1 /* 2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef I2S_AIAO_HI35XX_H 17 #define I2S_AIAO_HI35XX_H 18 19 #include "i2s_if.h" 20 #include "i2s_hi35xx.h" 21 #include "los_vm_zone.h" 22 23 24 #ifdef __cplusplus 25 #if __cplusplus 26 extern "C" { 27 #endif /* __cplusplus */ 28 #endif /* __cplusplus */ 29 30 #define I2S_AIAO_MAX_REG_SIZE (64 * 1024) 31 #define I2S_DDR_BUFF_ALIGN_SIZE (128 * 8) 32 #define I2S_RX_BUFF_SIZE 0x8000 33 #define I2X_RX_TRANS_SIZE 0x140 34 #define I2S_AIAO_BUFF_SIZE 0x8000 35 #define I2S_TX_DATA_MIN 128 36 #define I2S_TX_BUFF_SIZE 0x8000 37 #define I2S_TX_TRANS_SIZE 0x400 38 #define I2S_BUFF_DATA_HEAD_1 1 39 #define I2S_BUFF_DATA_HEAD_2 2 40 #define I2S_BUFF_DATA_TAIL_3 3 41 #define I2S_BUFF_DATA_TAIL_2 2 42 #define I2S_BUFF_DATA_TAIL_1 1 43 44 45 #define I2S_AIAO_SAMPLE_RATE_8 8 46 #define I2S_AIAO_SAMPLE_RATE_16 16 47 #define I2S_AIAO_SAMPLE_RATE_32 32 48 #define I2S_AIAO_SAMPLE_RATE_48 48 49 #define I2S_AIAO_SAMPLE_RATE_96 96 50 #define I2S_AIAO_SAMPLE_RATE_192 192 51 52 53 #define I2S_CRG_CFG0_00 0x0100 54 #define AIAO_MCLK_DIV 0x152EF0 55 56 #define I2S_AIAO_INT_ENA 0x0 57 #define I2S_AIAO_INT_ENA_RX_CH0 (0x1 << 0) 58 #define I2S_AIAO_INT_ENA_RX_CH0_SHIFT 0 59 #define I2S_AIAO_INT_ENA_TX_CH0 (0x1 << 16) 60 #define I2S_AIAO_INT_ENA_TX_CH0_SHIFT 16 61 #define I2S_AIAO_INT_ENA_TX_CH1 (0x1 << 17) 62 #define I2S_AIAO_INT_ENA_TX_CH1_SHIFT 17 63 64 #define I2S_AIAO_INT_STARUS 0x0004 65 66 #define I2S_AIAO_SWITCH_RX_BCLK 0x28 67 #define INNER_BCLK_WS_SEL_RX_00 (0xf << 0) 68 #define INNER_BCLK_WS_SEL_RX_00_SHIFT 0 69 70 #define I2S_AIAO_PLL_FEQ 1188 /* 1188M */ 71 72 /* I2S_CRG_CFG1_00 */ 73 #define I2S_CRG_CFG1_00 0x0104 74 #define I2S_CRG_CFG1_00_VAL 0x0000c133 75 #define I2S_AIAO_SRST_REQ (0x1 << 9) 76 #define I2S_AIAO_SRST_REQ_SHIFT 9 77 #define I2S_AIAO_CKEN (0x1 << 8) 78 #define I2S_AIAO_CKEN_SHIFT 8 79 #define I2S_AIAO_FSCLK_DIV (0x7 << 4) 80 #define I2S_AIAO_FSCLK_DIV_SHIFT 4 81 #define I2S_AIAO_BCLK_DIV (0xF << 0) 82 #define I2S_AIAO_BCLK_DIV_SHIFT 0 83 84 #define I2S_AIAO_SRST_REQ_NO_RESET 0 85 #define I2S_AIAO_CKEN_OPEN 1 86 87 #define I2S_CRG_CFG0_08 0x0140 88 #define I2S_CRG_CFG1_08 0x0144 89 90 91 /* RX_IF_ATTR1 */ 92 #define RX_IF_ATTR1 0x1000 93 #define RX_IF_ATTR1_VAL 0xE4800014 94 #define RX_SD_SOURCE_SEL (0xf << 20) 95 #define RX_SD_SOURCE_SEL_SHIFT 20 96 #define RX_SD_SOURCE_SEL_NORMAL 0x8 97 #define RX_TRACKMODE (0x7 << 16) 98 #define RX_TRACKMODE_SHIFT 16 99 #define RX_SD_OFFSET (0x255 << 8) 100 #define RX_SD_OFFSET_SHIFT 8 101 #define RX_CH_NUM (0x7 << 4) 102 #define RX_CH_NUM_SHIFT 4 103 #define RX_I2S_PRECISION (0x3 << 2) 104 #define RX_I2S_PRECISION_SHIFT 2 105 #define RX_MODE (0x3 << 0) 106 #define RX_MODE_SHIFT 0 107 108 #define AIAO_RX_SD_OFFSET_LSB 0x0 109 #define AIAO_RX_SD_OFFSET_STD 0x1 110 111 #define AIAO_RX_CH_NUM_1 0x0 112 #define AIAO_RX_CH_NUM_2 0x1 113 114 #define AIAO_RX_I2S_PRECISION_I2S_16 0x1 115 #define AIAO_RX_I2S_PRECISION_I2S_24 0x2 116 #define AIAO_RX_I2S_PRECISION_PCM_16 0x1 117 118 #define AIAO_RX_MODE_I2S 0x0 119 #define AIAO_RX_MODE_PCM 0x1 120 121 122 /* TX_IF_ATTR1 */ 123 #define TX_IF_ATTR1 0x2000 124 #define TX_CH_NUM (0x3 << 4) 125 #define TX_CH_NUM_SHIFT 4 126 #define TX_I2S_PRECISION (0x3 << 2) 127 #define TX_I2S_PRECISION_SHIFT 2 128 #define TX_MODE (0x3 << 0) 129 #define TX_MODE_SHIFT 0 130 131 #define RX_DSP_CTRL 0x1004 132 #define RX_DSP_CTRL_VAL 0x10000000 133 #define RX_DISABLE_DONE (0x1 << 29) 134 #define RX_DISABLE_DONE_SHIFT 29 135 #define RX_ENABLE (0x1 << 28) 136 #define RX_ENABLE_SHIFT 28 137 #define RX_DISABLE (0x1 << 28) 138 #define RX_DISABLE_SHIFT 28 139 140 #define RX_BUFF_ASDDR 0x1080 141 #define RX_BUFF_ASDDR_VAL 0x00000100 142 143 #define RX_BUFF_SIZE 0x1084 144 #define RX_BUFF_SIZE_VAL 0x0000F000 145 146 #define RX_BUFF_WPTR 0x1088 147 #define RX_BUFF_WPTR_VAL 0x0 148 149 #define RX_BUFF_RPTR 0x108C 150 #define RX_BUFF_RPTR_VAL 0x0 151 152 #define RX_TRANS_SIZE 0x1094 153 #define RX_TRANS_SIZE_VAL 0x00000F00 154 155 #define RX_INT_ENA 0x10A0 156 #define RX_INT_ENA_VAL 0x00000001 157 #define RX_TRANS_INT_ENA (0x1 << 0) 158 #define RX_TRANS_INT_ENA_SHIFT 0 159 #define RX_STOP_INT_ENA (0x1 << 5) 160 #define RX_STOP_INT_ENA_SHIFT 5 161 162 #define RX_INT_STATUS 0x10A8 163 #define RX_STOP_INT_STATUS (0x1 << 5) 164 #define RX_STOP_INT_STATUS_SHIFT 5 165 #define RX_TRANS_INT_STATUS (0x1 << 0) 166 #define RX_TRANS_INT_STATUS_SHIFT 0 167 168 #define RX_INT_CLR 0x10AC 169 #define RX_INT_CLR_CLEAR 0x000000FF 170 171 #define TX_DSP_CTRL 0x2004 172 #define TX_DISABLE_DONE (0x1 << 29) 173 #define TX_DISABLE_DONE_SHIFT 29 174 #define TX_ENABLE (0x1 << 28) 175 #define TX_ENABLE_SHIFT 28 176 #define TX_DISABLE (0x1 << 28) 177 #define TX_DISABLE_SHIFT 28 178 #define AIAO_STOP_RX_TX_MSLEEP 10 179 180 #define TX_BUFF_SADDR 0x2080 181 #define TX_BUFF_SIZE 0x2084 182 #define TX_BUFF_WPTR 0x2088 183 #define TX_BUFF_RPTR 0x208C 184 #define TX_TRANS_SIZE 0x2094 185 186 #define TX_INT_ENA 0x20A0 187 #define TX_TRANS_INT_ENA (0x1 << 0) 188 #define TX_TRANS_INT_ENA_SHIFT 0 189 #define TX_STOP_INT_ENA (0x1 << 5) 190 #define TX_STOP_INT_ENA_SHIFT 5 191 192 #define TX_INT_STATUS 0x20A8 193 #define TX_STOP_INT_STATUS (0x1 << 5) 194 #define TX_STOP_INT_STATUS_SHIFT 5 195 #define TX_TRANS_INT_STATUS (0x1 << 0) 196 #define TX_TRANS_INT_STATUS_SHIFT 0 197 198 #define TX_INT_CLR 0x20AC 199 #define TX_INT_CLR_CLEAR 0x000000FF 200 201 #define AIAO_MCLK_48K_256FS_1188M 0x00152EF0 /* 48k * 256 */ 202 #define AIAO_MCLK_441K_256FS_1188M 0x00137653 /* 44.1k * 256 */ 203 #define AIAO_MCLK_32K_256FS_1188M 0x000E1F4B /* 32k * 256 */ 204 205 #define AIAO_MCLK_48K_320FS_1188M 0x001A7AAC /* 48k * 320 */ 206 #define AIAO_MCLK_441K_320FS_1188M 0x00185FA0 /* 44.1k * 320 */ 207 #define AIAO_MCLK_32K_320FS_1188M 0x0011A71E /* 32k * 320 */ 208 209 #define RX_IF_ATTR1_INIT_VAL 0xe4880014 210 #define TX_IF_ATTR1_INIT_VAL 0xe4000054 211 #define TX_DSP_CTRL_INIT_VAL 0x7900 212 #define RX_DSP_CTRL_INIT_VAL 0x0 213 #define I2S_CRG_CFG0_08_INIT_VAL 0x152ef0 214 #define I2S_CRG_CFG1_08_INIT_VAL 0xc115 215 #define I2S_CRG_CFG0_00_INIT_VAL 0x152ef0 216 #define I2S_CRG_CFG1_00_INIT_VAL 0xc115 217 218 219 void GetI2sAiaoRxInfo(const struct I2sConfigInfo *i2sCfg); 220 void GetI2sAiaoTxInfo(const struct I2sConfigInfo *i2sCfg); 221 int32_t Hi35xxSampleRateShift(enum I2sSampleRate sampleRate); 222 int32_t Hi35xxSetCfgAiaoFsclkDiv(uint8_t *pAiaoFsclkDiv, uint16_t fsNum); 223 int32_t Hi35xxSetCfgAiaoBclkDiv(uint8_t *pAiaoBclkDiv, uint16_t bclkNum); 224 uint32_t AiaoGetRxIfAttri(struct I2sConfigInfo *i2sCfg, enum I2sProtocolType type, enum I2sChannelMode channelMode, 225 enum I2sChannelIfMode channelIfMode, uint8_t samplePrecision); 226 void CfgSetI2sCrgCfg000(const struct I2sConfigInfo *i2sCfg, enum I2slFsSel i2slFsSel, enum I2sSampleRate sampleRate); 227 void CfgSetI2sCrgCfg100(const struct I2sConfigInfo *i2sCfg); 228 void CfgSetRxIfSAttr1(const struct I2sConfigInfo *i2sCfg); 229 void CfgSetI2sCrgCfg008(const struct I2sConfigInfo *i2sCfg, enum I2slFsSel i2slFsSel, enum I2sSampleRate sampleRate); 230 void CfgSetI2sCrgCfg108(const struct I2sConfigInfo *i2sCfg); 231 void CfgSetTxIfSAttr1(const struct I2sConfigInfo *i2sCfg); 232 void CfgSetTxBuffInfo(struct I2sConfigInfo *i2sCfg); 233 void CfgSetRxBuffInfo(struct I2sConfigInfo *i2sCfg); 234 void CfgStartRecord(const struct I2sConfigInfo *i2sCfg); 235 void CfgStartPlay(struct I2sConfigInfo *i2sCfg); 236 int32_t Hi35xxI2sReadGetBuff(struct I2sConfigInfo *i2sInfo); 237 int32_t Hi35xxI2sWriteGetBuff(struct I2sConfigInfo *i2sInfo); 238 int32_t GetRxBuffData(struct I2sConfigInfo *i2sCfg, struct I2sMsg *msgs, uint32_t *pOffset); 239 int32_t WriteTxBuffData(struct I2sConfigInfo *i2sCfg, struct I2sMsg *msgs, 240 uint32_t txWptr, uint32_t *pOffset); 241 int32_t UpdateTxBuffData(struct I2sConfigInfo *i2sCfg, struct I2sMsg *msgs, uint32_t *pOffset); 242 uint32_t AiaoInit(struct I2sConfigInfo *i2sCfg); 243 244 #ifdef __cplusplus 245 #if __cplusplus 246 } 247 #endif /* __cplusplus */ 248 #endif /* __cplusplus */ 249 #endif /* I2S_AIAO_HI35XX_H */ 250