| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize() local
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| D | MipsSEFrameLowering.cpp | 198 unsigned RegSize) { in expandLoadACC()
223 unsigned RegSize) { in expandStoreACC()
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| D | MipsCallLowering.cpp | 505 unsigned RegSize = 4; in lowerFormalArguments() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 137 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 482 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0; in getRegSizeInBits() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1703 unsigned RegSize; in emitLogicalOp_ri() local
4124 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4231 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4352 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
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| D | AArch64FrameLowering.cpp | 2405 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves() local
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| D | AArch64InstructionSelector.cpp | 3295 unsigned RegSize = MRI.getType(LHS).getSizeInBits(); in emitTST() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 233 unsigned RegSize, SpillSize, SpillAlignment; member
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate()
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 918 unsigned RegSize = 0; member
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 190 int RegSize; in sizeOfSPAdjustment() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 807 unsigned RegSize = RegVT.getSizeInBits(); in LowerFormalArguments() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 5078 unsigned RegSize = TRI.getRegSizeInBits(*RC); in isNonFoldablePartialRegisterLoad() local
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| D | X86ISelLowering.cpp | 36723 unsigned RegSize = std::max(128u, (unsigned)InVT.getSizeInBits()); in createPSADBW() local
36966 unsigned RegSize = 128; in combineBasicSADPattern() local
44847 unsigned RegSize = 128; in combineLoopSADPattern() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 136 unsigned RegSize = RegTy.getSizeInBits(); in extractParts() local
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| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.cpp | 849 unsigned RegSize = RegisterVT.getScalarSizeInBits(); in getCopyFromRegs() local
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