1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef __TIMG_REG_H__ 15 #define __TIMG_REG_H__ 16 #include "soc.h" 17 18 /* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */ 19 #define TIMG_WDT_WKEY_VALUE 0x50D83AA1 20 21 /* Possible values for TIMG_WDT_STGx */ 22 #define TIMG_WDT_STG_SEL_OFF 0 23 #define TIMG_WDT_STG_SEL_INT 1 24 #define TIMG_WDT_STG_SEL_RESET_CPU 2 25 #define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 26 27 /* Possible values for TIMG_WDT_CPU_RESET_LENGTH and TIMG_WDT_SYS_RESET_LENGTH */ 28 #define TIMG_WDT_RESET_LENGTH_100_NS 0 29 #define TIMG_WDT_RESET_LENGTH_200_NS 1 30 #define TIMG_WDT_RESET_LENGTH_300_NS 2 31 #define TIMG_WDT_RESET_LENGTH_400_NS 3 32 #define TIMG_WDT_RESET_LENGTH_500_NS 4 33 #define TIMG_WDT_RESET_LENGTH_800_NS 5 34 #define TIMG_WDT_RESET_LENGTH_1600_NS 6 35 #define TIMG_WDT_RESET_LENGTH_3200_NS 7 36 37 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) 38 #define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) 39 /* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ 40 /*description: When set timer 0 time-base counter is enabled*/ 41 #define TIMG_T0_EN (BIT(31)) 42 #define TIMG_T0_EN_M (BIT(31)) 43 #define TIMG_T0_EN_V 0x1 44 #define TIMG_T0_EN_S 31 45 /* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ 46 /*description: When set timer 0 time-base counter increment. When cleared timer 47 0 time-base counter decrement.*/ 48 #define TIMG_T0_INCREASE (BIT(30)) 49 #define TIMG_T0_INCREASE_M (BIT(30)) 50 #define TIMG_T0_INCREASE_V 0x1 51 #define TIMG_T0_INCREASE_S 30 52 /* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ 53 /*description: When set timer 0 auto-reload at alarming is enabled*/ 54 #define TIMG_T0_AUTORELOAD (BIT(29)) 55 #define TIMG_T0_AUTORELOAD_M (BIT(29)) 56 #define TIMG_T0_AUTORELOAD_V 0x1 57 #define TIMG_T0_AUTORELOAD_S 29 58 /* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ 59 /*description: Timer 0 clock (T0_clk) prescale value.*/ 60 #define TIMG_T0_DIVIDER 0x0000FFFF 61 #define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S)) 62 #define TIMG_T0_DIVIDER_V 0xFFFF 63 #define TIMG_T0_DIVIDER_S 13 64 /* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ 65 /*description: When set edge type interrupt will be generated during alarm*/ 66 #define TIMG_T0_EDGE_INT_EN (BIT(12)) 67 #define TIMG_T0_EDGE_INT_EN_M (BIT(12)) 68 #define TIMG_T0_EDGE_INT_EN_V 0x1 69 #define TIMG_T0_EDGE_INT_EN_S 12 70 /* TIMG_T0_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */ 71 /*description: When set level type interrupt will be generated during alarm*/ 72 #define TIMG_T0_LEVEL_INT_EN (BIT(11)) 73 #define TIMG_T0_LEVEL_INT_EN_M (BIT(11)) 74 #define TIMG_T0_LEVEL_INT_EN_V 0x1 75 #define TIMG_T0_LEVEL_INT_EN_S 11 76 /* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ 77 /*description: When set alarm is enabled*/ 78 #define TIMG_T0_ALARM_EN (BIT(10)) 79 #define TIMG_T0_ALARM_EN_M (BIT(10)) 80 #define TIMG_T0_ALARM_EN_V 0x1 81 #define TIMG_T0_ALARM_EN_S 10 82 83 #define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004) 84 /* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 85 /*description: Register to store timer 0 time-base counter current value lower 32 bits.*/ 86 #define TIMG_T0_LO 0xFFFFFFFF 87 #define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S)) 88 #define TIMG_T0_LO_V 0xFFFFFFFF 89 #define TIMG_T0_LO_S 0 90 91 #define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008) 92 /* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 93 /*description: Register to store timer 0 time-base counter current value higher 32 bits.*/ 94 #define TIMG_T0_HI 0xFFFFFFFF 95 #define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S)) 96 #define TIMG_T0_HI_V 0xFFFFFFFF 97 #define TIMG_T0_HI_S 0 98 99 #define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c) 100 /* TIMG_T0_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */ 101 /*description: Write any value will trigger a timer 0 time-base counter value 102 update (timer 0 current value will be stored in registers above)*/ 103 #define TIMG_T0_UPDATE 0xFFFFFFFF 104 #define TIMG_T0_UPDATE_M ((TIMG_T0_UPDATE_V)<<(TIMG_T0_UPDATE_S)) 105 #define TIMG_T0_UPDATE_V 0xFFFFFFFF 106 #define TIMG_T0_UPDATE_S 0 107 108 #define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010) 109 /* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 110 /*description: Timer 0 time-base counter value lower 32 bits that will trigger the alarm*/ 111 #define TIMG_T0_ALARM_LO 0xFFFFFFFF 112 #define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S)) 113 #define TIMG_T0_ALARM_LO_V 0xFFFFFFFF 114 #define TIMG_T0_ALARM_LO_S 0 115 116 #define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014) 117 /* TIMG_T0_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 118 /*description: Timer 0 time-base counter value higher 32 bits that will trigger the alarm*/ 119 #define TIMG_T0_ALARM_HI 0xFFFFFFFF 120 #define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S)) 121 #define TIMG_T0_ALARM_HI_V 0xFFFFFFFF 122 #define TIMG_T0_ALARM_HI_S 0 123 124 #define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018) 125 /* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 126 /*description: Lower 32 bits of the value that will load into timer 0 time-base counter*/ 127 #define TIMG_T0_LOAD_LO 0xFFFFFFFF 128 #define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S)) 129 #define TIMG_T0_LOAD_LO_V 0xFFFFFFFF 130 #define TIMG_T0_LOAD_LO_S 0 131 132 #define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c) 133 /* TIMG_T0_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 134 /*description: higher 32 bits of the value that will load into timer 0 time-base counter*/ 135 #define TIMG_T0_LOAD_HI 0xFFFFFFFF 136 #define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S)) 137 #define TIMG_T0_LOAD_HI_V 0xFFFFFFFF 138 #define TIMG_T0_LOAD_HI_S 0 139 140 #define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020) 141 /* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ 142 /*description: Write any value will trigger timer 0 time-base counter reload*/ 143 #define TIMG_T0_LOAD 0xFFFFFFFF 144 #define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S)) 145 #define TIMG_T0_LOAD_V 0xFFFFFFFF 146 #define TIMG_T0_LOAD_S 0 147 148 #define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024) 149 /* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ 150 /*description: When set timer 1 time-base counter is enabled*/ 151 #define TIMG_T1_EN (BIT(31)) 152 #define TIMG_T1_EN_M (BIT(31)) 153 #define TIMG_T1_EN_V 0x1 154 #define TIMG_T1_EN_S 31 155 /* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ 156 /*description: When set timer 1 time-base counter increment. When cleared timer 157 1 time-base counter decrement.*/ 158 #define TIMG_T1_INCREASE (BIT(30)) 159 #define TIMG_T1_INCREASE_M (BIT(30)) 160 #define TIMG_T1_INCREASE_V 0x1 161 #define TIMG_T1_INCREASE_S 30 162 /* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ 163 /*description: When set timer 1 auto-reload at alarming is enabled*/ 164 #define TIMG_T1_AUTORELOAD (BIT(29)) 165 #define TIMG_T1_AUTORELOAD_M (BIT(29)) 166 #define TIMG_T1_AUTORELOAD_V 0x1 167 #define TIMG_T1_AUTORELOAD_S 29 168 /* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ 169 /*description: Timer 1 clock (T1_clk) prescale value.*/ 170 #define TIMG_T1_DIVIDER 0x0000FFFF 171 #define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S)) 172 #define TIMG_T1_DIVIDER_V 0xFFFF 173 #define TIMG_T1_DIVIDER_S 13 174 /* TIMG_T1_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ 175 /*description: When set edge type interrupt will be generated during alarm*/ 176 #define TIMG_T1_EDGE_INT_EN (BIT(12)) 177 #define TIMG_T1_EDGE_INT_EN_M (BIT(12)) 178 #define TIMG_T1_EDGE_INT_EN_V 0x1 179 #define TIMG_T1_EDGE_INT_EN_S 12 180 /* TIMG_T1_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */ 181 /*description: When set level type interrupt will be generated during alarm*/ 182 #define TIMG_T1_LEVEL_INT_EN (BIT(11)) 183 #define TIMG_T1_LEVEL_INT_EN_M (BIT(11)) 184 #define TIMG_T1_LEVEL_INT_EN_V 0x1 185 #define TIMG_T1_LEVEL_INT_EN_S 11 186 /* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ 187 /*description: When set alarm is enabled*/ 188 #define TIMG_T1_ALARM_EN (BIT(10)) 189 #define TIMG_T1_ALARM_EN_M (BIT(10)) 190 #define TIMG_T1_ALARM_EN_V 0x1 191 #define TIMG_T1_ALARM_EN_S 10 192 193 #define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028) 194 /* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 195 /*description: Register to store timer 1 time-base counter current value lower 32 bits.*/ 196 #define TIMG_T1_LO 0xFFFFFFFF 197 #define TIMG_T1_LO_M ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S)) 198 #define TIMG_T1_LO_V 0xFFFFFFFF 199 #define TIMG_T1_LO_S 0 200 201 #define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c) 202 /* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 203 /*description: Register to store timer 1 time-base counter current value higher 32 bits.*/ 204 #define TIMG_T1_HI 0xFFFFFFFF 205 #define TIMG_T1_HI_M ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S)) 206 #define TIMG_T1_HI_V 0xFFFFFFFF 207 #define TIMG_T1_HI_S 0 208 209 #define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030) 210 /* TIMG_T1_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */ 211 /*description: Write any value will trigger a timer 1 time-base counter value 212 update (timer 1 current value will be stored in registers above)*/ 213 #define TIMG_T1_UPDATE 0xFFFFFFFF 214 #define TIMG_T1_UPDATE_M ((TIMG_T1_UPDATE_V)<<(TIMG_T1_UPDATE_S)) 215 #define TIMG_T1_UPDATE_V 0xFFFFFFFF 216 #define TIMG_T1_UPDATE_S 0 217 218 #define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034) 219 /* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 220 /*description: Timer 1 time-base counter value lower 32 bits that will trigger the alarm*/ 221 #define TIMG_T1_ALARM_LO 0xFFFFFFFF 222 #define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S)) 223 #define TIMG_T1_ALARM_LO_V 0xFFFFFFFF 224 #define TIMG_T1_ALARM_LO_S 0 225 226 #define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038) 227 /* TIMG_T1_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 228 /*description: Timer 1 time-base counter value higher 32 bits that will trigger the alarm*/ 229 #define TIMG_T1_ALARM_HI 0xFFFFFFFF 230 #define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S)) 231 #define TIMG_T1_ALARM_HI_V 0xFFFFFFFF 232 #define TIMG_T1_ALARM_HI_S 0 233 234 #define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c) 235 /* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 236 /*description: Lower 32 bits of the value that will load into timer 1 time-base counter*/ 237 #define TIMG_T1_LOAD_LO 0xFFFFFFFF 238 #define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S)) 239 #define TIMG_T1_LOAD_LO_V 0xFFFFFFFF 240 #define TIMG_T1_LOAD_LO_S 0 241 242 #define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040) 243 /* TIMG_T1_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 244 /*description: higher 32 bits of the value that will load into timer 1 time-base counter*/ 245 #define TIMG_T1_LOAD_HI 0xFFFFFFFF 246 #define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S)) 247 #define TIMG_T1_LOAD_HI_V 0xFFFFFFFF 248 #define TIMG_T1_LOAD_HI_S 0 249 250 #define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044) 251 /* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ 252 /*description: Write any value will trigger timer 1 time-base counter reload*/ 253 #define TIMG_T1_LOAD 0xFFFFFFFF 254 #define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S)) 255 #define TIMG_T1_LOAD_V 0xFFFFFFFF 256 #define TIMG_T1_LOAD_S 0 257 258 #define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048) 259 /* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ 260 /*description: When set SWDT is enabled*/ 261 #define TIMG_WDT_EN (BIT(31)) 262 #define TIMG_WDT_EN_M (BIT(31)) 263 #define TIMG_WDT_EN_V 0x1 264 #define TIMG_WDT_EN_S 31 265 /* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 1'd0 ; */ 266 /*description: Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ 267 #define TIMG_WDT_STG0 0x00000003 268 #define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S)) 269 #define TIMG_WDT_STG0_V 0x3 270 #define TIMG_WDT_STG0_S 29 271 /* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; */ 272 /*description: Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ 273 #define TIMG_WDT_STG1 0x00000003 274 #define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S)) 275 #define TIMG_WDT_STG1_V 0x3 276 #define TIMG_WDT_STG1_S 27 277 /* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 1'd0 ; */ 278 /*description: Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ 279 #define TIMG_WDT_STG2 0x00000003 280 #define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S)) 281 #define TIMG_WDT_STG2_V 0x3 282 #define TIMG_WDT_STG2_S 25 283 /* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 1'd0 ; */ 284 /*description: Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system*/ 285 #define TIMG_WDT_STG3 0x00000003 286 #define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S)) 287 #define TIMG_WDT_STG3_V 0x3 288 #define TIMG_WDT_STG3_S 23 289 /* TIMG_WDT_EDGE_INT_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */ 290 /*description: When set edge type interrupt generation is enabled*/ 291 #define TIMG_WDT_EDGE_INT_EN (BIT(22)) 292 #define TIMG_WDT_EDGE_INT_EN_M (BIT(22)) 293 #define TIMG_WDT_EDGE_INT_EN_V 0x1 294 #define TIMG_WDT_EDGE_INT_EN_S 22 295 /* TIMG_WDT_LEVEL_INT_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */ 296 /*description: When set level type interrupt generation is enabled*/ 297 #define TIMG_WDT_LEVEL_INT_EN (BIT(21)) 298 #define TIMG_WDT_LEVEL_INT_EN_M (BIT(21)) 299 #define TIMG_WDT_LEVEL_INT_EN_V 0x1 300 #define TIMG_WDT_LEVEL_INT_EN_S 21 301 /* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */ 302 /*description: length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 303 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ 304 #define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 305 #define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S)) 306 #define TIMG_WDT_CPU_RESET_LENGTH_V 0x7 307 #define TIMG_WDT_CPU_RESET_LENGTH_S 18 308 /* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */ 309 /*description: length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 310 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us*/ 311 #define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 312 #define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S)) 313 #define TIMG_WDT_SYS_RESET_LENGTH_V 0x7 314 #define TIMG_WDT_SYS_RESET_LENGTH_S 15 315 /* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ 316 /*description: When set flash boot protection is enabled*/ 317 #define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) 318 #define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) 319 #define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1 320 #define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 321 322 #define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c) 323 /* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */ 324 /*description: SWDT clock prescale value. Period = 12.5ns * value stored in this register*/ 325 #define TIMG_WDT_CLK_PRESCALE 0x0000FFFF 326 #define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S)) 327 #define TIMG_WDT_CLK_PRESCALE_V 0xFFFF 328 #define TIMG_WDT_CLK_PRESCALE_S 16 329 330 #define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050) 331 /* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */ 332 /*description: Stage 0 timeout value in SWDT clock cycles*/ 333 #define TIMG_WDT_STG0_HOLD 0xFFFFFFFF 334 #define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S)) 335 #define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF 336 #define TIMG_WDT_STG0_HOLD_S 0 337 338 #define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054) 339 /* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */ 340 /*description: Stage 1 timeout value in SWDT clock cycles*/ 341 #define TIMG_WDT_STG1_HOLD 0xFFFFFFFF 342 #define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S)) 343 #define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF 344 #define TIMG_WDT_STG1_HOLD_S 0 345 346 #define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058) 347 /* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ 348 /*description: Stage 2 timeout value in SWDT clock cycles*/ 349 #define TIMG_WDT_STG2_HOLD 0xFFFFFFFF 350 #define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S)) 351 #define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF 352 #define TIMG_WDT_STG2_HOLD_S 0 353 354 #define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c) 355 /* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ 356 /*description: Stage 3 timeout value in SWDT clock cycles*/ 357 #define TIMG_WDT_STG3_HOLD 0xFFFFFFFF 358 #define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S)) 359 #define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF 360 #define TIMG_WDT_STG3_HOLD_S 0 361 362 #define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060) 363 /* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */ 364 /*description: Write any value will feed SWDT*/ 365 #define TIMG_WDT_FEED 0xFFFFFFFF 366 #define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S)) 367 #define TIMG_WDT_FEED_V 0xFFFFFFFF 368 #define TIMG_WDT_FEED_S 0 369 370 #define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064) 371 /* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ 372 /*description: If change its value from default then write protection is on.*/ 373 #define TIMG_WDT_WKEY 0xFFFFFFFF 374 #define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S)) 375 #define TIMG_WDT_WKEY_V 0xFFFFFFFF 376 #define TIMG_WDT_WKEY_S 0 377 378 #define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) 379 /* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */ 380 /*description: */ 381 #define TIMG_RTC_CALI_START (BIT(31)) 382 #define TIMG_RTC_CALI_START_M (BIT(31)) 383 #define TIMG_RTC_CALI_START_V 0x1 384 #define TIMG_RTC_CALI_START_S 31 385 /* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */ 386 /*description: */ 387 #define TIMG_RTC_CALI_MAX 0x00007FFF 388 #define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S)) 389 #define TIMG_RTC_CALI_MAX_V 0x7FFF 390 #define TIMG_RTC_CALI_MAX_S 16 391 /* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */ 392 /*description: */ 393 #define TIMG_RTC_CALI_RDY (BIT(15)) 394 #define TIMG_RTC_CALI_RDY_M (BIT(15)) 395 #define TIMG_RTC_CALI_RDY_V 0x1 396 #define TIMG_RTC_CALI_RDY_S 15 397 /* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ 398 /*description: */ 399 #define TIMG_RTC_CALI_CLK_SEL 0x00000003 400 #define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S)) 401 #define TIMG_RTC_CALI_CLK_SEL_V 0x3 402 #define TIMG_RTC_CALI_CLK_SEL_S 13 403 /* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */ 404 /*description: */ 405 #define TIMG_RTC_CALI_START_CYCLING (BIT(12)) 406 #define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) 407 #define TIMG_RTC_CALI_START_CYCLING_V 0x1 408 #define TIMG_RTC_CALI_START_CYCLING_S 12 409 410 #define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) 411 /* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */ 412 /*description: */ 413 #define TIMG_RTC_CALI_VALUE 0x01FFFFFF 414 #define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S)) 415 #define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF 416 #define TIMG_RTC_CALI_VALUE_S 7 417 418 #define TIMG_LACTCONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0070) 419 /* TIMG_LACT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ 420 /*description: */ 421 #define TIMG_LACT_EN (BIT(31)) 422 #define TIMG_LACT_EN_M (BIT(31)) 423 #define TIMG_LACT_EN_V 0x1 424 #define TIMG_LACT_EN_S 31 425 /* TIMG_LACT_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ 426 /*description: */ 427 #define TIMG_LACT_INCREASE (BIT(30)) 428 #define TIMG_LACT_INCREASE_M (BIT(30)) 429 #define TIMG_LACT_INCREASE_V 0x1 430 #define TIMG_LACT_INCREASE_S 30 431 /* TIMG_LACT_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ 432 /*description: */ 433 #define TIMG_LACT_AUTORELOAD (BIT(29)) 434 #define TIMG_LACT_AUTORELOAD_M (BIT(29)) 435 #define TIMG_LACT_AUTORELOAD_V 0x1 436 #define TIMG_LACT_AUTORELOAD_S 29 437 /* TIMG_LACT_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ 438 /*description: */ 439 #define TIMG_LACT_DIVIDER 0x0000FFFF 440 #define TIMG_LACT_DIVIDER_M ((TIMG_LACT_DIVIDER_V)<<(TIMG_LACT_DIVIDER_S)) 441 #define TIMG_LACT_DIVIDER_V 0xFFFF 442 #define TIMG_LACT_DIVIDER_S 13 443 /* TIMG_LACT_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */ 444 /*description: */ 445 #define TIMG_LACT_EDGE_INT_EN (BIT(12)) 446 #define TIMG_LACT_EDGE_INT_EN_M (BIT(12)) 447 #define TIMG_LACT_EDGE_INT_EN_V 0x1 448 #define TIMG_LACT_EDGE_INT_EN_S 12 449 /* TIMG_LACT_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */ 450 /*description: */ 451 #define TIMG_LACT_LEVEL_INT_EN (BIT(11)) 452 #define TIMG_LACT_LEVEL_INT_EN_M (BIT(11)) 453 #define TIMG_LACT_LEVEL_INT_EN_V 0x1 454 #define TIMG_LACT_LEVEL_INT_EN_S 11 455 /* TIMG_LACT_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ 456 /*description: */ 457 #define TIMG_LACT_ALARM_EN (BIT(10)) 458 #define TIMG_LACT_ALARM_EN_M (BIT(10)) 459 #define TIMG_LACT_ALARM_EN_V 0x1 460 #define TIMG_LACT_ALARM_EN_S 10 461 /* TIMG_LACT_LAC_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ 462 /*description: */ 463 #define TIMG_LACT_LAC_EN (BIT(9)) 464 #define TIMG_LACT_LAC_EN_M (BIT(9)) 465 #define TIMG_LACT_LAC_EN_V 0x1 466 #define TIMG_LACT_LAC_EN_S 9 467 /* TIMG_LACT_CPST_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ 468 /*description: */ 469 #define TIMG_LACT_CPST_EN (BIT(8)) 470 #define TIMG_LACT_CPST_EN_M (BIT(8)) 471 #define TIMG_LACT_CPST_EN_V 0x1 472 #define TIMG_LACT_CPST_EN_S 8 473 /* TIMG_LACT_RTC_ONLY : R/W ;bitpos:[7] ;default: 1'h0 ; */ 474 /*description: */ 475 #define TIMG_LACT_RTC_ONLY (BIT(7)) 476 #define TIMG_LACT_RTC_ONLY_M (BIT(7)) 477 #define TIMG_LACT_RTC_ONLY_V 0x1 478 #define TIMG_LACT_RTC_ONLY_S 7 479 480 #define TIMG_LACTRTC_REG(i) (REG_TIMG_BASE(i) + 0x0074) 481 /* TIMG_LACT_RTC_STEP_LEN : R/W ;bitpos:[31:6] ;default: 26'h0 ; */ 482 /*description: */ 483 #define TIMG_LACT_RTC_STEP_LEN 0x03FFFFFF 484 #define TIMG_LACT_RTC_STEP_LEN_M ((TIMG_LACT_RTC_STEP_LEN_V)<<(TIMG_LACT_RTC_STEP_LEN_S)) 485 #define TIMG_LACT_RTC_STEP_LEN_V 0x3FFFFFF 486 #define TIMG_LACT_RTC_STEP_LEN_S 6 487 488 #define TIMG_LACTLO_REG(i) (REG_TIMG_BASE(i) + 0x0078) 489 /* TIMG_LACT_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 490 /*description: */ 491 #define TIMG_LACT_LO 0xFFFFFFFF 492 #define TIMG_LACT_LO_M ((TIMG_LACT_LO_V)<<(TIMG_LACT_LO_S)) 493 #define TIMG_LACT_LO_V 0xFFFFFFFF 494 #define TIMG_LACT_LO_S 0 495 496 #define TIMG_LACTHI_REG(i) (REG_TIMG_BASE(i) + 0x007c) 497 /* TIMG_LACT_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */ 498 /*description: */ 499 #define TIMG_LACT_HI 0xFFFFFFFF 500 #define TIMG_LACT_HI_M ((TIMG_LACT_HI_V)<<(TIMG_LACT_HI_S)) 501 #define TIMG_LACT_HI_V 0xFFFFFFFF 502 #define TIMG_LACT_HI_S 0 503 504 #define TIMG_LACTUPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0080) 505 /* TIMG_LACT_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */ 506 /*description: */ 507 #define TIMG_LACT_UPDATE 0xFFFFFFFF 508 #define TIMG_LACT_UPDATE_M ((TIMG_LACT_UPDATE_V)<<(TIMG_LACT_UPDATE_S)) 509 #define TIMG_LACT_UPDATE_V 0xFFFFFFFF 510 #define TIMG_LACT_UPDATE_S 0 511 512 #define TIMG_LACTALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0084) 513 /* TIMG_LACT_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 514 /*description: */ 515 #define TIMG_LACT_ALARM_LO 0xFFFFFFFF 516 #define TIMG_LACT_ALARM_LO_M ((TIMG_LACT_ALARM_LO_V)<<(TIMG_LACT_ALARM_LO_S)) 517 #define TIMG_LACT_ALARM_LO_V 0xFFFFFFFF 518 #define TIMG_LACT_ALARM_LO_S 0 519 520 #define TIMG_LACTALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0088) 521 /* TIMG_LACT_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 522 /*description: */ 523 #define TIMG_LACT_ALARM_HI 0xFFFFFFFF 524 #define TIMG_LACT_ALARM_HI_M ((TIMG_LACT_ALARM_HI_V)<<(TIMG_LACT_ALARM_HI_S)) 525 #define TIMG_LACT_ALARM_HI_V 0xFFFFFFFF 526 #define TIMG_LACT_ALARM_HI_S 0 527 528 #define TIMG_LACTLOADLO_REG(i) (REG_TIMG_BASE(i) + 0x008c) 529 /* TIMG_LACT_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 530 /*description: */ 531 #define TIMG_LACT_LOAD_LO 0xFFFFFFFF 532 #define TIMG_LACT_LOAD_LO_M ((TIMG_LACT_LOAD_LO_V)<<(TIMG_LACT_LOAD_LO_S)) 533 #define TIMG_LACT_LOAD_LO_V 0xFFFFFFFF 534 #define TIMG_LACT_LOAD_LO_S 0 535 536 #define TIMG_LACTLOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0090) 537 /* TIMG_LACT_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ 538 /*description: */ 539 #define TIMG_LACT_LOAD_HI 0xFFFFFFFF 540 #define TIMG_LACT_LOAD_HI_M ((TIMG_LACT_LOAD_HI_V)<<(TIMG_LACT_LOAD_HI_S)) 541 #define TIMG_LACT_LOAD_HI_V 0xFFFFFFFF 542 #define TIMG_LACT_LOAD_HI_S 0 543 544 #define TIMG_LACTLOAD_REG(i) (REG_TIMG_BASE(i) + 0x0094) 545 /* TIMG_LACT_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ 546 /*description: */ 547 #define TIMG_LACT_LOAD 0xFFFFFFFF 548 #define TIMG_LACT_LOAD_M ((TIMG_LACT_LOAD_V)<<(TIMG_LACT_LOAD_S)) 549 #define TIMG_LACT_LOAD_V 0xFFFFFFFF 550 #define TIMG_LACT_LOAD_S 0 551 552 #define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0098) 553 /* TIMG_LACT_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */ 554 /*description: */ 555 #define TIMG_LACT_INT_ENA (BIT(3)) 556 #define TIMG_LACT_INT_ENA_M (BIT(3)) 557 #define TIMG_LACT_INT_ENA_V 0x1 558 #define TIMG_LACT_INT_ENA_S 3 559 /* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ 560 /*description: Interrupt when an interrupt stage timeout*/ 561 #define TIMG_WDT_INT_ENA (BIT(2)) 562 #define TIMG_WDT_INT_ENA_M (BIT(2)) 563 #define TIMG_WDT_INT_ENA_V 0x1 564 #define TIMG_WDT_INT_ENA_S 2 565 /* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ 566 /*description: interrupt when timer1 alarm*/ 567 #define TIMG_T1_INT_ENA (BIT(1)) 568 #define TIMG_T1_INT_ENA_M (BIT(1)) 569 #define TIMG_T1_INT_ENA_V 0x1 570 #define TIMG_T1_INT_ENA_S 1 571 /* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ 572 /*description: interrupt when timer0 alarm*/ 573 #define TIMG_T0_INT_ENA (BIT(0)) 574 #define TIMG_T0_INT_ENA_M (BIT(0)) 575 #define TIMG_T0_INT_ENA_V 0x1 576 #define TIMG_T0_INT_ENA_S 0 577 578 #define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x009c) 579 /* TIMG_LACT_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */ 580 /*description: */ 581 #define TIMG_LACT_INT_RAW (BIT(3)) 582 #define TIMG_LACT_INT_RAW_M (BIT(3)) 583 #define TIMG_LACT_INT_RAW_V 0x1 584 #define TIMG_LACT_INT_RAW_S 3 585 /* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ 586 /*description: Interrupt when an interrupt stage timeout*/ 587 #define TIMG_WDT_INT_RAW (BIT(2)) 588 #define TIMG_WDT_INT_RAW_M (BIT(2)) 589 #define TIMG_WDT_INT_RAW_V 0x1 590 #define TIMG_WDT_INT_RAW_S 2 591 /* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ 592 /*description: interrupt when timer1 alarm*/ 593 #define TIMG_T1_INT_RAW (BIT(1)) 594 #define TIMG_T1_INT_RAW_M (BIT(1)) 595 #define TIMG_T1_INT_RAW_V 0x1 596 #define TIMG_T1_INT_RAW_S 1 597 /* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ 598 /*description: interrupt when timer0 alarm*/ 599 #define TIMG_T0_INT_RAW (BIT(0)) 600 #define TIMG_T0_INT_RAW_M (BIT(0)) 601 #define TIMG_T0_INT_RAW_V 0x1 602 #define TIMG_T0_INT_RAW_S 0 603 604 #define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a0) 605 /* TIMG_LACT_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */ 606 /*description: */ 607 #define TIMG_LACT_INT_ST (BIT(3)) 608 #define TIMG_LACT_INT_ST_M (BIT(3)) 609 #define TIMG_LACT_INT_ST_V 0x1 610 #define TIMG_LACT_INT_ST_S 3 611 /* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ 612 /*description: Interrupt when an interrupt stage timeout*/ 613 #define TIMG_WDT_INT_ST (BIT(2)) 614 #define TIMG_WDT_INT_ST_M (BIT(2)) 615 #define TIMG_WDT_INT_ST_V 0x1 616 #define TIMG_WDT_INT_ST_S 2 617 /* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ 618 /*description: interrupt when timer1 alarm*/ 619 #define TIMG_T1_INT_ST (BIT(1)) 620 #define TIMG_T1_INT_ST_M (BIT(1)) 621 #define TIMG_T1_INT_ST_V 0x1 622 #define TIMG_T1_INT_ST_S 1 623 /* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ 624 /*description: interrupt when timer0 alarm*/ 625 #define TIMG_T0_INT_ST (BIT(0)) 626 #define TIMG_T0_INT_ST_M (BIT(0)) 627 #define TIMG_T0_INT_ST_V 0x1 628 #define TIMG_T0_INT_ST_S 0 629 630 #define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x00a4) 631 /* TIMG_LACT_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */ 632 /*description: */ 633 #define TIMG_LACT_INT_CLR (BIT(3)) 634 #define TIMG_LACT_INT_CLR_M (BIT(3)) 635 #define TIMG_LACT_INT_CLR_V 0x1 636 #define TIMG_LACT_INT_CLR_S 3 637 /* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ 638 /*description: Interrupt when an interrupt stage timeout*/ 639 #define TIMG_WDT_INT_CLR (BIT(2)) 640 #define TIMG_WDT_INT_CLR_M (BIT(2)) 641 #define TIMG_WDT_INT_CLR_V 0x1 642 #define TIMG_WDT_INT_CLR_S 2 643 /* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ 644 /*description: interrupt when timer1 alarm*/ 645 #define TIMG_T1_INT_CLR (BIT(1)) 646 #define TIMG_T1_INT_CLR_M (BIT(1)) 647 #define TIMG_T1_INT_CLR_V 0x1 648 #define TIMG_T1_INT_CLR_S 1 649 /* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ 650 /*description: interrupt when timer0 alarm*/ 651 #define TIMG_T0_INT_CLR (BIT(0)) 652 #define TIMG_T0_INT_CLR_M (BIT(0)) 653 #define TIMG_T0_INT_CLR_V 0x1 654 #define TIMG_T0_INT_CLR_S 0 655 656 #define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8) 657 /* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604290 ; */ 658 /*description: Version of this regfile*/ 659 #define TIMG_NTIMERS_DATE 0x0FFFFFFF 660 #define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S)) 661 #define TIMG_NTIMERS_DATE_V 0xFFFFFFF 662 #define TIMG_NTIMERS_DATE_S 0 663 664 #define TIMGCLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc) 665 /* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ 666 /*description: Force clock enable for this regfile*/ 667 #define TIMG_CLK_EN (BIT(31)) 668 #define TIMG_CLK_EN_M (BIT(31)) 669 #define TIMG_CLK_EN_V 0x1 670 #define TIMG_CLK_EN_S 31 671 672 673 674 675 #endif /*__TIMG_REG_H__ */ 676