1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 #ifndef __UART_REG_H__ 15 #define __UART_REG_H__ 16 17 18 #include "soc.h" 19 20 #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) 21 #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) 22 #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) 23 #define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) 24 25 /* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ 26 /*description: This register stores one byte data read by rx fifo.*/ 27 #define UART_RXFIFO_RD_BYTE 0x000000FF 28 #define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S)) 29 #define UART_RXFIFO_RD_BYTE_V 0xFF 30 #define UART_RXFIFO_RD_BYTE_S 0 31 32 #define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) 33 /* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ 34 /*description: This interrupt raw bit turns to high level when receiver detects 35 the configured at_cmd chars.*/ 36 #define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) 37 #define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) 38 #define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 39 #define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 40 /* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ 41 /*description: This interrupt raw bit turns to high level when rs485 detects 42 the clash between transmitter and receiver.*/ 43 #define UART_RS485_CLASH_INT_RAW (BIT(17)) 44 #define UART_RS485_CLASH_INT_RAW_M (BIT(17)) 45 #define UART_RS485_CLASH_INT_RAW_V 0x1 46 #define UART_RS485_CLASH_INT_RAW_S 17 47 /* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ 48 /*description: This interrupt raw bit turns to high level when rs485 detects 49 the data frame error.*/ 50 #define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) 51 #define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) 52 #define UART_RS485_FRM_ERR_INT_RAW_V 0x1 53 #define UART_RS485_FRM_ERR_INT_RAW_S 16 54 /* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ 55 /*description: This interrupt raw bit turns to high level when rs485 detects the parity error.*/ 56 #define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) 57 #define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) 58 #define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 59 #define UART_RS485_PARITY_ERR_INT_RAW_S 15 60 /* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ 61 /*description: This interrupt raw bit turns to high level when transmitter has 62 send all the data in fifo.*/ 63 #define UART_TX_DONE_INT_RAW (BIT(14)) 64 #define UART_TX_DONE_INT_RAW_M (BIT(14)) 65 #define UART_TX_DONE_INT_RAW_V 0x1 66 #define UART_TX_DONE_INT_RAW_S 14 67 /* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ 68 /*description: This interrupt raw bit turns to high level when transmitter has 69 kept the shortest duration after the last data has been send.*/ 70 #define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) 71 #define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) 72 #define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 73 #define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 74 /* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ 75 /*description: This interrupt raw bit turns to high level when transmitter completes 76 sendding 0 after all the datas in transmitter's fifo are send.*/ 77 #define UART_TX_BRK_DONE_INT_RAW (BIT(12)) 78 #define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) 79 #define UART_TX_BRK_DONE_INT_RAW_V 0x1 80 #define UART_TX_BRK_DONE_INT_RAW_S 12 81 /* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ 82 /*description: This interrupt raw bit turns to high level when receiver detects the start bit.*/ 83 #define UART_GLITCH_DET_INT_RAW (BIT(11)) 84 #define UART_GLITCH_DET_INT_RAW_M (BIT(11)) 85 #define UART_GLITCH_DET_INT_RAW_V 0x1 86 #define UART_GLITCH_DET_INT_RAW_S 11 87 /* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ 88 /*description: This interrupt raw bit turns to high level when receiver receives 89 xon char with uart_sw_flow_con_en is set to 1.*/ 90 #define UART_SW_XOFF_INT_RAW (BIT(10)) 91 #define UART_SW_XOFF_INT_RAW_M (BIT(10)) 92 #define UART_SW_XOFF_INT_RAW_V 0x1 93 #define UART_SW_XOFF_INT_RAW_S 10 94 /* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ 95 /*description: This interrupt raw bit turns to high level when receiver receives 96 xoff char with uart_sw_flow_con_en is set to 1.*/ 97 #define UART_SW_XON_INT_RAW (BIT(9)) 98 #define UART_SW_XON_INT_RAW_M (BIT(9)) 99 #define UART_SW_XON_INT_RAW_V 0x1 100 #define UART_SW_XON_INT_RAW_S 9 101 /* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ 102 /*description: This interrupt raw bit turns to high level when receiver takes 103 more time than rx_tout_thrhd to receive a byte.*/ 104 #define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) 105 #define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) 106 #define UART_RXFIFO_TOUT_INT_RAW_V 0x1 107 #define UART_RXFIFO_TOUT_INT_RAW_S 8 108 /* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ 109 /*description: This interrupt raw bit turns to high level when receiver detects 110 the 0 after the stop bit.*/ 111 #define UART_BRK_DET_INT_RAW (BIT(7)) 112 #define UART_BRK_DET_INT_RAW_M (BIT(7)) 113 #define UART_BRK_DET_INT_RAW_V 0x1 114 #define UART_BRK_DET_INT_RAW_S 7 115 /* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ 116 /*description: This interrupt raw bit turns to high level when receiver detects 117 the edge change of ctsn signal.*/ 118 #define UART_CTS_CHG_INT_RAW (BIT(6)) 119 #define UART_CTS_CHG_INT_RAW_M (BIT(6)) 120 #define UART_CTS_CHG_INT_RAW_V 0x1 121 #define UART_CTS_CHG_INT_RAW_S 6 122 /* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ 123 /*description: This interrupt raw bit turns to high level when receiver detects 124 the edge change of dsrn signal.*/ 125 #define UART_DSR_CHG_INT_RAW (BIT(5)) 126 #define UART_DSR_CHG_INT_RAW_M (BIT(5)) 127 #define UART_DSR_CHG_INT_RAW_V 0x1 128 #define UART_DSR_CHG_INT_RAW_S 5 129 /* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ 130 /*description: This interrupt raw bit turns to high level when receiver receives 131 more data than the fifo can store.*/ 132 #define UART_RXFIFO_OVF_INT_RAW (BIT(4)) 133 #define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) 134 #define UART_RXFIFO_OVF_INT_RAW_V 0x1 135 #define UART_RXFIFO_OVF_INT_RAW_S 4 136 /* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ 137 /*description: This interrupt raw bit turns to high level when receiver detects 138 data's frame error .*/ 139 #define UART_FRM_ERR_INT_RAW (BIT(3)) 140 #define UART_FRM_ERR_INT_RAW_M (BIT(3)) 141 #define UART_FRM_ERR_INT_RAW_V 0x1 142 #define UART_FRM_ERR_INT_RAW_S 3 143 /* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ 144 /*description: This interrupt raw bit turns to high level when receiver detects 145 the parity error of data.*/ 146 #define UART_PARITY_ERR_INT_RAW (BIT(2)) 147 #define UART_PARITY_ERR_INT_RAW_M (BIT(2)) 148 #define UART_PARITY_ERR_INT_RAW_V 0x1 149 #define UART_PARITY_ERR_INT_RAW_S 2 150 /* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ 151 /*description: This interrupt raw bit turns to high level when the amount of 152 data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/ 153 #define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) 154 #define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) 155 #define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 156 #define UART_TXFIFO_EMPTY_INT_RAW_S 1 157 /* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ 158 /*description: This interrupt raw bit turns to high level when receiver receives 159 more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/ 160 #define UART_RXFIFO_FULL_INT_RAW (BIT(0)) 161 #define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) 162 #define UART_RXFIFO_FULL_INT_RAW_V 0x1 163 #define UART_RXFIFO_FULL_INT_RAW_S 0 164 165 #define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) 166 /* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ 167 /*description: This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena 168 is set to 1.*/ 169 #define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) 170 #define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) 171 #define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 172 #define UART_AT_CMD_CHAR_DET_INT_ST_S 18 173 /* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ 174 /*description: This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena 175 is set to 1.*/ 176 #define UART_RS485_CLASH_INT_ST (BIT(17)) 177 #define UART_RS485_CLASH_INT_ST_M (BIT(17)) 178 #define UART_RS485_CLASH_INT_ST_V 0x1 179 #define UART_RS485_CLASH_INT_ST_S 17 180 /* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ 181 /*description: This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena 182 is set to 1.*/ 183 #define UART_RS485_FRM_ERR_INT_ST (BIT(16)) 184 #define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) 185 #define UART_RS485_FRM_ERR_INT_ST_V 0x1 186 #define UART_RS485_FRM_ERR_INT_ST_S 16 187 /* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ 188 /*description: This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena 189 is set to 1.*/ 190 #define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) 191 #define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) 192 #define UART_RS485_PARITY_ERR_INT_ST_V 0x1 193 #define UART_RS485_PARITY_ERR_INT_ST_S 15 194 /* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ 195 /*description: This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/ 196 #define UART_TX_DONE_INT_ST (BIT(14)) 197 #define UART_TX_DONE_INT_ST_M (BIT(14)) 198 #define UART_TX_DONE_INT_ST_V 0x1 199 #define UART_TX_DONE_INT_ST_S 14 200 /* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ 201 /*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena 202 is set to 1.*/ 203 #define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) 204 #define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) 205 #define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 206 #define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 207 /* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ 208 /*description: This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena 209 is set to 1.*/ 210 #define UART_TX_BRK_DONE_INT_ST (BIT(12)) 211 #define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) 212 #define UART_TX_BRK_DONE_INT_ST_V 0x1 213 #define UART_TX_BRK_DONE_INT_ST_S 12 214 /* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ 215 /*description: This is the status bit for glitch_det_int_raw when glitch_det_int_ena 216 is set to 1.*/ 217 #define UART_GLITCH_DET_INT_ST (BIT(11)) 218 #define UART_GLITCH_DET_INT_ST_M (BIT(11)) 219 #define UART_GLITCH_DET_INT_ST_V 0x1 220 #define UART_GLITCH_DET_INT_ST_S 11 221 /* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ 222 /*description: This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/ 223 #define UART_SW_XOFF_INT_ST (BIT(10)) 224 #define UART_SW_XOFF_INT_ST_M (BIT(10)) 225 #define UART_SW_XOFF_INT_ST_V 0x1 226 #define UART_SW_XOFF_INT_ST_S 10 227 /* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ 228 /*description: This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/ 229 #define UART_SW_XON_INT_ST (BIT(9)) 230 #define UART_SW_XON_INT_ST_M (BIT(9)) 231 #define UART_SW_XON_INT_ST_V 0x1 232 #define UART_SW_XON_INT_ST_S 9 233 /* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ 234 /*description: This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena 235 is set to 1.*/ 236 #define UART_RXFIFO_TOUT_INT_ST (BIT(8)) 237 #define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) 238 #define UART_RXFIFO_TOUT_INT_ST_V 0x1 239 #define UART_RXFIFO_TOUT_INT_ST_S 8 240 /* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ 241 /*description: This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/ 242 #define UART_BRK_DET_INT_ST (BIT(7)) 243 #define UART_BRK_DET_INT_ST_M (BIT(7)) 244 #define UART_BRK_DET_INT_ST_V 0x1 245 #define UART_BRK_DET_INT_ST_S 7 246 /* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ 247 /*description: This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/ 248 #define UART_CTS_CHG_INT_ST (BIT(6)) 249 #define UART_CTS_CHG_INT_ST_M (BIT(6)) 250 #define UART_CTS_CHG_INT_ST_V 0x1 251 #define UART_CTS_CHG_INT_ST_S 6 252 /* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ 253 /*description: This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/ 254 #define UART_DSR_CHG_INT_ST (BIT(5)) 255 #define UART_DSR_CHG_INT_ST_M (BIT(5)) 256 #define UART_DSR_CHG_INT_ST_V 0x1 257 #define UART_DSR_CHG_INT_ST_S 5 258 /* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ 259 /*description: This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena 260 is set to 1.*/ 261 #define UART_RXFIFO_OVF_INT_ST (BIT(4)) 262 #define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) 263 #define UART_RXFIFO_OVF_INT_ST_V 0x1 264 #define UART_RXFIFO_OVF_INT_ST_S 4 265 /* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ 266 /*description: This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/ 267 #define UART_FRM_ERR_INT_ST (BIT(3)) 268 #define UART_FRM_ERR_INT_ST_M (BIT(3)) 269 #define UART_FRM_ERR_INT_ST_V 0x1 270 #define UART_FRM_ERR_INT_ST_S 3 271 /* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ 272 /*description: This is the status bit for parity_err_int_raw when parity_err_int_ena 273 is set to 1.*/ 274 #define UART_PARITY_ERR_INT_ST (BIT(2)) 275 #define UART_PARITY_ERR_INT_ST_M (BIT(2)) 276 #define UART_PARITY_ERR_INT_ST_V 0x1 277 #define UART_PARITY_ERR_INT_ST_S 2 278 /* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ 279 /*description: This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena 280 is set to 1.*/ 281 #define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) 282 #define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) 283 #define UART_TXFIFO_EMPTY_INT_ST_V 0x1 284 #define UART_TXFIFO_EMPTY_INT_ST_S 1 285 /* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ 286 /*description: This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena 287 is set to 1.*/ 288 #define UART_RXFIFO_FULL_INT_ST (BIT(0)) 289 #define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) 290 #define UART_RXFIFO_FULL_INT_ST_V 0x1 291 #define UART_RXFIFO_FULL_INT_ST_S 0 292 293 #define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) 294 /* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ 295 /*description: This is the enable bit for at_cmd_char_det_int_st register.*/ 296 #define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) 297 #define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) 298 #define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 299 #define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 300 /* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ 301 /*description: This is the enable bit for rs485_clash_int_st register.*/ 302 #define UART_RS485_CLASH_INT_ENA (BIT(17)) 303 #define UART_RS485_CLASH_INT_ENA_M (BIT(17)) 304 #define UART_RS485_CLASH_INT_ENA_V 0x1 305 #define UART_RS485_CLASH_INT_ENA_S 17 306 /* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ 307 /*description: This is the enable bit for rs485_parity_err_int_st register.*/ 308 #define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) 309 #define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) 310 #define UART_RS485_FRM_ERR_INT_ENA_V 0x1 311 #define UART_RS485_FRM_ERR_INT_ENA_S 16 312 /* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ 313 /*description: This is the enable bit for rs485_parity_err_int_st register.*/ 314 #define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) 315 #define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) 316 #define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 317 #define UART_RS485_PARITY_ERR_INT_ENA_S 15 318 /* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ 319 /*description: This is the enable bit for tx_done_int_st register.*/ 320 #define UART_TX_DONE_INT_ENA (BIT(14)) 321 #define UART_TX_DONE_INT_ENA_M (BIT(14)) 322 #define UART_TX_DONE_INT_ENA_V 0x1 323 #define UART_TX_DONE_INT_ENA_S 14 324 /* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ 325 /*description: This is the enable bit for tx_brk_idle_done_int_st register.*/ 326 #define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) 327 #define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) 328 #define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 329 #define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 330 /* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ 331 /*description: This is the enable bit for tx_brk_done_int_st register.*/ 332 #define UART_TX_BRK_DONE_INT_ENA (BIT(12)) 333 #define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) 334 #define UART_TX_BRK_DONE_INT_ENA_V 0x1 335 #define UART_TX_BRK_DONE_INT_ENA_S 12 336 /* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ 337 /*description: This is the enable bit for glitch_det_int_st register.*/ 338 #define UART_GLITCH_DET_INT_ENA (BIT(11)) 339 #define UART_GLITCH_DET_INT_ENA_M (BIT(11)) 340 #define UART_GLITCH_DET_INT_ENA_V 0x1 341 #define UART_GLITCH_DET_INT_ENA_S 11 342 /* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ 343 /*description: This is the enable bit for sw_xoff_int_st register.*/ 344 #define UART_SW_XOFF_INT_ENA (BIT(10)) 345 #define UART_SW_XOFF_INT_ENA_M (BIT(10)) 346 #define UART_SW_XOFF_INT_ENA_V 0x1 347 #define UART_SW_XOFF_INT_ENA_S 10 348 /* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ 349 /*description: This is the enable bit for sw_xon_int_st register.*/ 350 #define UART_SW_XON_INT_ENA (BIT(9)) 351 #define UART_SW_XON_INT_ENA_M (BIT(9)) 352 #define UART_SW_XON_INT_ENA_V 0x1 353 #define UART_SW_XON_INT_ENA_S 9 354 /* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ 355 /*description: This is the enable bit for rxfifo_tout_int_st register.*/ 356 #define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) 357 #define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) 358 #define UART_RXFIFO_TOUT_INT_ENA_V 0x1 359 #define UART_RXFIFO_TOUT_INT_ENA_S 8 360 /* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ 361 /*description: This is the enable bit for brk_det_int_st register.*/ 362 #define UART_BRK_DET_INT_ENA (BIT(7)) 363 #define UART_BRK_DET_INT_ENA_M (BIT(7)) 364 #define UART_BRK_DET_INT_ENA_V 0x1 365 #define UART_BRK_DET_INT_ENA_S 7 366 /* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ 367 /*description: This is the enable bit for cts_chg_int_st register.*/ 368 #define UART_CTS_CHG_INT_ENA (BIT(6)) 369 #define UART_CTS_CHG_INT_ENA_M (BIT(6)) 370 #define UART_CTS_CHG_INT_ENA_V 0x1 371 #define UART_CTS_CHG_INT_ENA_S 6 372 /* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ 373 /*description: This is the enable bit for dsr_chg_int_st register.*/ 374 #define UART_DSR_CHG_INT_ENA (BIT(5)) 375 #define UART_DSR_CHG_INT_ENA_M (BIT(5)) 376 #define UART_DSR_CHG_INT_ENA_V 0x1 377 #define UART_DSR_CHG_INT_ENA_S 5 378 /* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ 379 /*description: This is the enable bit for rxfifo_ovf_int_st register.*/ 380 #define UART_RXFIFO_OVF_INT_ENA (BIT(4)) 381 #define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) 382 #define UART_RXFIFO_OVF_INT_ENA_V 0x1 383 #define UART_RXFIFO_OVF_INT_ENA_S 4 384 /* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ 385 /*description: This is the enable bit for frm_err_int_st register.*/ 386 #define UART_FRM_ERR_INT_ENA (BIT(3)) 387 #define UART_FRM_ERR_INT_ENA_M (BIT(3)) 388 #define UART_FRM_ERR_INT_ENA_V 0x1 389 #define UART_FRM_ERR_INT_ENA_S 3 390 /* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ 391 /*description: This is the enable bit for parity_err_int_st register.*/ 392 #define UART_PARITY_ERR_INT_ENA (BIT(2)) 393 #define UART_PARITY_ERR_INT_ENA_M (BIT(2)) 394 #define UART_PARITY_ERR_INT_ENA_V 0x1 395 #define UART_PARITY_ERR_INT_ENA_S 2 396 /* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ 397 /*description: This is the enable bit for rxfifo_full_int_st register.*/ 398 #define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) 399 #define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) 400 #define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 401 #define UART_TXFIFO_EMPTY_INT_ENA_S 1 402 /* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ 403 /*description: This is the enable bit for rxfifo_full_int_st register.*/ 404 #define UART_RXFIFO_FULL_INT_ENA (BIT(0)) 405 #define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) 406 #define UART_RXFIFO_FULL_INT_ENA_V 0x1 407 #define UART_RXFIFO_FULL_INT_ENA_S 0 408 409 #define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) 410 /* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ 411 /*description: Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/ 412 #define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) 413 #define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) 414 #define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 415 #define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 416 /* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ 417 /*description: Set this bit to clear the rs485_clash_int_raw interrupt.*/ 418 #define UART_RS485_CLASH_INT_CLR (BIT(17)) 419 #define UART_RS485_CLASH_INT_CLR_M (BIT(17)) 420 #define UART_RS485_CLASH_INT_CLR_V 0x1 421 #define UART_RS485_CLASH_INT_CLR_S 17 422 /* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ 423 /*description: Set this bit to clear the rs485_frm_err_int_raw interrupt.*/ 424 #define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) 425 #define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) 426 #define UART_RS485_FRM_ERR_INT_CLR_V 0x1 427 #define UART_RS485_FRM_ERR_INT_CLR_S 16 428 /* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ 429 /*description: Set this bit to clear the rs485_parity_err_int_raw interrupt.*/ 430 #define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) 431 #define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) 432 #define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 433 #define UART_RS485_PARITY_ERR_INT_CLR_S 15 434 /* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ 435 /*description: Set this bit to clear the tx_done_int_raw interrupt.*/ 436 #define UART_TX_DONE_INT_CLR (BIT(14)) 437 #define UART_TX_DONE_INT_CLR_M (BIT(14)) 438 #define UART_TX_DONE_INT_CLR_V 0x1 439 #define UART_TX_DONE_INT_CLR_S 14 440 /* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ 441 /*description: Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/ 442 #define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) 443 #define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) 444 #define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 445 #define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 446 /* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ 447 /*description: Set this bit to clear the tx_brk_done_int_raw interrupt..*/ 448 #define UART_TX_BRK_DONE_INT_CLR (BIT(12)) 449 #define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) 450 #define UART_TX_BRK_DONE_INT_CLR_V 0x1 451 #define UART_TX_BRK_DONE_INT_CLR_S 12 452 /* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ 453 /*description: Set this bit to clear the glitch_det_int_raw interrupt.*/ 454 #define UART_GLITCH_DET_INT_CLR (BIT(11)) 455 #define UART_GLITCH_DET_INT_CLR_M (BIT(11)) 456 #define UART_GLITCH_DET_INT_CLR_V 0x1 457 #define UART_GLITCH_DET_INT_CLR_S 11 458 /* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ 459 /*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ 460 #define UART_SW_XOFF_INT_CLR (BIT(10)) 461 #define UART_SW_XOFF_INT_CLR_M (BIT(10)) 462 #define UART_SW_XOFF_INT_CLR_V 0x1 463 #define UART_SW_XOFF_INT_CLR_S 10 464 /* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ 465 /*description: Set this bit to clear the sw_xon_int_raw interrupt.*/ 466 #define UART_SW_XON_INT_CLR (BIT(9)) 467 #define UART_SW_XON_INT_CLR_M (BIT(9)) 468 #define UART_SW_XON_INT_CLR_V 0x1 469 #define UART_SW_XON_INT_CLR_S 9 470 /* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ 471 /*description: Set this bit to clear the rxfifo_tout_int_raw interrupt.*/ 472 #define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) 473 #define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) 474 #define UART_RXFIFO_TOUT_INT_CLR_V 0x1 475 #define UART_RXFIFO_TOUT_INT_CLR_S 8 476 /* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ 477 /*description: Set this bit to clear the brk_det_int_raw interrupt.*/ 478 #define UART_BRK_DET_INT_CLR (BIT(7)) 479 #define UART_BRK_DET_INT_CLR_M (BIT(7)) 480 #define UART_BRK_DET_INT_CLR_V 0x1 481 #define UART_BRK_DET_INT_CLR_S 7 482 /* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ 483 /*description: Set this bit to clear the cts_chg_int_raw interrupt.*/ 484 #define UART_CTS_CHG_INT_CLR (BIT(6)) 485 #define UART_CTS_CHG_INT_CLR_M (BIT(6)) 486 #define UART_CTS_CHG_INT_CLR_V 0x1 487 #define UART_CTS_CHG_INT_CLR_S 6 488 /* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ 489 /*description: Set this bit to clear the dsr_chg_int_raw interrupt.*/ 490 #define UART_DSR_CHG_INT_CLR (BIT(5)) 491 #define UART_DSR_CHG_INT_CLR_M (BIT(5)) 492 #define UART_DSR_CHG_INT_CLR_V 0x1 493 #define UART_DSR_CHG_INT_CLR_S 5 494 /* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ 495 /*description: Set this bit to clear rxfifo_ovf_int_raw interrupt.*/ 496 #define UART_RXFIFO_OVF_INT_CLR (BIT(4)) 497 #define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) 498 #define UART_RXFIFO_OVF_INT_CLR_V 0x1 499 #define UART_RXFIFO_OVF_INT_CLR_S 4 500 /* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ 501 /*description: Set this bit to clear frm_err_int_raw interrupt.*/ 502 #define UART_FRM_ERR_INT_CLR (BIT(3)) 503 #define UART_FRM_ERR_INT_CLR_M (BIT(3)) 504 #define UART_FRM_ERR_INT_CLR_V 0x1 505 #define UART_FRM_ERR_INT_CLR_S 3 506 /* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ 507 /*description: Set this bit to clear parity_err_int_raw interrupt.*/ 508 #define UART_PARITY_ERR_INT_CLR (BIT(2)) 509 #define UART_PARITY_ERR_INT_CLR_M (BIT(2)) 510 #define UART_PARITY_ERR_INT_CLR_V 0x1 511 #define UART_PARITY_ERR_INT_CLR_S 2 512 /* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ 513 /*description: Set this bit to clear txfifo_empty_int_raw interrupt.*/ 514 #define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) 515 #define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) 516 #define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 517 #define UART_TXFIFO_EMPTY_INT_CLR_S 1 518 /* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ 519 /*description: Set this bit to clear the rxfifo_full_int_raw interrupt.*/ 520 #define UART_RXFIFO_FULL_INT_CLR (BIT(0)) 521 #define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) 522 #define UART_RXFIFO_FULL_INT_CLR_V 0x1 523 #define UART_RXFIFO_FULL_INT_CLR_S 0 524 525 #define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) 526 /* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ 527 /*description: The register value is the decimal part of the frequency divider's factor.*/ 528 #define UART_CLKDIV_FRAG 0x0000000F 529 #define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S)) 530 #define UART_CLKDIV_FRAG_V 0xF 531 #define UART_CLKDIV_FRAG_S 20 532 /* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */ 533 /*description: The register value is the integer part of the frequency divider's factor.*/ 534 #define UART_CLKDIV 0x000FFFFF 535 #define UART_CLKDIV_M ((UART_CLKDIV_V)<<(UART_CLKDIV_S)) 536 #define UART_CLKDIV_V 0xFFFFF 537 #define UART_CLKDIV_S 0 538 539 #define UART_AUTOBAUD_REG(i) (REG_UART_BASE(i) + 0x18) 540 /* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */ 541 /*description: when input pulse width is lower then this value igore this pulse.this 542 register is used in autobaud detect process.*/ 543 #define UART_GLITCH_FILT 0x000000FF 544 #define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S)) 545 #define UART_GLITCH_FILT_V 0xFF 546 #define UART_GLITCH_FILT_S 8 547 /* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 548 /*description: This is the enable bit for detecting baudrate.*/ 549 #define UART_AUTOBAUD_EN (BIT(0)) 550 #define UART_AUTOBAUD_EN_M (BIT(0)) 551 #define UART_AUTOBAUD_EN_V 0x1 552 #define UART_AUTOBAUD_EN_S 0 553 554 #define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) 555 /* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */ 556 /*description: This register represent the level value of the internal uart rxd signal.*/ 557 #define UART_TXD (BIT(31)) 558 #define UART_TXD_M (BIT(31)) 559 #define UART_TXD_V 0x1 560 #define UART_TXD_S 31 561 /* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */ 562 /*description: This register represent the level value of the internal uart cts signal.*/ 563 #define UART_RTSN (BIT(30)) 564 #define UART_RTSN_M (BIT(30)) 565 #define UART_RTSN_V 0x1 566 #define UART_RTSN_S 30 567 /* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */ 568 /*description: The register represent the level value of the internal uart dsr signal.*/ 569 #define UART_DTRN (BIT(29)) 570 #define UART_DTRN_M (BIT(29)) 571 #define UART_DTRN_V 0x1 572 #define UART_DTRN_S 29 573 /* UART_ST_UTX_OUT : RO ;bitpos:[27:24] ;default: 4'b0 ; */ 574 /*description: This register stores the value of transmitter's finite state 575 machine. 0:TX_IDLE 1:TX_STRT 2:TX_DAT0 3:TX_DAT1 4:TX_DAT2 5:TX_DAT3 6:TX_DAT4 7:TX_DAT5 8:TX_DAT6 9:TX_DAT7 10:TX_PRTY 11:TX_STP1 12:TX_STP2 13:TX_DL0 14:TX_DL1*/ 576 #define UART_ST_UTX_OUT 0x0000000F 577 #define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S)) 578 #define UART_ST_UTX_OUT_V 0xF 579 #define UART_ST_UTX_OUT_S 24 580 /* UART_TXFIFO_CNT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ 581 /*description: (tx_mem_cnt txfifo_cnt) stores the byte num of valid datas in 582 transmitter's fifo.tx_mem_cnt stores the 3 most significant bits txfifo_cnt stores the 8 least significant bits.*/ 583 #define UART_TXFIFO_CNT 0x000000FF 584 #define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S)) 585 #define UART_TXFIFO_CNT_V 0xFF 586 #define UART_TXFIFO_CNT_S 16 587 /* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */ 588 /*description: This register stores the level value of the internal uart rxd signal.*/ 589 #define UART_RXD (BIT(15)) 590 #define UART_RXD_M (BIT(15)) 591 #define UART_RXD_V 0x1 592 #define UART_RXD_S 15 593 /* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */ 594 /*description: This register stores the level value of the internal uart cts signal.*/ 595 #define UART_CTSN (BIT(14)) 596 #define UART_CTSN_M (BIT(14)) 597 #define UART_CTSN_V 0x1 598 #define UART_CTSN_S 14 599 /* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */ 600 /*description: This register stores the level value of the internal uart dsr signal.*/ 601 #define UART_DSRN (BIT(13)) 602 #define UART_DSRN_M (BIT(13)) 603 #define UART_DSRN_V 0x1 604 #define UART_DSRN_S 13 605 /* UART_ST_URX_OUT : RO ;bitpos:[11:8] ;default: 4'b0 ; */ 606 /*description: This register stores the value of receiver's finite state machine. 607 0:RX_IDLE 1:RX_STRT 2:RX_DAT0 3:RX_DAT1 4:RX_DAT2 5:RX_DAT3 6:RX_DAT4 7:RX_DAT5 8:RX_DAT6 9:RX_DAT7 10:RX_PRTY 11:RX_STP1 12:RX_STP2 13:RX_DL1*/ 608 #define UART_ST_URX_OUT 0x0000000F 609 #define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S)) 610 #define UART_ST_URX_OUT_V 0xF 611 #define UART_ST_URX_OUT_S 8 612 /* UART_RXFIFO_CNT : RO ;bitpos:[7:0] ;default: 8'b0 ; */ 613 /*description: (rx_mem_cnt rxfifo_cnt) stores the byte num of valid datas in 614 receiver's fifo. rx_mem_cnt register stores the 3 most significant bits rxfifo_cnt stores the 8 least significant bits.*/ 615 #define UART_RXFIFO_CNT 0x000000FF 616 #define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S)) 617 #define UART_RXFIFO_CNT_V 0xFF 618 #define UART_RXFIFO_CNT_S 0 619 620 #define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) 621 /* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */ 622 /*description: This register is used to select the clock.1.apb clock 0:ref_tick*/ 623 #define UART_TICK_REF_ALWAYS_ON (BIT(27)) 624 #define UART_TICK_REF_ALWAYS_ON_M (BIT(27)) 625 #define UART_TICK_REF_ALWAYS_ON_V 0x1 626 #define UART_TICK_REF_ALWAYS_ON_S 27 627 /* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */ 628 /*description: 1.receiver stops storing data int fifo when data is wrong. 629 0.receiver stores the data even if the received data is wrong.*/ 630 #define UART_ERR_WR_MASK (BIT(26)) 631 #define UART_ERR_WR_MASK_M (BIT(26)) 632 #define UART_ERR_WR_MASK_V 0x1 633 #define UART_ERR_WR_MASK_S 26 634 /* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */ 635 /*description: 1.force clock on for registers.support clock only when write registers*/ 636 #define UART_CLK_EN (BIT(25)) 637 #define UART_CLK_EN_M (BIT(25)) 638 #define UART_CLK_EN_V 0x1 639 #define UART_CLK_EN_S 25 640 /* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */ 641 /*description: Set this bit to inverse the level value of uart dtr signal.*/ 642 #define UART_DTR_INV (BIT(24)) 643 #define UART_DTR_INV_M (BIT(24)) 644 #define UART_DTR_INV_V 0x1 645 #define UART_DTR_INV_S 24 646 /* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */ 647 /*description: Set this bit to inverse the level value of uart rts signal.*/ 648 #define UART_RTS_INV (BIT(23)) 649 #define UART_RTS_INV_M (BIT(23)) 650 #define UART_RTS_INV_V 0x1 651 #define UART_RTS_INV_S 23 652 /* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */ 653 /*description: Set this bit to inverse the level value of uart txd signal.*/ 654 #define UART_TXD_INV (BIT(22)) 655 #define UART_TXD_INV_M (BIT(22)) 656 #define UART_TXD_INV_V 0x1 657 #define UART_TXD_INV_S 22 658 /* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */ 659 /*description: Set this bit to inverse the level value of uart dsr signal.*/ 660 #define UART_DSR_INV (BIT(21)) 661 #define UART_DSR_INV_M (BIT(21)) 662 #define UART_DSR_INV_V 0x1 663 #define UART_DSR_INV_S 21 664 /* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */ 665 /*description: Set this bit to inverse the level value of uart cts signal.*/ 666 #define UART_CTS_INV (BIT(20)) 667 #define UART_CTS_INV_M (BIT(20)) 668 #define UART_CTS_INV_V 0x1 669 #define UART_CTS_INV_S 20 670 /* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */ 671 /*description: Set this bit to inverse the level value of uart rxd signal.*/ 672 #define UART_RXD_INV (BIT(19)) 673 #define UART_RXD_INV_M (BIT(19)) 674 #define UART_RXD_INV_V 0x1 675 #define UART_RXD_INV_S 19 676 /* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */ 677 /*description: Set this bit to reset uart transmitter's fifo.*/ 678 #define UART_TXFIFO_RST (BIT(18)) 679 #define UART_TXFIFO_RST_M (BIT(18)) 680 #define UART_TXFIFO_RST_V 0x1 681 #define UART_TXFIFO_RST_S 18 682 /* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */ 683 /*description: Set this bit to reset uart receiver's fifo.*/ 684 #define UART_RXFIFO_RST (BIT(17)) 685 #define UART_RXFIFO_RST_M (BIT(17)) 686 #define UART_RXFIFO_RST_V 0x1 687 #define UART_RXFIFO_RST_S 17 688 /* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ 689 /*description: Set this bit to enable irda protocol.*/ 690 #define UART_IRDA_EN (BIT(16)) 691 #define UART_IRDA_EN_M (BIT(16)) 692 #define UART_IRDA_EN_V 0x1 693 #define UART_IRDA_EN_S 16 694 /* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ 695 /*description: Set this bit to enable transmitter's flow control function.*/ 696 #define UART_TX_FLOW_EN (BIT(15)) 697 #define UART_TX_FLOW_EN_M (BIT(15)) 698 #define UART_TX_FLOW_EN_V 0x1 699 #define UART_TX_FLOW_EN_S 15 700 /* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */ 701 /*description: Set this bit to enable uart loopback test mode.*/ 702 #define UART_LOOPBACK (BIT(14)) 703 #define UART_LOOPBACK_M (BIT(14)) 704 #define UART_LOOPBACK_V 0x1 705 #define UART_LOOPBACK_S 14 706 /* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ 707 /*description: Set this bit to inverse the level value of irda receiver's level.*/ 708 #define UART_IRDA_RX_INV (BIT(13)) 709 #define UART_IRDA_RX_INV_M (BIT(13)) 710 #define UART_IRDA_RX_INV_V 0x1 711 #define UART_IRDA_RX_INV_S 13 712 /* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */ 713 /*description: Set this bit to inverse the level value of irda transmitter's level.*/ 714 #define UART_IRDA_TX_INV (BIT(12)) 715 #define UART_IRDA_TX_INV_M (BIT(12)) 716 #define UART_IRDA_TX_INV_V 0x1 717 #define UART_IRDA_TX_INV_S 12 718 /* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */ 719 /*description: 1.the irda transmitter's 11th bit is the same to the 10th bit. 720 0.set irda transmitter's 11th bit to 0.*/ 721 #define UART_IRDA_WCTL (BIT(11)) 722 #define UART_IRDA_WCTL_M (BIT(11)) 723 #define UART_IRDA_WCTL_V 0x1 724 #define UART_IRDA_WCTL_S 11 725 /* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ 726 /*description: This is the start enable bit for irda transmitter.*/ 727 #define UART_IRDA_TX_EN (BIT(10)) 728 #define UART_IRDA_TX_EN_M (BIT(10)) 729 #define UART_IRDA_TX_EN_V 0x1 730 #define UART_IRDA_TX_EN_S 10 731 /* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */ 732 /*description: Set this bit to enable irda loopback mode.*/ 733 #define UART_IRDA_DPLX (BIT(9)) 734 #define UART_IRDA_DPLX_M (BIT(9)) 735 #define UART_IRDA_DPLX_V 0x1 736 #define UART_IRDA_DPLX_S 9 737 /* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ 738 /*description: Set this bit to enbale transmitter to send 0 when the process 739 of sending data is done.*/ 740 #define UART_TXD_BRK (BIT(8)) 741 #define UART_TXD_BRK_M (BIT(8)) 742 #define UART_TXD_BRK_V 0x1 743 #define UART_TXD_BRK_S 8 744 /* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */ 745 /*description: This register is used to configure the software dtr signal which 746 is used in software flow control..*/ 747 #define UART_SW_DTR (BIT(7)) 748 #define UART_SW_DTR_M (BIT(7)) 749 #define UART_SW_DTR_V 0x1 750 #define UART_SW_DTR_S 7 751 /* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */ 752 /*description: This register is used to configure the software rts signal which 753 is used in software flow control.*/ 754 #define UART_SW_RTS (BIT(6)) 755 #define UART_SW_RTS_M (BIT(6)) 756 #define UART_SW_RTS_V 0x1 757 #define UART_SW_RTS_S 6 758 /* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */ 759 /*description: This register is used to set the length of stop bit. 1:1bit 2:1.5bits 3:2bits*/ 760 #define UART_STOP_BIT_NUM 0x00000003 761 #define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S)) 762 #define UART_STOP_BIT_NUM_V 0x3 763 #define UART_STOP_BIT_NUM_S 4 764 /* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ 765 /*description: This registe is used to set the length of data: 0:5bits 1:6bits 2:7bits 3:8bits*/ 766 #define UART_BIT_NUM 0x00000003 767 #define UART_BIT_NUM_M ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S)) 768 #define UART_BIT_NUM_V 0x3 769 #define UART_BIT_NUM_S 2 770 /* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 771 /*description: Set this bit to enable uart parity check.*/ 772 #define UART_PARITY_EN (BIT(1)) 773 #define UART_PARITY_EN_M (BIT(1)) 774 #define UART_PARITY_EN_V 0x1 775 #define UART_PARITY_EN_S 1 776 /* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */ 777 /*description: This register is used to configure the parity check mode. 0:even 1:odd*/ 778 #define UART_PARITY (BIT(0)) 779 #define UART_PARITY_M (BIT(0)) 780 #define UART_PARITY_V 0x1 781 #define UART_PARITY_S 0 782 783 #define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) 784 /* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ 785 /*description: This is the enble bit for uart receiver's timeout function.*/ 786 #define UART_RX_TOUT_EN (BIT(31)) 787 #define UART_RX_TOUT_EN_M (BIT(31)) 788 #define UART_RX_TOUT_EN_V 0x1 789 #define UART_RX_TOUT_EN_S 31 790 /* UART_RX_TOUT_THRHD : R/W ;bitpos:[30:24] ;default: 7'b0 ; */ 791 /*description: This register is used to configure the timeout value for uart 792 receiver receiving a byte.*/ 793 #define UART_RX_TOUT_THRHD 0x0000007F 794 #define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S)) 795 #define UART_RX_TOUT_THRHD_V 0x7F 796 #define UART_RX_TOUT_THRHD_S 24 797 /* UART_RX_FLOW_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ 798 /*description: This is the flow enable bit for uart receiver. 1:choose software 799 flow control with configuring sw_rts signal*/ 800 #define UART_RX_FLOW_EN (BIT(23)) 801 #define UART_RX_FLOW_EN_M (BIT(23)) 802 #define UART_RX_FLOW_EN_V 0x1 803 #define UART_RX_FLOW_EN_S 23 804 /* UART_RX_FLOW_THRHD : R/W ;bitpos:[22:16] ;default: 7'h0 ; */ 805 /*description: when receiver receives more data than its threshold value. 806 receiver produce signal to tell the transmitter stop transferring data. the threshold value is (rx_flow_thrhd_h3 rx_flow_thrhd).*/ 807 #define UART_RX_FLOW_THRHD 0x0000007F 808 #define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S)) 809 #define UART_RX_FLOW_THRHD_V 0x7F 810 #define UART_RX_FLOW_THRHD_S 16 811 /* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[14:8] ;default: 7'h60 ; */ 812 /*description: when the data amount in transmitter fifo is less than its threshold 813 value. it will produce txfifo_empty_int_raw interrupt. the threshold value is (tx_mem_empty_thrhd txfifo_empty_thrhd)*/ 814 #define UART_TXFIFO_EMPTY_THRHD 0x0000007F 815 #define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S)) 816 #define UART_TXFIFO_EMPTY_THRHD_V 0x7F 817 #define UART_TXFIFO_EMPTY_THRHD_S 8 818 /* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[6:0] ;default: 7'h60 ; */ 819 /*description: When receiver receives more data than its threshold value.receiver 820 will produce rxfifo_full_int_raw interrupt.the threshold value is (rx_flow_thrhd_h3 rxfifo_full_thrhd).*/ 821 #define UART_RXFIFO_FULL_THRHD 0x0000007F 822 #define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S)) 823 #define UART_RXFIFO_FULL_THRHD_V 0x7F 824 #define UART_RXFIFO_FULL_THRHD_S 0 825 826 #define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) 827 /* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ 828 /*description: This register stores the value of the minimum duration time for 829 the low level pulse. it is used in baudrate-detect process.*/ 830 #define UART_LOWPULSE_MIN_CNT 0x000FFFFF 831 #define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S)) 832 #define UART_LOWPULSE_MIN_CNT_V 0xFFFFF 833 #define UART_LOWPULSE_MIN_CNT_S 0 834 835 #define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) 836 /* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ 837 /*description: This register stores the value of the maxinum duration time 838 for the high level pulse. it is used in baudrate-detect process.*/ 839 #define UART_HIGHPULSE_MIN_CNT 0x000FFFFF 840 #define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S)) 841 #define UART_HIGHPULSE_MIN_CNT_V 0xFFFFF 842 #define UART_HIGHPULSE_MIN_CNT_S 0 843 844 #define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) 845 /* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ 846 /*description: This register stores the count of rxd edge change. it is used 847 in baudrate-detect process.*/ 848 #define UART_RXD_EDGE_CNT 0x000003FF 849 #define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S)) 850 #define UART_RXD_EDGE_CNT_V 0x3FF 851 #define UART_RXD_EDGE_CNT_S 0 852 853 #define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) 854 /* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */ 855 /*description: Set this bit to send xoff char. it is cleared by hardware automatically.*/ 856 #define UART_SEND_XOFF (BIT(5)) 857 #define UART_SEND_XOFF_M (BIT(5)) 858 #define UART_SEND_XOFF_V 0x1 859 #define UART_SEND_XOFF_S 5 860 /* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */ 861 /*description: Set this bit to send xon char. it is cleared by hardware automatically.*/ 862 #define UART_SEND_XON (BIT(4)) 863 #define UART_SEND_XON_M (BIT(4)) 864 #define UART_SEND_XON_V 0x1 865 #define UART_SEND_XON_S 4 866 /* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */ 867 /*description: Set this bit to set ctsn to enable the transmitter to go on sending data.*/ 868 #define UART_FORCE_XOFF (BIT(3)) 869 #define UART_FORCE_XOFF_M (BIT(3)) 870 #define UART_FORCE_XOFF_V 0x1 871 #define UART_FORCE_XOFF_S 3 872 /* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */ 873 /*description: Set this bit to clear ctsn to stop the transmitter from sending data.*/ 874 #define UART_FORCE_XON (BIT(2)) 875 #define UART_FORCE_XON_M (BIT(2)) 876 #define UART_FORCE_XON_V 0x1 877 #define UART_FORCE_XON_S 2 878 /* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */ 879 /*description: Set this bit to remove flow control char from the received data.*/ 880 #define UART_XONOFF_DEL (BIT(1)) 881 #define UART_XONOFF_DEL_M (BIT(1)) 882 #define UART_XONOFF_DEL_V 0x1 883 #define UART_XONOFF_DEL_S 1 884 /* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 885 /*description: Set this bit to enable software flow control. it is used with 886 register sw_xon or sw_xoff .*/ 887 #define UART_SW_FLOW_CON_EN (BIT(0)) 888 #define UART_SW_FLOW_CON_EN_M (BIT(0)) 889 #define UART_SW_FLOW_CON_EN_V 0x1 890 #define UART_SW_FLOW_CON_EN_S 0 891 892 #define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) 893 /* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ 894 /*description: When the input rxd edge changes more than this register value. 895 the uart is active from light sleeping mode.*/ 896 #define UART_ACTIVE_THRESHOLD 0x000003FF 897 #define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S)) 898 #define UART_ACTIVE_THRESHOLD_V 0x3FF 899 #define UART_ACTIVE_THRESHOLD_S 0 900 901 #define UART_SWFC_CONF_REG(i) (REG_UART_BASE(i) + 0x3C) 902 /* UART_XOFF_CHAR : R/W ;bitpos:[31:24] ;default: 8'h13 ; */ 903 /*description: This register stores the xoff flow control char.*/ 904 #define UART_XOFF_CHAR 0x000000FF 905 #define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S)) 906 #define UART_XOFF_CHAR_V 0xFF 907 #define UART_XOFF_CHAR_S 24 908 /* UART_XON_CHAR : R/W ;bitpos:[23:16] ;default: 8'h11 ; */ 909 /*description: This register stores the xon flow control char.*/ 910 #define UART_XON_CHAR 0x000000FF 911 #define UART_XON_CHAR_M ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S)) 912 #define UART_XON_CHAR_V 0xFF 913 #define UART_XON_CHAR_S 16 914 /* UART_XOFF_THRESHOLD : R/W ;bitpos:[15:8] ;default: 8'he0 ; */ 915 /*description: When the data amount in receiver's fifo is less than this register 916 value. it will send a xon char with uart_sw_flow_con_en set to 1.*/ 917 #define UART_XOFF_THRESHOLD 0x000000FF 918 #define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S)) 919 #define UART_XOFF_THRESHOLD_V 0xFF 920 #define UART_XOFF_THRESHOLD_S 8 921 /* UART_XON_THRESHOLD : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ 922 /*description: when the data amount in receiver's fifo is more than this register 923 value. it will send a xoff char with uart_sw_flow_con_en set to 1.*/ 924 #define UART_XON_THRESHOLD 0x000000FF 925 #define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S)) 926 #define UART_XON_THRESHOLD_V 0xFF 927 #define UART_XON_THRESHOLD_S 0 928 929 #define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x40) 930 /* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */ 931 /*description: This register is used to configure the num of 0 send after the 932 process of sending data is done. it is active when txd_brk is set to 1.*/ 933 #define UART_TX_BRK_NUM 0x000000FF 934 #define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S)) 935 #define UART_TX_BRK_NUM_V 0xFF 936 #define UART_TX_BRK_NUM_S 20 937 /* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */ 938 /*description: This register is used to configure the duration time between transfers.*/ 939 #define UART_TX_IDLE_NUM 0x000003FF 940 #define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S)) 941 #define UART_TX_IDLE_NUM_V 0x3FF 942 #define UART_TX_IDLE_NUM_S 10 943 /* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ 944 /*description: when receiver takes more time than this register value to receive 945 a byte data. it will produce frame end signal for uhci to stop receiving data.*/ 946 #define UART_RX_IDLE_THRHD 0x000003FF 947 #define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S)) 948 #define UART_RX_IDLE_THRHD_V 0x3FF 949 #define UART_RX_IDLE_THRHD_S 0 950 951 #define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x44) 952 /* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ 953 /*description: This register is used to delay the transmitter's internal data signal.*/ 954 #define UART_RS485_TX_DLY_NUM 0x0000000F 955 #define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S)) 956 #define UART_RS485_TX_DLY_NUM_V 0xF 957 #define UART_RS485_TX_DLY_NUM_S 6 958 /* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */ 959 /*description: This register is used to delay the receiver's internal data signal.*/ 960 #define UART_RS485_RX_DLY_NUM (BIT(5)) 961 #define UART_RS485_RX_DLY_NUM_M (BIT(5)) 962 #define UART_RS485_RX_DLY_NUM_V 0x1 963 #define UART_RS485_RX_DLY_NUM_S 5 964 /* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ 965 /*description: 1: enable rs485's transmitter to send data when rs485's receiver 966 is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/ 967 #define UART_RS485RXBY_TX_EN (BIT(4)) 968 #define UART_RS485RXBY_TX_EN_M (BIT(4)) 969 #define UART_RS485RXBY_TX_EN_V 0x1 970 #define UART_RS485RXBY_TX_EN_S 4 971 /* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ 972 /*description: Set this bit to enable loopback transmitter's output data signal 973 to receiver's input data signal.*/ 974 #define UART_RS485TX_RX_EN (BIT(3)) 975 #define UART_RS485TX_RX_EN_M (BIT(3)) 976 #define UART_RS485TX_RX_EN_V 0x1 977 #define UART_RS485TX_RX_EN_S 3 978 /* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ 979 /*description: Set this bit to delay the stop bit by 1 bit.*/ 980 #define UART_DL1_EN (BIT(2)) 981 #define UART_DL1_EN_M (BIT(2)) 982 #define UART_DL1_EN_V 0x1 983 #define UART_DL1_EN_S 2 984 /* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ 985 /*description: Set this bit to delay the stop bit by 1 bit.*/ 986 #define UART_DL0_EN (BIT(1)) 987 #define UART_DL0_EN_M (BIT(1)) 988 #define UART_DL0_EN_V 0x1 989 #define UART_DL0_EN_S 1 990 /* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ 991 /*description: Set this bit to choose rs485 mode.*/ 992 #define UART_RS485_EN (BIT(0)) 993 #define UART_RS485_EN_M (BIT(0)) 994 #define UART_RS485_EN_V 0x1 995 #define UART_RS485_EN_S 0 996 997 #define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x48) 998 /* UART_PRE_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ 999 /*description: This register is used to configure the idle duration time before 1000 the first at_cmd is received by receiver. when the the duration is less than this register value it will not take the next data received as at_cmd char.*/ 1001 #define UART_PRE_IDLE_NUM 0x00FFFFFF 1002 #define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S)) 1003 #define UART_PRE_IDLE_NUM_V 0xFFFFFF 1004 #define UART_PRE_IDLE_NUM_S 0 1005 1006 #define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x4c) 1007 /* UART_POST_IDLE_NUM : R/W ;bitpos:[23:0] ;default: 24'h186a00 ; */ 1008 /*description: This register is used to configure the duration time between 1009 the last at_cmd and the next data. when the duration is less than this register value it will not take the previous data as at_cmd char.*/ 1010 #define UART_POST_IDLE_NUM 0x00FFFFFF 1011 #define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S)) 1012 #define UART_POST_IDLE_NUM_V 0xFFFFFF 1013 #define UART_POST_IDLE_NUM_S 0 1014 1015 #define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x50) 1016 /* UART_RX_GAP_TOUT : R/W ;bitpos:[23:0] ;default: 24'h1e00 ; */ 1017 /*description: This register is used to configure the duration time between 1018 the at_cmd chars. when the duration time is less than this register value it will not take the datas as continous at_cmd chars.*/ 1019 #define UART_RX_GAP_TOUT 0x00FFFFFF 1020 #define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S)) 1021 #define UART_RX_GAP_TOUT_V 0xFFFFFF 1022 #define UART_RX_GAP_TOUT_S 0 1023 1024 #define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x54) 1025 /* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ 1026 /*description: This register is used to configure the num of continous at_cmd 1027 chars received by receiver.*/ 1028 #define UART_CHAR_NUM 0x000000FF 1029 #define UART_CHAR_NUM_M ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S)) 1030 #define UART_CHAR_NUM_V 0xFF 1031 #define UART_CHAR_NUM_S 8 1032 /* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */ 1033 /*description: This register is used to configure the content of at_cmd char.*/ 1034 #define UART_AT_CMD_CHAR 0x000000FF 1035 #define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S)) 1036 #define UART_AT_CMD_CHAR_V 0xFF 1037 #define UART_AT_CMD_CHAR_S 0 1038 1039 #define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x58) 1040 /* UART_TX_MEM_EMPTY_THRHD : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ 1041 /*description: refer to txfifo_empty_thrhd 's describtion.*/ 1042 #define UART_TX_MEM_EMPTY_THRHD 0x00000007 1043 #define UART_TX_MEM_EMPTY_THRHD_M ((UART_TX_MEM_EMPTY_THRHD_V)<<(UART_TX_MEM_EMPTY_THRHD_S)) 1044 #define UART_TX_MEM_EMPTY_THRHD_V 0x7 1045 #define UART_TX_MEM_EMPTY_THRHD_S 28 1046 /* UART_RX_MEM_FULL_THRHD : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ 1047 /*description: refer to the rxfifo_full_thrhd's describtion.*/ 1048 #define UART_RX_MEM_FULL_THRHD 0x00000007 1049 #define UART_RX_MEM_FULL_THRHD_M ((UART_RX_MEM_FULL_THRHD_V)<<(UART_RX_MEM_FULL_THRHD_S)) 1050 #define UART_RX_MEM_FULL_THRHD_V 0x7 1051 #define UART_RX_MEM_FULL_THRHD_S 25 1052 /* UART_XOFF_THRESHOLD_H2 : R/W ;bitpos:[24:23] ;default: 2'h0 ; */ 1053 /*description: refer to the uart_xoff_threshold's describtion.*/ 1054 #define UART_XOFF_THRESHOLD_H2 0x00000003 1055 #define UART_XOFF_THRESHOLD_H2_M ((UART_XOFF_THRESHOLD_H2_V)<<(UART_XOFF_THRESHOLD_H2_S)) 1056 #define UART_XOFF_THRESHOLD_H2_V 0x3 1057 #define UART_XOFF_THRESHOLD_H2_S 23 1058 /* UART_XON_THRESHOLD_H2 : R/W ;bitpos:[22:21] ;default: 2'h0 ; */ 1059 /*description: refer to the uart_xon_threshold's describtion.*/ 1060 #define UART_XON_THRESHOLD_H2 0x00000003 1061 #define UART_XON_THRESHOLD_H2_M ((UART_XON_THRESHOLD_H2_V)<<(UART_XON_THRESHOLD_H2_S)) 1062 #define UART_XON_THRESHOLD_H2_V 0x3 1063 #define UART_XON_THRESHOLD_H2_S 21 1064 /* UART_RX_TOUT_THRHD_H3 : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ 1065 /*description: refer to the rx_tout_thrhd's describtion.*/ 1066 #define UART_RX_TOUT_THRHD_H3 0x00000007 1067 #define UART_RX_TOUT_THRHD_H3_M ((UART_RX_TOUT_THRHD_H3_V)<<(UART_RX_TOUT_THRHD_H3_S)) 1068 #define UART_RX_TOUT_THRHD_H3_V 0x7 1069 #define UART_RX_TOUT_THRHD_H3_S 18 1070 /* UART_RX_FLOW_THRHD_H3 : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ 1071 /*description: refer to the rx_flow_thrhd's describtion.*/ 1072 #define UART_RX_FLOW_THRHD_H3 0x00000007 1073 #define UART_RX_FLOW_THRHD_H3_M ((UART_RX_FLOW_THRHD_H3_V)<<(UART_RX_FLOW_THRHD_H3_S)) 1074 #define UART_RX_FLOW_THRHD_H3_V 0x7 1075 #define UART_RX_FLOW_THRHD_H3_S 15 1076 /* UART_TX_SIZE : R/W ;bitpos:[10:7] ;default: 4'h1 ; */ 1077 /*description: This register is used to configure the amount of mem allocated 1078 to transmitter's fifo.the default byte num is 128.*/ 1079 #define UART_TX_SIZE 0x0000000F 1080 #define UART_TX_SIZE_M ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S)) 1081 #define UART_TX_SIZE_V 0xF 1082 #define UART_TX_SIZE_S 7 1083 /* UART_RX_SIZE : R/W ;bitpos:[6:3] ;default: 4'h1 ; */ 1084 /*description: This register is used to configure the amount of mem allocated 1085 to receiver's fifo. the default byte num is 128.*/ 1086 #define UART_RX_SIZE 0x0000000F 1087 #define UART_RX_SIZE_M ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S)) 1088 #define UART_RX_SIZE_V 0xF 1089 #define UART_RX_SIZE_S 3 1090 /* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ 1091 /*description: Set this bit to power down mem.when reg_mem_pd registers in 1092 the 3 uarts are all set to 1 mem will enter low power mode.*/ 1093 #define UART_MEM_PD (BIT(0)) 1094 #define UART_MEM_PD_M (BIT(0)) 1095 #define UART_MEM_PD_V 0x1 1096 #define UART_MEM_PD_S 0 1097 1098 #define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x5c) 1099 /* UART_MEM_TX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ 1100 /*description: */ 1101 #define UART_MEM_TX_STATUS 0x00FFFFFF 1102 #define UART_MEM_TX_STATUS_M ((UART_MEM_TX_STATUS_V)<<(UART_MEM_TX_STATUS_S)) 1103 #define UART_MEM_TX_STATUS_V 0xFFFFFF 1104 #define UART_MEM_TX_STATUS_S 0 1105 1106 #define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x60) 1107 /* UART_MEM_RX_STATUS : RO ;bitpos:[23:0] ;default: 24'h0 ; */ 1108 /*description: This register stores the current uart rx mem read address 1109 and rx mem write address */ 1110 #define UART_MEM_RX_STATUS 0x00FFFFFF 1111 #define UART_MEM_RX_STATUS_M ((UART_MEM_RX_STATUS_V)<<(UART_MEM_RX_STATUS_S)) 1112 #define UART_MEM_RX_STATUS_V 0xFFFFFF 1113 #define UART_MEM_RX_STATUS_S 0 1114 /* UART_MEM_RX_RD_ADDR : RO ;bitpos:[12:2] ;default: 11'h0 ; */ 1115 /*description: This register stores the rx mem read address */ 1116 #define UART_MEM_RX_RD_ADDR 0x000007FF 1117 #define UART_MEM_RX_RD_ADDR_M ((UART_MEM_RX_RD_ADDR_V)<<(UART_MEM_RX_RD_ADDR_S)) 1118 #define UART_MEM_RX_RD_ADDR_V (0x7FF) 1119 #define UART_MEM_RX_RD_ADDR_S (2) 1120 /* UART_MEM_RX_WR_ADDR : RO ;bitpos:[23:13] ;default: 11'h0 ; */ 1121 /*description: This register stores the rx mem write address */ 1122 #define UART_MEM_RX_WR_ADDR 0x000007FF 1123 #define UART_MEM_RX_WR_ADDR_M ((UART_MEM_RX_WR_ADDR_V)<<(UART_MEM_RX_WR_ADDR_S)) 1124 #define UART_MEM_RX_WR_ADDR_V (0x7FF) 1125 #define UART_MEM_RX_WR_ADDR_S (13) 1126 1127 #define UART_MEM_CNT_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) 1128 /* UART_TX_MEM_CNT : RO ;bitpos:[5:3] ;default: 3'b0 ; */ 1129 /*description: refer to the txfifo_cnt's describtion.*/ 1130 #define UART_TX_MEM_CNT 0x00000007 1131 #define UART_TX_MEM_CNT_M ((UART_TX_MEM_CNT_V)<<(UART_TX_MEM_CNT_S)) 1132 #define UART_TX_MEM_CNT_V 0x7 1133 #define UART_TX_MEM_CNT_S 3 1134 /* UART_RX_MEM_CNT : RO ;bitpos:[2:0] ;default: 3'b0 ; */ 1135 /*description: refer to the rxfifo_cnt's describtion.*/ 1136 #define UART_RX_MEM_CNT 0x00000007 1137 #define UART_RX_MEM_CNT_M ((UART_RX_MEM_CNT_V)<<(UART_RX_MEM_CNT_S)) 1138 #define UART_RX_MEM_CNT_V 0x7 1139 #define UART_RX_MEM_CNT_S 0 1140 1141 #define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x68) 1142 /* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ 1143 /*description: This register stores the count of rxd posedge edge. it is used 1144 in boudrate-detect process.*/ 1145 #define UART_POSEDGE_MIN_CNT 0x000FFFFF 1146 #define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S)) 1147 #define UART_POSEDGE_MIN_CNT_V 0xFFFFF 1148 #define UART_POSEDGE_MIN_CNT_S 0 1149 1150 #define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x6c) 1151 /* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */ 1152 /*description: This register stores the count of rxd negedge edge. it is used 1153 in boudrate-detect process.*/ 1154 #define UART_NEGEDGE_MIN_CNT 0x000FFFFF 1155 #define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S)) 1156 #define UART_NEGEDGE_MIN_CNT_V 0xFFFFF 1157 #define UART_NEGEDGE_MIN_CNT_S 0 1158 1159 #define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x78) 1160 /* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h15122500 ; */ 1161 /*description: */ 1162 #define UART_DATE 0xFFFFFFFF 1163 #define UART_DATE_M ((UART_DATE_V)<<(UART_DATE_S)) 1164 #define UART_DATE_V 0xFFFFFFFF 1165 #define UART_DATE_S 0 1166 1167 #define UART_ID_REG(i) (REG_UART_BASE(i) + 0x7C) 1168 /* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */ 1169 /*description: */ 1170 #define UART_ID 0xFFFFFFFF 1171 #define UART_ID_M ((UART_ID_V)<<(UART_ID_S)) 1172 #define UART_ID_V 0xFFFFFFFF 1173 #define UART_ID_S 0 1174 1175 1176 1177 1178 #endif /*__UART_REG_H__ */ 1179